Set RTS Watermarks dependend of rx-buffersizeteensy4-core
| @@ -42,8 +42,8 @@ | |||
| #ifndef SERIAL1_RX_BUFFER_SIZE | |||
| #define SERIAL1_RX_BUFFER_SIZE 64 // number of incoming bytes to buffer | |||
| #endif | |||
| #define RTS_HIGH_WATERMARK 40 // RTS requests sender to pause | |||
| #define RTS_LOW_WATERMARK 26 // RTS allows sender to resume | |||
| #define RTS_HIGH_WATERMARK (SERIAL1_RX_BUFFER_SIZE-24) // RTS requests sender to pause | |||
| #define RTS_LOW_WATERMARK (SERIAL1_RX_BUFFER_SIZE-38) // RTS allows sender to resume | |||
| #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest | |||
| @@ -42,8 +42,8 @@ | |||
| #ifndef SERIAL2_RX_BUFFER_SIZE | |||
| #define SERIAL2_RX_BUFFER_SIZE 64 // number of incoming bytes to buffer | |||
| #endif | |||
| #define RTS_HIGH_WATERMARK 40 // RTS requests sender to pause | |||
| #define RTS_LOW_WATERMARK 26 // RTS allows sender to resume | |||
| #define RTS_HIGH_WATERMARK (SERIAL2_RX_BUFFER_SIZE-24) // RTS requests sender to pause | |||
| #define RTS_LOW_WATERMARK (SERIAL2_RX_BUFFER_SIZE-38) // RTS allows sender to resume | |||
| #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest | |||
| //////////////////////////////////////////////////////////////// | |||
| @@ -42,8 +42,8 @@ | |||
| #ifndef SERIAL3_RX_BUFFER_SIZE | |||
| #define SERIAL3_RX_BUFFER_SIZE 64 // number of incoming bytes to buffer | |||
| #endif | |||
| #define RTS_HIGH_WATERMARK 40 // RTS requests sender to pause | |||
| #define RTS_LOW_WATERMARK 26 // RTS allows sender to resume | |||
| #define RTS_HIGH_WATERMARK (SERIAL3_RX_BUFFER_SIZE-24) // RTS requests sender to pause | |||
| #define RTS_LOW_WATERMARK (SERIAL3_RX_BUFFER_SIZE-38) // RTS allows sender to resume | |||
| #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest | |||
| @@ -44,8 +44,8 @@ | |||
| #ifndef SERIAL4_RX_BUFFER_SIZE | |||
| #define SERIAL4_RX_BUFFER_SIZE 64 // number of incoming bytes to buffer | |||
| #endif | |||
| #define RTS_HIGH_WATERMARK 40 // RTS requests sender to pause | |||
| #define RTS_LOW_WATERMARK 26 // RTS allows sender to resume | |||
| #define RTS_HIGH_WATERMARK (SERIAL4_RX_BUFFER_SIZE-24) // RTS requests sender to pause | |||
| #define RTS_LOW_WATERMARK (SERIAL4_RX_BUFFER_SIZE-38) // RTS allows sender to resume | |||
| #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest | |||
| @@ -44,8 +44,8 @@ | |||
| #ifndef SERIAL5_RX_BUFFER_SIZE | |||
| #define SERIAL5_RX_BUFFER_SIZE 64 // number of incoming bytes to buffer | |||
| #endif | |||
| #define RTS_HIGH_WATERMARK 40 // RTS requests sender to pause | |||
| #define RTS_LOW_WATERMARK 26 // RTS allows sender to resume | |||
| #define RTS_HIGH_WATERMARK (SERIAL5_RX_BUFFER_SIZE-24) // RTS requests sender to pause | |||
| #define RTS_LOW_WATERMARK (SERIAL5_RX_BUFFER_SIZE-38) // RTS allows sender to resume | |||
| #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest | |||
| @@ -44,8 +44,8 @@ | |||
| #ifndef SERIAL6_RX_BUFFER_SIZE | |||
| #define SERIAL6_RX_BUFFER_SIZE 64 // number of incoming bytes to buffer | |||
| #endif | |||
| #define RTS_HIGH_WATERMARK 40 // RTS requests sender to pause | |||
| #define RTS_LOW_WATERMARK 26 // RTS allows sender to resume | |||
| #define RTS_HIGH_WATERMARK (SERIAL6_RX_BUFFER_SIZE-24) // RTS requests sender to pause | |||
| #define RTS_LOW_WATERMARK (SERIAL6_RX_BUFFER_SIZE-38) // RTS allows sender to resume | |||
| #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest | |||
| @@ -52,8 +52,8 @@ | |||
| #ifndef SERIAL6_RX_BUFFER_SIZE | |||
| #define SERIAL6_RX_BUFFER_SIZE 64 // number of incoming bytes to buffer | |||
| #endif | |||
| #define RTS_HIGH_WATERMARK 40 // RTS requests sender to pause | |||
| #define RTS_LOW_WATERMARK 26 // RTS allows sender to resume | |||
| #define RTS_HIGH_WATERMARK (SERIAL6_RX_BUFFER_SIZE-24) // RTS requests sender to pause | |||
| #define RTS_LOW_WATERMARK (SERIAL6_RX_BUFFER_SIZE-38) // RTS allows sender to resume | |||
| #define IRQ_PRIORITY 64 // 0 = highest priority, 255 = lowest | |||