Transmit only polling HardwareSerial on imxrt

teensy4/HardwareSerial.cpp

@@ -0,0 +1,159 @@
+
+#include "HardwareSerial.h"
+
+#include "debug/printf.h"
+
+/*typedef struct {
+        const uint32_t VERID;
+        const uint32_t PARAM;
+        volatile uint32_t GLOBAL;
+        volatile uint32_t PINCFG;
+        volatile uint32_t BAUD;
+        volatile uint32_t STAT;
+        volatile uint32_t CTRL;
+        volatile uint32_t DATA;
+        volatile uint32_t MATCH;
+        volatile uint32_t MODIR;
+        volatile uint32_t FIFO;
+        volatile uint32_t WATER;
+} IMXRT_LPUART_t; */
+
+#define UART_CLOCK 24000000
+
+void HardwareSerial::begin(uint32_t baud, uint8_t format)
+{
+	//printf("HardwareSerial begin\n");
+	float base = (float)UART_CLOCK / (float)baud;
+	float besterr = 1e20;
+	int bestdiv = 1;
+	int bestosr = 4;
+	for (int osr=4; osr <= 32; osr++) {
+		float div = base / (float)osr;
+		int divint = (int)(div + 0.5f);
+		if (divint < 1) divint = 1;
+		else if (divint > 8191) divint = 8191;
+		float err = ((float)divint - div) / div;
+		if (err < 0.0f) err = -err;
+		if (err <= besterr) {
+			besterr = err;
+			bestdiv = divint;
+			bestosr = osr;
+		}
+	}
+	//printf(" baud %d: osr=%d, div=%d\n", baud, bestosr, bestdiv);
+	hardware->ccm_register |= hardware->ccm_value;
+	hardware->rx_mux_register = hardware->rx_mux_val;
+	hardware->tx_mux_register = hardware->tx_mux_val;
+	port->BAUD = LPUART_BAUD_OSR(bestosr - 1) | LPUART_BAUD_SBR(bestdiv);
+	port->CTRL = LPUART_CTRL_TE | LPUART_CTRL_RE;
+};
+
+int HardwareSerial::available(void)
+{
+	return -1;
+}
+
+int HardwareSerial::peek(void)
+{
+	return -1;
+}
+
+int HardwareSerial::read(void)
+{
+	return -1;
+}
+void HardwareSerial::flush(void)
+{
+}
+
+size_t HardwareSerial::write(uint8_t c)
+{
+	while (!(port->STAT & LPUART_STAT_TDRE)) ; // wait
+	port->DATA = c;
+	return 1;
+}
+
+__attribute__((section(".progmem")))
+const HardwareSerial::hardware_t UART6_Hardware = {
+	IRQ_LPUART6,
+	CCM_CCGR3, CCM_CCGR3_LPUART6(CCM_CCGR_ON),
+	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03, // pin 0
+	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02, // pin 1
+	2, // page 473
+	2, // page 472
+};
+HardwareSerial Serial1(&IMXRT_LPUART6, &UART6_Hardware);
+
+static HardwareSerial::hardware_t UART4_Hardware = {
+	IRQ_LPUART4,
+	CCM_CCGR1, CCM_CCGR1_LPUART4(CCM_CCGR_ON),
+	IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01, // pin 6
+	IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00, // pin 7
+	2, // page 521
+	2, // page 520
+};
+HardwareSerial Serial2(&IMXRT_LPUART4, &UART4_Hardware);
+
+static HardwareSerial::hardware_t UART2_Hardware = {
+	IRQ_LPUART2,
+	CCM_CCGR0, CCM_CCGR0_LPUART2(CCM_CCGR_ON),
+	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03, // pin 15
+	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02, // pin 14
+	2, // page 491
+	2, // page 490
+};
+HardwareSerial Serial3(&IMXRT_LPUART2, &UART2_Hardware);
+
+static HardwareSerial::hardware_t UART3_Hardware = {
+	IRQ_LPUART3,
+	CCM_CCGR0, CCM_CCGR0_LPUART3(CCM_CCGR_ON),
+	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07, // pin 16
+	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06, // pin 17
+	2, // page 495
+	2, // page 494
+};
+HardwareSerial Serial4(&IMXRT_LPUART3, &UART3_Hardware);
+
+static HardwareSerial::hardware_t UART8_Hardware = {
+	IRQ_LPUART8,
+	CCM_CCGR6, CCM_CCGR6_LPUART8(CCM_CCGR_ON),
+	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11, // pin 21
+	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10, // pin 20
+	2, // page 499
+	2, // page 498
+};
+HardwareSerial Serial5(&IMXRT_LPUART8, &UART8_Hardware);
+
+static HardwareSerial::hardware_t UART1_Hardware = {
+	IRQ_LPUART1,
+	CCM_CCGR5, CCM_CCGR5_LPUART1(CCM_CCGR_ON),
+	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13, // pin 25
+	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12, // pin 24
+	2, // page 486
+	2, // page 485
+};
+HardwareSerial Serial6(&IMXRT_LPUART1, &UART1_Hardware);
+
+static HardwareSerial::hardware_t UART7_Hardware = {
+	IRQ_LPUART7,
+	CCM_CCGR5, CCM_CCGR5_LPUART7(CCM_CCGR_ON),
+	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, // pin 28
+	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, // pin 29
+	2, // page 458
+	2, // page 457
+};
+HardwareSerial Serial7(&IMXRT_LPUART7, &UART7_Hardware);
+
+static HardwareSerial::hardware_t UART5_Hardware = {
+	IRQ_LPUART5,
+	CCM_CCGR3, CCM_CCGR3_LPUART5(CCM_CCGR_ON),
+	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, // pin 30
+	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, // pin 31
+	2, // page 450
+	2, // page 449
+};
+HardwareSerial Serial8(&IMXRT_LPUART5, &UART5_Hardware);
+
+
+
+

teensy4/HardwareSerial.h

@@ -33,6 +33,78 @@
 
 #include "imxrt.h"
 
+#ifdef __cplusplus
+#include "Stream.h"
+class HardwareSerial : public Stream
+{
+public:
+	typedef struct {
+		IRQ_NUMBER_t irq;
+		volatile uint32_t &ccm_register;
+		const uint32_t ccm_value;
+		volatile uint32_t &rx_mux_register;
+		volatile uint32_t &tx_mux_register;
+		const uint8_t rx_mux_val;
+		const uint8_t tx_mux_val;
+	} hardware_t;
+public:
+	constexpr HardwareSerial(IMXRT_LPUART_t *myport, const hardware_t *myhardware) :
+		port(myport), hardware(myhardware) {
+	}
+	void begin(uint32_t baud, uint8_t format=0);
+
+	virtual int available(void);
+	virtual int peek(void);
+	virtual void flush(void);
+	virtual size_t write(uint8_t c);
+	virtual int read(void);
+	using Print::write;
+
+/*
+	virtual void begin(uint32_t baud) { serial_begin(BAUD2DIV(baud)); }
+	virtual void begin(uint32_t baud, uint32_t format) {
+					  serial_begin(BAUD2DIV(baud));
+					  serial_format(format); }
+	virtual void end(void)		{ serial_end(); }
+	virtual void transmitterEnable(uint8_t pin) { serial_set_transmit_pin(pin); }
+	virtual void setRX(uint8_t pin) { serial_set_rx(pin); }
+	virtual void setTX(uint8_t pin, bool opendrain=false) { serial_set_tx(pin, opendrain); }
+	virtual bool attachRts(uint8_t pin) { return serial_set_rts(pin); }
+	virtual bool attachCts(uint8_t pin) { return serial_set_cts(pin); }
+	virtual void clear(void)	{ serial_clear(); }
+	virtual int availableForWrite(void) { return serial_write_buffer_free(); }
+	using Print::write;
+	virtual size_t write(uint8_t c) { serial_putchar(c); return 1; }
+	virtual size_t write(unsigned long n)   { return write((uint8_t)n); }
+	virtual size_t write(long n)            { return write((uint8_t)n); }
+	virtual size_t write(unsigned int n)    { return write((uint8_t)n); }
+	virtual size_t write(int n)             { return write((uint8_t)n); }
+	virtual size_t write(const uint8_t *buffer, size_t size)
+					{ serial_write(buffer, size); return size; }
+        virtual size_t write(const char *str)	{ size_t len = strlen(str);
+					  serial_write((const uint8_t *)str, len);
+					  return len; }
+	virtual size_t write9bit(uint32_t c)	{ serial_putchar(c); return 1; }
+*/
+	operator bool()			{ return true; }
+private:
+	IMXRT_LPUART_t * const port;
+	const hardware_t * const hardware;
+};
+extern HardwareSerial Serial1;
+extern HardwareSerial Serial2;
+extern HardwareSerial Serial3;
+extern HardwareSerial Serial4;
+extern HardwareSerial Serial5;
+extern HardwareSerial Serial6;
+extern HardwareSerial Serial7;
+extern HardwareSerial Serial8;
+//extern void serialEvent1(void);
+
+
+#endif // __cplusplus
+
+
 // Uncomment to enable 9 bit formats.  These are default disabled to save memory.
 //#define SERIAL_9BIT_SUPPORT
 //
@@ -133,7 +205,7 @@
 #define BAUD2DIV3(baud) (((F_BUS / 16) + ((baud) >> 1)) / (baud))
 #endif
 */
-
+#if 0
 
 // C language implementation
 //
@@ -486,6 +558,7 @@ extern void serialEvent6(void);
 
 
 
+#endif
 
 #endif
 #endif

teensy4/imxrt.h

@@ -5514,110 +5514,124 @@ typedef struct {
 #define LPSPI_RSR_SOF				((uint32_t)(1<<0))
 
 // 39.3.1.1: page 2466
-#define IMXRT_LPUART1		(*(IMXRT_REGISTER32_t *)0x40184000)
-#define LPUART1_VERID			(IMXRT_LPUART1.offset000)
-#define LPUART1_PARAM			(IMXRT_LPUART1.offset004)
-#define LPUART1_GLOBAL			(IMXRT_LPUART1.offset008)
-#define LPUART1_PINCFG			(IMXRT_LPUART1.offset00C)
-#define LPUART1_BAUD			(IMXRT_LPUART1.offset010)
-#define LPUART1_STAT			(IMXRT_LPUART1.offset014)
-#define LPUART1_CTRL			(IMXRT_LPUART1.offset018)
-#define LPUART1_DATA			(IMXRT_LPUART1.offset01C)
-#define LPUART1_MATCH			(IMXRT_LPUART1.offset020)
-#define LPUART1_MODIR			(IMXRT_LPUART1.offset024)
-#define LPUART1_FIFO			(IMXRT_LPUART1.offset028)
-#define LPUART1_WATER			(IMXRT_LPUART1.offset02C)
-#define IMXRT_LPUART2		(*(IMXRT_REGISTER32_t *)0x40188000)
-#define LPUART2_VERID			(IMXRT_LPUART2.offset000)
-#define LPUART2_PARAM			(IMXRT_LPUART2.offset004)
-#define LPUART2_GLOBAL			(IMXRT_LPUART2.offset008)
-#define LPUART2_PINCFG			(IMXRT_LPUART2.offset00C)
-#define LPUART2_BAUD			(IMXRT_LPUART2.offset010)
-#define LPUART2_STAT			(IMXRT_LPUART2.offset014)
-#define LPUART2_CTRL			(IMXRT_LPUART2.offset018)
-#define LPUART2_DATA			(IMXRT_LPUART2.offset01C)
-#define LPUART2_MATCH			(IMXRT_LPUART2.offset020)
-#define LPUART2_MODIR			(IMXRT_LPUART2.offset024)
-#define LPUART2_FIFO			(IMXRT_LPUART2.offset028)
-#define LPUART2_WATER			(IMXRT_LPUART2.offset02C)
-#define IMXRT_LPUART3		(*(IMXRT_REGISTER32_t *)0x4018C000)
-#define LPUART3_VERID			(IMXRT_LPUART3.offset000)
-#define LPUART3_PARAM			(IMXRT_LPUART3.offset004)
-#define LPUART3_GLOBAL			(IMXRT_LPUART3.offset008)
-#define LPUART3_PINCFG			(IMXRT_LPUART3.offset00C)
-#define LPUART3_BAUD			(IMXRT_LPUART3.offset010)
-#define LPUART3_STAT			(IMXRT_LPUART3.offset014)
-#define LPUART3_CTRL			(IMXRT_LPUART3.offset018)
-#define LPUART3_DATA			(IMXRT_LPUART3.offset01C)
-#define LPUART3_MATCH			(IMXRT_LPUART3.offset020)
-#define LPUART3_MODIR			(IMXRT_LPUART3.offset024)
-#define LPUART3_FIFO			(IMXRT_LPUART3.offset028)
-#define LPUART3_WATER			(IMXRT_LPUART3.offset02C)
-#define IMXRT_LPUART4		(*(IMXRT_REGISTER32_t *)0x40190000)
-#define LPUART4_VERID			(IMXRT_LPUART4.offset000)
-#define LPUART4_PARAM			(IMXRT_LPUART4.offset004)
-#define LPUART4_GLOBAL			(IMXRT_LPUART4.offset008)
-#define LPUART4_PINCFG			(IMXRT_LPUART4.offset00C)
-#define LPUART4_BAUD			(IMXRT_LPUART4.offset010)
-#define LPUART4_STAT			(IMXRT_LPUART4.offset014)
-#define LPUART4_CTRL			(IMXRT_LPUART4.offset018)
-#define LPUART4_DATA			(IMXRT_LPUART4.offset01C)
-#define LPUART4_MATCH			(IMXRT_LPUART4.offset020)
-#define LPUART4_MODIR			(IMXRT_LPUART4.offset024)
-#define LPUART4_FIFO			(IMXRT_LPUART4.offset028)
-#define LPUART4_WATER			(IMXRT_LPUART4.offset02C)
-#define IMXRT_LPUART5		(*(IMXRT_REGISTER32_t *)0x40194000)
-#define LPUART5_VERID			(IMXRT_LPUART5.offset000)
-#define LPUART5_PARAM			(IMXRT_LPUART5.offset004)
-#define LPUART5_GLOBAL			(IMXRT_LPUART5.offset008)
-#define LPUART5_PINCFG			(IMXRT_LPUART5.offset00C)
-#define LPUART5_BAUD			(IMXRT_LPUART5.offset010)
-#define LPUART5_STAT			(IMXRT_LPUART5.offset014)
-#define LPUART5_CTRL			(IMXRT_LPUART5.offset018)
-#define LPUART5_DATA			(IMXRT_LPUART5.offset01C)
-#define LPUART5_MATCH			(IMXRT_LPUART5.offset020)
-#define LPUART5_MODIR			(IMXRT_LPUART5.offset024)
-#define LPUART5_FIFO			(IMXRT_LPUART5.offset028)
-#define LPUART5_WATER			(IMXRT_LPUART5.offset02C)
-#define IMXRT_LPUART6		(*(IMXRT_REGISTER32_t *)0x40198000)
-#define LPUART6_VERID			(IMXRT_LPUART6.offset000)
-#define LPUART6_PARAM			(IMXRT_LPUART6.offset004)
-#define LPUART6_GLOBAL			(IMXRT_LPUART6.offset008)
-#define LPUART6_PINCFG			(IMXRT_LPUART6.offset00C)
-#define LPUART6_BAUD			(IMXRT_LPUART6.offset010)
-#define LPUART6_STAT			(IMXRT_LPUART6.offset014)
-#define LPUART6_CTRL			(IMXRT_LPUART6.offset018)
-#define LPUART6_DATA			(IMXRT_LPUART6.offset01C)
-#define LPUART6_MATCH			(IMXRT_LPUART6.offset020)
-#define LPUART6_MODIR			(IMXRT_LPUART6.offset024)
-#define LPUART6_FIFO			(IMXRT_LPUART6.offset028)
-#define LPUART6_WATER			(IMXRT_LPUART6.offset02C)
-#define IMXRT_LPUART7		(*(IMXRT_REGISTER32_t *)0x4019C000)
-#define LPUART7_VERID			(IMXRT_LPUART7.offset000)
-#define LPUART7_PARAM			(IMXRT_LPUART7.offset004)
-#define LPUART7_GLOBAL			(IMXRT_LPUART7.offset008)
-#define LPUART7_PINCFG			(IMXRT_LPUART7.offset00C)
-#define LPUART7_BAUD			(IMXRT_LPUART7.offset010)
-#define LPUART7_STAT			(IMXRT_LPUART7.offset014)
-#define LPUART7_CTRL			(IMXRT_LPUART7.offset018)
-#define LPUART7_DATA			(IMXRT_LPUART7.offset01C)
-#define LPUART7_MATCH			(IMXRT_LPUART7.offset020)
-#define LPUART7_MODIR			(IMXRT_LPUART7.offset024)
-#define LPUART7_FIFO			(IMXRT_LPUART7.offset028)
-#define LPUART7_WATER			(IMXRT_LPUART7.offset02C)
-#define IMXRT_LPUART8		(*(IMXRT_REGISTER32_t *)0x401A0000)
-#define LPUART8_VERID			(IMXRT_LPUART8.offset000)
-#define LPUART8_PARAM			(IMXRT_LPUART8.offset004)
-#define LPUART8_GLOBAL			(IMXRT_LPUART8.offset008)
-#define LPUART8_PINCFG			(IMXRT_LPUART8.offset00C)
-#define LPUART8_BAUD			(IMXRT_LPUART8.offset010)
-#define LPUART8_STAT			(IMXRT_LPUART8.offset014)
-#define LPUART8_CTRL			(IMXRT_LPUART8.offset018)
-#define LPUART8_DATA			(IMXRT_LPUART8.offset01C)
-#define LPUART8_MATCH			(IMXRT_LPUART8.offset020)
-#define LPUART8_MODIR			(IMXRT_LPUART8.offset024)
-#define LPUART8_FIFO			(IMXRT_LPUART8.offset028)
-#define LPUART8_WATER			(IMXRT_LPUART8.offset02C)
+typedef struct {
+	const uint32_t VERID;
+	const uint32_t PARAM;
+	volatile uint32_t GLOBAL;
+	volatile uint32_t PINCFG;
+	volatile uint32_t BAUD;
+	volatile uint32_t STAT;
+	volatile uint32_t CTRL;
+	volatile uint32_t DATA;
+	volatile uint32_t MATCH;
+	volatile uint32_t MODIR;
+	volatile uint32_t FIFO;
+	volatile uint32_t WATER;
+} IMXRT_LPUART_t;
+#define IMXRT_LPUART1		(*(IMXRT_LPUART_t *)0x40184000)
+#define LPUART1_VERID			(IMXRT_LPUART1.VERID)
+#define LPUART1_PARAM			(IMXRT_LPUART1.PARAM)
+#define LPUART1_GLOBAL			(IMXRT_LPUART1.GLOBAL)
+#define LPUART1_PINCFG			(IMXRT_LPUART1.PINCFG)
+#define LPUART1_BAUD			(IMXRT_LPUART1.BAUD)
+#define LPUART1_STAT			(IMXRT_LPUART1.STAT)
+#define LPUART1_CTRL			(IMXRT_LPUART1.CTRL)
+#define LPUART1_DATA			(IMXRT_LPUART1.DATA)
+#define LPUART1_MATCH			(IMXRT_LPUART1.MATCH)
+#define LPUART1_MODIR			(IMXRT_LPUART1.MODIR)
+#define LPUART1_FIFO			(IMXRT_LPUART1.FIFO)
+#define LPUART1_WATER			(IMXRT_LPUART1.WATER)
+#define IMXRT_LPUART2		(*(IMXRT_LPUART_t *)0x40188000)
+#define LPUART2_VERID			(IMXRT_LPUART2.VERID)
+#define LPUART2_PARAM			(IMXRT_LPUART2.PARAM)
+#define LPUART2_GLOBAL			(IMXRT_LPUART2.GLOBAL)
+#define LPUART2_PINCFG			(IMXRT_LPUART2.PINCFG)
+#define LPUART2_BAUD			(IMXRT_LPUART2.BAUD)
+#define LPUART2_STAT			(IMXRT_LPUART2.STAT)
+#define LPUART2_CTRL			(IMXRT_LPUART2.CTRL)
+#define LPUART2_DATA			(IMXRT_LPUART2.DATA)
+#define LPUART2_MATCH			(IMXRT_LPUART2.MATCH)
+#define LPUART2_MODIR			(IMXRT_LPUART2.MODIR)
+#define LPUART2_FIFO			(IMXRT_LPUART2.FIFO)
+#define LPUART2_WATER			(IMXRT_LPUART2.WATER)
+#define IMXRT_LPUART3		(*(IMXRT_LPUART_t *)0x4018C000)
+#define LPUART3_VERID			(IMXRT_LPUART3.VERID)
+#define LPUART3_PARAM			(IMXRT_LPUART3.PARAM)
+#define LPUART3_GLOBAL			(IMXRT_LPUART3.GLOBAL)
+#define LPUART3_PINCFG			(IMXRT_LPUART3.PINCFG)
+#define LPUART3_BAUD			(IMXRT_LPUART3.BAUD)
+#define LPUART3_STAT			(IMXRT_LPUART3.STAT)
+#define LPUART3_CTRL			(IMXRT_LPUART3.CTRL)
+#define LPUART3_DATA			(IMXRT_LPUART3.DATA)
+#define LPUART3_MATCH			(IMXRT_LPUART3.MATCH)
+#define LPUART3_MODIR			(IMXRT_LPUART3.MODIR)
+#define LPUART3_FIFO			(IMXRT_LPUART3.FIFO)
+#define LPUART3_WATER			(IMXRT_LPUART3.WATER)
+#define IMXRT_LPUART4		(*(IMXRT_LPUART_t *)0x40190000)
+#define LPUART4_VERID			(IMXRT_LPUART4.VERID)
+#define LPUART4_PARAM			(IMXRT_LPUART4.PARAM)
+#define LPUART4_GLOBAL			(IMXRT_LPUART4.GLOBAL)
+#define LPUART4_PINCFG			(IMXRT_LPUART4.PINCFG)
+#define LPUART4_BAUD			(IMXRT_LPUART4.BAUD)
+#define LPUART4_STAT			(IMXRT_LPUART4.STAT)
+#define LPUART4_CTRL			(IMXRT_LPUART4.CTRL)
+#define LPUART4_DATA			(IMXRT_LPUART4.DATA)
+#define LPUART4_MATCH			(IMXRT_LPUART4.MATCH)
+#define LPUART4_MODIR			(IMXRT_LPUART4.MODIR)
+#define LPUART4_FIFO			(IMXRT_LPUART4.FIFO)
+#define LPUART4_WATER			(IMXRT_LPUART4.WATER)
+#define IMXRT_LPUART5		(*(IMXRT_LPUART_t *)0x40194000)
+#define LPUART5_VERID			(IMXRT_LPUART5.VERID)
+#define LPUART5_PARAM			(IMXRT_LPUART5.PARAM)
+#define LPUART5_GLOBAL			(IMXRT_LPUART5.GLOBAL)
+#define LPUART5_PINCFG			(IMXRT_LPUART5.PINCFG)
+#define LPUART5_BAUD			(IMXRT_LPUART5.BAUD)
+#define LPUART5_STAT			(IMXRT_LPUART5.STAT)
+#define LPUART5_CTRL			(IMXRT_LPUART5.CTRL)
+#define LPUART5_DATA			(IMXRT_LPUART5.DATA)
+#define LPUART5_MATCH			(IMXRT_LPUART5.MATCH)
+#define LPUART5_MODIR			(IMXRT_LPUART5.MODIR)
+#define LPUART5_FIFO			(IMXRT_LPUART5.FIFO)
+#define LPUART5_WATER			(IMXRT_LPUART5.WATER)
+#define IMXRT_LPUART6		(*(IMXRT_LPUART_t *)0x40198000)
+#define LPUART6_VERID			(IMXRT_LPUART6.VERID)
+#define LPUART6_PARAM			(IMXRT_LPUART6.PARAM)
+#define LPUART6_GLOBAL			(IMXRT_LPUART6.GLOBAL)
+#define LPUART6_PINCFG			(IMXRT_LPUART6.PINCFG)
+#define LPUART6_BAUD			(IMXRT_LPUART6.BAUD)
+#define LPUART6_STAT			(IMXRT_LPUART6.STAT)
+#define LPUART6_CTRL			(IMXRT_LPUART6.CTRL)
+#define LPUART6_DATA			(IMXRT_LPUART6.DATA)
+#define LPUART6_MATCH			(IMXRT_LPUART6.MATCH)
+#define LPUART6_MODIR			(IMXRT_LPUART6.MODIR)
+#define LPUART6_FIFO			(IMXRT_LPUART6.FIFO)
+#define LPUART6_WATER			(IMXRT_LPUART6.WATER)
+#define IMXRT_LPUART7		(*(IMXRT_LPUART_t *)0x4019C000)
+#define LPUART7_VERID			(IMXRT_LPUART7.VERID)
+#define LPUART7_PARAM			(IMXRT_LPUART7.PARAM)
+#define LPUART7_GLOBAL			(IMXRT_LPUART7.GLOBAL)
+#define LPUART7_PINCFG			(IMXRT_LPUART7.PINCFG)
+#define LPUART7_BAUD			(IMXRT_LPUART7.BAUD)
+#define LPUART7_STAT			(IMXRT_LPUART7.STAT)
+#define LPUART7_CTRL			(IMXRT_LPUART7.CTRL)
+#define LPUART7_DATA			(IMXRT_LPUART7.DATA)
+#define LPUART7_MATCH			(IMXRT_LPUART7.MATCH)
+#define LPUART7_MODIR			(IMXRT_LPUART7.MODIR)
+#define LPUART7_FIFO			(IMXRT_LPUART7.FIFO)
+#define LPUART7_WATER			(IMXRT_LPUART7.WATER)
+#define IMXRT_LPUART8		(*(IMXRT_LPUART_t *)0x401A0000)
+#define LPUART8_VERID			(IMXRT_LPUART8.VERID)
+#define LPUART8_PARAM			(IMXRT_LPUART8.PARAM)
+#define LPUART8_GLOBAL			(IMXRT_LPUART8.GLOBAL)
+#define LPUART8_PINCFG			(IMXRT_LPUART8.PINCFG)
+#define LPUART8_BAUD			(IMXRT_LPUART8.BAUD)
+#define LPUART8_STAT			(IMXRT_LPUART8.STAT)
+#define LPUART8_CTRL			(IMXRT_LPUART8.CTRL)
+#define LPUART8_DATA			(IMXRT_LPUART8.DATA)
+#define LPUART8_MATCH			(IMXRT_LPUART8.MATCH)
+#define LPUART8_MODIR			(IMXRT_LPUART8.MODIR)
+#define LPUART8_FIFO			(IMXRT_LPUART8.FIFO)
+#define LPUART8_WATER			(IMXRT_LPUART8.WATER)
 #define LPUART_VERID_MAJOR(n)			((uint32_t)(((n) & 0xFF) << 24))
 #define LPUART_VERID_MINOR(n)			((uint32_t)(((n) & 0xFF) << 16))
 #define LPUART_VERID_FEATURE(n)			((uint32_t)(((n) & 0xFFFF) << 0))

teensy4/imxrt.ld

@@ -19,6 +19,19 @@ SECTIONS
 		KEEP(*(.vectors))
 		KEEP(*(.startup))
 		*(.progmem*)
+                . = ALIGN(4);
+/*
+		TODO: how much of this C++ stuff is really needed?
+                KEEP(*(.init))
+                . = ALIGN(4);
+                __preinit_array_start = .;
+                KEEP (*(.preinit_array))
+                __preinit_array_end = .;
+                __init_array_start = .;
+                KEEP (*(SORT(.init_array.*)))
+                KEEP (*(.init_array))
+                __init_array_end = .;
+*/
 		. = ALIGN(16);
 	} > FLASH
 

teensy4/usb.c

@@ -128,7 +128,7 @@ void usb_init(void)
 		//printf("USBPHY1_RX=%08lX\n", USBPHY1_RX);
 		//printf("USBPHY1_CTRL=%08lX\n", USBPHY1_CTRL);
 		//printf("USB1_USBMODE=%08lX\n", USB1_USBMODE);
-		//delay(500);
+		delay(100);
 	}
 #endif
 	// Device Controller Initialization, page 3161