| @@ -29,6 +29,7 @@ | |||
| #define FASTRUN __attribute__ ((section(".fastrun") )) | |||
| #define PROGMEM __attribute__((section(".progmem"))) | |||
| #define FLASHMEM __attribute__((section(".flashmem"))) | |||
| #define EXTMEM __attribute__((section(".externalram"))) | |||
| #define PGM_P const char * | |||
| #define PSTR(str) ({static const char data[] PROGMEM = (str); &data[0];}) | |||
| @@ -1256,17 +1256,21 @@ typedef struct { | |||
| #define CCM_CBCDR_IPG_PODF_MASK ((uint32_t)(0x03 << 8)) | |||
| #define CCM_CBCDR_SEMC_ALT_CLK_SEL ((uint32_t)(1<<7)) | |||
| #define CCM_CBCDR_SEMC_CLK_SEL ((uint32_t)(1<<6)) | |||
| #define CCM_CBCMR_FLEXSPI2_PODF(n) ((uint32_t)(((n) & 0x07) << 29)) | |||
| #define CCM_CBCMR_LPSPI_PODF(n) ((uint32_t)(((n) & 0x07) << 26)) | |||
| #define CCM_CBCMR_LCDIF_PODF(n) ((uint32_t)(((n) & 0x07) << 23)) | |||
| #define CCM_CBCMR_PRE_PERIPH_CLK_SEL(n) ((uint32_t)(((n) & 0x03) << 18)) | |||
| #define CCM_CBCMR_TRACE_CLK_SEL(n) ((uint32_t)(((n) & 0x03) << 14)) | |||
| #define CCM_CBCMR_PERIPH_CLK2_SEL(n) ((uint32_t)(((n) & 0x03) << 12)) | |||
| #define CCM_CBCMR_PERIPH_CLK2_SEL_MASK ((uint32_t)(0x03 << 12)) | |||
| #define CCM_CBCMR_FLEXSPI2_CLK_SEL(n) ((uint32_t)(((n) & 0x03) << 8)) | |||
| #define CCM_CBCMR_LPSPI_CLK_SEL(n) ((uint32_t)(((n) & 0x03) << 4)) | |||
| #define CCM_CBCMR_FLEXSPI2_PODF_MASK ((uint32_t)(0x07 << 29)) | |||
| #define CCM_CBCMR_LPSPI_PODF_MASK ((uint32_t)(0x07 << 26)) | |||
| #define CCM_CBCMR_LCDIF_PODF_MASK ((uint32_t)(0x07 << 23)) | |||
| #define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK ((uint32_t)(0x03 << 18)) | |||
| #define CCM_CBCMR_TRACE_CLK_SEL_MASK ((uint32_t)(0x03 << 14)) | |||
| #define CCM_CBCMR_PERIPH_CLK2_SEL_MASK ((uint32_t)(0x03 << 12)) | |||
| #define CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK ((uint32_t)(0x03 << 8)) | |||
| #define CCM_CBCMR_LPSPI_CLK_SEL_MASK ((uint32_t)(0x03 << 4)) | |||
| #define CCM_CSCMR1_FLEXSPI_CLK_SEL(n) ((uint32_t)(((n) & 0x03) << 29)) | |||
| #define CCM_CSCMR1_FLEXSPI_PODF(n) ((uint32_t)(((n) & 0x07) << 23)) | |||
| @@ -3,7 +3,8 @@ MEMORY | |||
| ITCM (rwx): ORIGIN = 0x00000000, LENGTH = 512K | |||
| DTCM (rwx): ORIGIN = 0x20000000, LENGTH = 512K | |||
| RAM (rwx): ORIGIN = 0x20200000, LENGTH = 512K | |||
| FLASH (rwx): ORIGIN = 0x60000000, LENGTH = 1984K | |||
| FLASH (rwx): ORIGIN = 0x60000000, LENGTH = 7936K | |||
| ERAM (rwx): ORIGIN = 0x70000000, LENGTH = 8192K | |||
| } | |||
| ENTRY(ImageVectorTable) | |||
| @@ -60,6 +61,10 @@ SECTIONS | |||
| . = ALIGN(16); | |||
| } > RAM | |||
| .bss.extram (NOLOAD) : { | |||
| *(.externalram) | |||
| } > ERAM | |||
| _stext = ADDR(.text.itcm); | |||
| _etext = ADDR(.text.itcm) + SIZEOF(.text.itcm); | |||
| _stextload = LOADADDR(.text.itcm); | |||
| @@ -187,6 +187,7 @@ static void configure_systick(void) | |||
| #define SIZE_16M (SCB_MPU_RASR_SIZE(23) | SCB_MPU_RASR_ENABLE) | |||
| #define SIZE_32M (SCB_MPU_RASR_SIZE(24) | SCB_MPU_RASR_ENABLE) | |||
| #define SIZE_64M (SCB_MPU_RASR_SIZE(25) | SCB_MPU_RASR_ENABLE) | |||
| #define SIZE_256M (SCB_MPU_RASR_SIZE(26) | SCB_MPU_RASR_ENABLE) | |||
| #define REGION(n) (SCB_MPU_RBAR_REGION(n) | SCB_MPU_RBAR_VALID) | |||
| FLASHMEM void configure_cache(void) | |||
| @@ -216,6 +217,12 @@ FLASHMEM void configure_cache(void) | |||
| SCB_MPU_RBAR = 0x60000000 | REGION(5); // QSPI Flash | |||
| SCB_MPU_RASR = MEM_CACHE_WBWA | READONLY | SIZE_16M; | |||
| SCB_MPU_RBAR = 0x70000000 | REGION(6); // FlexSPI2 | |||
| SCB_MPU_RASR = MEM_CACHE_WBWA | READONLY | SIZE_256M; | |||
| SCB_MPU_RBAR = 0x70000000 | REGION(7); // FlexSPI2 | |||
| SCB_MPU_RASR = MEM_CACHE_WBWA | READWRITE | SIZE_16M; | |||
| // TODO: 32 byte sub-region at 0x00000000 with NOACCESS, to trap NULL pointer deref | |||
| // TODO: protect access to power supply config | |||
| // TODO: 32 byte sub-region at end of .bss section with NOACCESS, to trap stack overflow | |||