SPIFIFO support for any CS pins

teensy3/SPIFIFO.h

 
 #define SPI_CONTINUE 1
 
-static uint8_t pcs=0;
+static uint8_t pcs = 0;
+static volatile uint8_t *reg = 0;
 
 class SPIFIFOclass
 {
 public:
-	inline bool begin(uint8_t pin, uint32_t speed, uint32_t mode=SPI_MODE0) __attribute__((always_inline)) {
+	inline void begin(uint8_t pin, uint32_t speed, uint32_t mode=SPI_MODE0) __attribute__((always_inline)) {
 		uint32_t p, ctar = speed;
 		SIM_SCGC6 |= SIM_SCGC6_SPI0;
 
-		SPI0_MCR = SPI_MCR_MSTR | SPI_MCR_MDIS | SPI_MCR_HALT | SPI_MCR_PCSIS(0x1F);
+		SPI0.MCR = SPI_MCR_MSTR | SPI_MCR_MDIS | SPI_MCR_HALT | SPI_MCR_PCSIS(0x1F);
 		if (mode & 0x08) ctar |= SPI_CTAR_CPOL;
 		if (mode & 0x04) {
 			ctar |= SPI_CTAR_CPHA;
 		} else {
 			ctar |= (ctar & 0x0F) << 12;
 		}
-		SPI0_CTAR0 = ctar | SPI_CTAR_FMSZ(7);
-		SPI0_CTAR1 = ctar | SPI_CTAR_FMSZ(15);
+		SPI0.CTAR0 = ctar | SPI_CTAR_FMSZ(7);
+		SPI0.CTAR1 = ctar | SPI_CTAR_FMSZ(15);
 		if (pin == 10) {         // PTC4
 			CORE_PIN10_CONFIG = PORT_PCR_MUX(2);
 			p = 0x01;
 			CORE_PIN15_CONFIG = PORT_PCR_MUX(2);
 			p = 0x10;
 		} else {
-			return false;
+			reg = portOutputRegister(pin);
+			*reg = 1;
+			pinMode(pin, OUTPUT);
+			p = 0;
 		}
 		pcs = p;
 		clear();
 		SPCR.enable_pins();
-		return true;
 	}
 	inline void write(uint32_t b, uint32_t cont=0) __attribute__((always_inline)) {
-		while (((SPI0_SR) & (15 << 12)) > (3 << 12)) ; // wait for space in the TX fifo
-		SPI0_PUSHR = (b & 0xFF) | (pcs << 16) | (cont ? SPI_PUSHR_CONT : 0);
+		uint32_t pcsbits = pcs << 16;
+		if (pcsbits) {
+			SPI0.PUSHR = (b & 0xFF) | pcsbits | (cont ? SPI_PUSHR_CONT : 0);
+			while (((SPI0.SR) & (15 << 12)) > (3 << 12)) ; // wait if FIFO full
+		} else {
+			*reg = 0;
+			SPI0.SR = SPI_SR_EOQF;
+			SPI0.PUSHR = (b & 0xFF) | (cont ? 0 : SPI_PUSHR_EOQ);
+			if (cont) {
+				while (((SPI0.SR) & (15 << 12)) > (3 << 12)) ;
+			} else {
+				while (!(SPI0.SR & SPI_SR_EOQF)) ;
+				*reg = 1;
+			}
+		}
 	}
 	inline void write16(uint32_t b, uint32_t cont=0) __attribute__((always_inline)) {
-		while (((SPI0_SR) & (15 << 12)) > (3 << 12)) ; // wait for space in the TX fifo
-		SPI0_PUSHR = (b & 0xFFFF) | (pcs << 16) | (cont ? SPI_PUSHR_CONT : 0) | SPI_PUSHR_CTAS(1);
+		uint32_t pcsbits = pcs << 16;
+		if (pcsbits) {
+			SPI0.PUSHR = (b & 0xFFFF) | (pcs << 16) |
+				(cont ? SPI_PUSHR_CONT : 0) | SPI_PUSHR_CTAS(1);
+			while (((SPI0.SR) & (15 << 12)) > (3 << 12)) ;
+		} else {
+			*reg = 0;
+			SPI0.SR = SPI_SR_EOQF;
+			SPI0.PUSHR = (b & 0xFFFF) | (cont ? 0 : SPI_PUSHR_EOQ) | SPI_PUSHR_CTAS(1);
+			if (cont) {
+				while (((SPI0.SR) & (15 << 12)) > (3 << 12)) ;
+			} else {
+				while (!(SPI0.SR & SPI_SR_EOQF)) ;
+				*reg = 1;
+			}
+		}
 	}
 	inline uint32_t read(void) __attribute__((always_inline)) {
-		while ((SPI0_SR & (15 << 4)) == 0) ;  // TODO, could wait forever
-		return SPI0_POPR;
+		while ((SPI0.SR & (15 << 4)) == 0) ;  // TODO, could wait forever
+		return SPI0.POPR;
 	}
 	inline void clear(void) __attribute__((always_inline)) {
-		SPI0_MCR = SPI_MCR_MSTR | SPI_MCR_PCSIS(0x1F) | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;
+		SPI0.MCR = SPI_MCR_MSTR | SPI_MCR_PCSIS(0x1F) | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;
 	}
 };
 extern SPIFIFOclass SPIFIFO;

teensy3/mk20dx128.h

 #define SPI0_RXFR1              *(volatile uint32_t *)0x4002C080 // DSPI Receive FIFO Registers
 #define SPI0_RXFR2              *(volatile uint32_t *)0x4002C084 // DSPI Receive FIFO Registers
 #define SPI0_RXFR3              *(volatile uint32_t *)0x4002C088 // DSPI Receive FIFO Registers
+typedef struct {
+	volatile uint32_t	MCR;	// 0
+	volatile uint32_t	unused1;// 4
+	volatile uint32_t	TCR;	// 8
+	volatile uint32_t	CTAR0;	// c
+	volatile uint32_t	CTAR1;	// 10
+	volatile uint32_t	CTAR2;	// 14
+	volatile uint32_t	CTAR3;	// 18
+	volatile uint32_t	CTAR4;	// 1c
+	volatile uint32_t	CTAR5;	// 20
+	volatile uint32_t	CTAR6;	// 24
+	volatile uint32_t	CTAR7;	// 28
+	volatile uint32_t	SR;	// 2c
+	volatile uint32_t	RSER;	// 30
+	volatile uint32_t	PUSHR;	// 34
+	volatile uint32_t	POPR;	// 38
+	volatile uint32_t	TXFR[16]; // 3c
+	volatile uint32_t	RXFR[16]; // 7c
+} SPI_t;
+#define SPI0		(*(SPI_t *)0x4002C000)
 
 // Chapter 44: Inter-Integrated Circuit (I2C)
 #define I2C0_A1                 *(volatile uint8_t  *)0x40066000 // I2C Address Register 1