/* ---------------------------------------------------------------------- | |||||
* Project: CMSIS DSP Library | |||||
* Title: arm_common_tables.h | |||||
* Description: Extern declaration for common tables | |||||
* | |||||
* $Date: 27. January 2017 | |||||
* $Revision: V.1.5.1 | |||||
* | |||||
* Target Processor: Cortex-M cores | |||||
* -------------------------------------------------------------------- */ | |||||
/* | |||||
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. | |||||
* | |||||
* SPDX-License-Identifier: Apache-2.0 | |||||
* | |||||
* Licensed under the Apache License, Version 2.0 (the License); you may | |||||
* not use this file except in compliance with the License. | |||||
* You may obtain a copy of the License at | |||||
* | |||||
* www.apache.org/licenses/LICENSE-2.0 | |||||
* | |||||
* Unless required by applicable law or agreed to in writing, software | |||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT | |||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | |||||
* See the License for the specific language governing permissions and | |||||
* limitations under the License. | |||||
*/ | |||||
#ifndef _ARM_COMMON_TABLES_H | |||||
#define _ARM_COMMON_TABLES_H | |||||
#include "arm_math.h" | |||||
extern const uint16_t armBitRevTable[1024]; | |||||
extern const q15_t armRecipTableQ15[64]; | |||||
extern const q31_t armRecipTableQ31[64]; | |||||
extern const float32_t twiddleCoef_16[32]; | |||||
extern const float32_t twiddleCoef_32[64]; | |||||
extern const float32_t twiddleCoef_64[128]; | |||||
extern const float32_t twiddleCoef_128[256]; | |||||
extern const float32_t twiddleCoef_256[512]; | |||||
extern const float32_t twiddleCoef_512[1024]; | |||||
extern const float32_t twiddleCoef_1024[2048]; | |||||
extern const float32_t twiddleCoef_2048[4096]; | |||||
extern const float32_t twiddleCoef_4096[8192]; | |||||
#define twiddleCoef twiddleCoef_4096 | |||||
extern const q31_t twiddleCoef_16_q31[24]; | |||||
extern const q31_t twiddleCoef_32_q31[48]; | |||||
extern const q31_t twiddleCoef_64_q31[96]; | |||||
extern const q31_t twiddleCoef_128_q31[192]; | |||||
extern const q31_t twiddleCoef_256_q31[384]; | |||||
extern const q31_t twiddleCoef_512_q31[768]; | |||||
extern const q31_t twiddleCoef_1024_q31[1536]; | |||||
extern const q31_t twiddleCoef_2048_q31[3072]; | |||||
extern const q31_t twiddleCoef_4096_q31[6144]; | |||||
extern const q15_t twiddleCoef_16_q15[24]; | |||||
extern const q15_t twiddleCoef_32_q15[48]; | |||||
extern const q15_t twiddleCoef_64_q15[96]; | |||||
extern const q15_t twiddleCoef_128_q15[192]; | |||||
extern const q15_t twiddleCoef_256_q15[384]; | |||||
extern const q15_t twiddleCoef_512_q15[768]; | |||||
extern const q15_t twiddleCoef_1024_q15[1536]; | |||||
extern const q15_t twiddleCoef_2048_q15[3072]; | |||||
extern const q15_t twiddleCoef_4096_q15[6144]; | |||||
extern const float32_t twiddleCoef_rfft_32[32]; | |||||
extern const float32_t twiddleCoef_rfft_64[64]; | |||||
extern const float32_t twiddleCoef_rfft_128[128]; | |||||
extern const float32_t twiddleCoef_rfft_256[256]; | |||||
extern const float32_t twiddleCoef_rfft_512[512]; | |||||
extern const float32_t twiddleCoef_rfft_1024[1024]; | |||||
extern const float32_t twiddleCoef_rfft_2048[2048]; | |||||
extern const float32_t twiddleCoef_rfft_4096[4096]; | |||||
/* floating-point bit reversal tables */ | |||||
#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) | |||||
#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) | |||||
#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) | |||||
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) | |||||
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) | |||||
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) | |||||
#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) | |||||
#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) | |||||
#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) | |||||
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; | |||||
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; | |||||
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; | |||||
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; | |||||
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; | |||||
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; | |||||
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; | |||||
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; | |||||
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; | |||||
/* fixed-point bit reversal tables */ | |||||
#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) | |||||
#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) | |||||
#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) | |||||
#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) | |||||
#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) | |||||
#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) | |||||
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) | |||||
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) | |||||
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) | |||||
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; | |||||
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; | |||||
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; | |||||
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; | |||||
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; | |||||
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; | |||||
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; | |||||
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; | |||||
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; | |||||
/* Tables for Fast Math Sine and Cosine */ | |||||
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; | |||||
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; | |||||
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; | |||||
#endif /* ARM_COMMON_TABLES_H */ |
/* ---------------------------------------------------------------------- | |||||
* Project: CMSIS DSP Library | |||||
* Title: arm_const_structs.h | |||||
* Description: Constant structs that are initialized for user convenience. | |||||
* For example, some can be given as arguments to the arm_cfft_f32() function. | |||||
* | |||||
* $Date: 27. January 2017 | |||||
* $Revision: V.1.5.1 | |||||
* | |||||
* Target Processor: Cortex-M cores | |||||
* -------------------------------------------------------------------- */ | |||||
/* | |||||
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. | |||||
* | |||||
* SPDX-License-Identifier: Apache-2.0 | |||||
* | |||||
* Licensed under the Apache License, Version 2.0 (the License); you may | |||||
* not use this file except in compliance with the License. | |||||
* You may obtain a copy of the License at | |||||
* | |||||
* www.apache.org/licenses/LICENSE-2.0 | |||||
* | |||||
* Unless required by applicable law or agreed to in writing, software | |||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT | |||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | |||||
* See the License for the specific language governing permissions and | |||||
* limitations under the License. | |||||
*/ | |||||
#ifndef _ARM_CONST_STRUCTS_H | |||||
#define _ARM_CONST_STRUCTS_H | |||||
#include "arm_math.h" | |||||
#include "arm_common_tables.h" | |||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; | |||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; | |||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; | |||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; | |||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; | |||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; | |||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; | |||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; | |||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; | |||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; | |||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; | |||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; | |||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; | |||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; | |||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; | |||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; | |||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; | |||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; | |||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; | |||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; | |||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; | |||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; | |||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; | |||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; | |||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; | |||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; | |||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; | |||||
#endif |
/**************************************************************************//** | |||||
* @file core_cmInstr.h | |||||
* @brief CMSIS Cortex-M Core Instruction Access Header File | |||||
* @version V3.01 | |||||
* @date 06. March 2012 | |||||
* | |||||
* @note | |||||
* Copyright (C) 2009-2012 ARM Limited. All rights reserved. | |||||
* | |||||
* @par | |||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M | |||||
* processor based microcontrollers. This file can be freely distributed | |||||
* within development tools that are supporting such ARM based processors. | |||||
* | |||||
* @par | |||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED | |||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF | |||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. | |||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR | |||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. | |||||
* | |||||
******************************************************************************/ | |||||
#ifndef __CORE_CMINSTR_H | |||||
#define __CORE_CMINSTR_H | |||||
/* ########################## Core Instruction Access ######################### */ | |||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface | |||||
Access to dedicated instructions | |||||
@{ | |||||
*/ | |||||
#if defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ | |||||
/* GNU gcc specific functions */ | |||||
/** \brief No Operation | |||||
No Operation does nothing. This instruction can be used for code alignment purposes. | |||||
*/ | |||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) | |||||
{ | |||||
__ASM volatile ("nop"); | |||||
} | |||||
/** \brief Wait For Interrupt | |||||
Wait For Interrupt is a hint instruction that suspends execution | |||||
until one of a number of events occurs. | |||||
*/ | |||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) | |||||
{ | |||||
__ASM volatile ("wfi"); | |||||
} | |||||
/** \brief Wait For Event | |||||
Wait For Event is a hint instruction that permits the processor to enter | |||||
a low-power state until one of a number of events occurs. | |||||
*/ | |||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) | |||||
{ | |||||
__ASM volatile ("wfe"); | |||||
} | |||||
/** \brief Send Event | |||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU. | |||||
*/ | |||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) | |||||
{ | |||||
__ASM volatile ("sev"); | |||||
} | |||||
/** \brief Instruction Synchronization Barrier | |||||
Instruction Synchronization Barrier flushes the pipeline in the processor, | |||||
so that all instructions following the ISB are fetched from cache or | |||||
memory, after the instruction has been completed. | |||||
*/ | |||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) | |||||
{ | |||||
__ASM volatile ("isb"); | |||||
} | |||||
/** \brief Data Synchronization Barrier | |||||
This function acts as a special kind of Data Memory Barrier. | |||||
It completes when all explicit memory accesses before this instruction complete. | |||||
*/ | |||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) | |||||
{ | |||||
__ASM volatile ("dsb"); | |||||
} | |||||
/** \brief Data Memory Barrier | |||||
This function ensures the apparent order of the explicit memory operations before | |||||
and after the instruction, without ensuring their completion. | |||||
*/ | |||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) | |||||
{ | |||||
__ASM volatile ("dmb"); | |||||
} | |||||
/** \brief Reverse byte order (32 bit) | |||||
This function reverses the byte order in integer value. | |||||
\param [in] value Value to reverse | |||||
\return Reversed value | |||||
*/ | |||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) | |||||
{ | |||||
uint32_t result; | |||||
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); | |||||
return(result); | |||||
} | |||||
/** \brief Reverse byte order (16 bit) | |||||
This function reverses the byte order in two unsigned short values. | |||||
\param [in] value Value to reverse | |||||
\return Reversed value | |||||
*/ | |||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) | |||||
{ | |||||
uint32_t result; | |||||
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); | |||||
return(result); | |||||
} | |||||
/** \brief Reverse byte order in signed short value | |||||
This function reverses the byte order in a signed short value with sign extension to integer. | |||||
\param [in] value Value to reverse | |||||
\return Reversed value | |||||
*/ | |||||
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) | |||||
{ | |||||
uint32_t result; | |||||
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); | |||||
return(result); | |||||
} | |||||
/** \brief Rotate Right in unsigned value (32 bit) | |||||
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. | |||||
\param [in] value Value to rotate | |||||
\param [in] value Number of Bits to rotate | |||||
\return Rotated value | |||||
*/ | |||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) | |||||
{ | |||||
__ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); | |||||
return(op1); | |||||
} | |||||
#if (__CORTEX_M >= 0x03) | |||||
/** \brief Reverse bit order of value | |||||
This function reverses the bit order of the given value. | |||||
\param [in] value Value to reverse | |||||
\return Reversed value | |||||
*/ | |||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) | |||||
{ | |||||
uint32_t result; | |||||
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); | |||||
return(result); | |||||
} | |||||
/** \brief LDR Exclusive (8 bit) | |||||
This function performs a exclusive LDR command for 8 bit value. | |||||
\param [in] ptr Pointer to data | |||||
\return value of type uint8_t at (*ptr) | |||||
*/ | |||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) | |||||
{ | |||||
uint8_t result; | |||||
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); | |||||
return(result); | |||||
} | |||||
/** \brief LDR Exclusive (16 bit) | |||||
This function performs a exclusive LDR command for 16 bit values. | |||||
\param [in] ptr Pointer to data | |||||
\return value of type uint16_t at (*ptr) | |||||
*/ | |||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) | |||||
{ | |||||
uint16_t result; | |||||
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); | |||||
return(result); | |||||
} | |||||
/** \brief LDR Exclusive (32 bit) | |||||
This function performs a exclusive LDR command for 32 bit values. | |||||
\param [in] ptr Pointer to data | |||||
\return value of type uint32_t at (*ptr) | |||||
*/ | |||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) | |||||
{ | |||||
uint32_t result; | |||||
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); | |||||
return(result); | |||||
} | |||||
/** \brief STR Exclusive (8 bit) | |||||
This function performs a exclusive STR command for 8 bit values. | |||||
\param [in] value Value to store | |||||
\param [in] ptr Pointer to location | |||||
\return 0 Function succeeded | |||||
\return 1 Function failed | |||||
*/ | |||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) | |||||
{ | |||||
uint32_t result; | |||||
__ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); | |||||
return(result); | |||||
} | |||||
/** \brief STR Exclusive (16 bit) | |||||
This function performs a exclusive STR command for 16 bit values. | |||||
\param [in] value Value to store | |||||
\param [in] ptr Pointer to location | |||||
\return 0 Function succeeded | |||||
\return 1 Function failed | |||||
*/ | |||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) | |||||
{ | |||||
uint32_t result; | |||||
__ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); | |||||
return(result); | |||||
} | |||||
/** \brief STR Exclusive (32 bit) | |||||
This function performs a exclusive STR command for 32 bit values. | |||||
\param [in] value Value to store | |||||
\param [in] ptr Pointer to location | |||||
\return 0 Function succeeded | |||||
\return 1 Function failed | |||||
*/ | |||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) | |||||
{ | |||||
uint32_t result; | |||||
__ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); | |||||
return(result); | |||||
} | |||||
/** \brief Remove the exclusive lock | |||||
This function removes the exclusive lock which is created by LDREX. | |||||
*/ | |||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) | |||||
{ | |||||
__ASM volatile ("clrex"); | |||||
} | |||||
/** \brief Signed Saturate | |||||
This function saturates a signed value. | |||||
\param [in] value Value to be saturated | |||||
\param [in] sat Bit position to saturate to (1..32) | |||||
\return Saturated value | |||||
*/ | |||||
#define __SSAT(ARG1,ARG2) \ | |||||
({ \ | |||||
uint32_t __RES, __ARG1 = (ARG1); \ | |||||
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ | |||||
__RES; \ | |||||
}) | |||||
/** \brief Unsigned Saturate | |||||
This function saturates an unsigned value. | |||||
\param [in] value Value to be saturated | |||||
\param [in] sat Bit position to saturate to (0..31) | |||||
\return Saturated value | |||||
*/ | |||||
#define __USAT(ARG1,ARG2) \ | |||||
({ \ | |||||
uint32_t __RES, __ARG1 = (ARG1); \ | |||||
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ | |||||
__RES; \ | |||||
}) | |||||
/** \brief Count leading zeros | |||||
This function counts the number of leading zeros of a data value. | |||||
\param [in] value Value to count the leading zeros | |||||
\return number of leading zeros in value | |||||
*/ | |||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) | |||||
{ | |||||
uint8_t result; | |||||
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); | |||||
return(result); | |||||
} | |||||
#endif /* (__CORTEX_M >= 0x03) */ | |||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ | |||||
/* TASKING carm specific functions */ | |||||
/* | |||||
* The CMSIS functions have been implemented as intrinsics in the compiler. | |||||
* Please use "carm -?i" to get an up to date list of all intrinsics, | |||||
* Including the CMSIS ones. | |||||
*/ | |||||
#endif | |||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ | |||||
#endif /* __CORE_CMINSTR_H */ |