Merge pull request #2 from PaulStoffregen/master

resync

teensy3/DMAChannel.cpp

@@ -23,14 +23,19 @@ DMAChannel::DMAChannel(uint8_t channelRequest) : TCD(*(TCD_t *)0), channel(16)
 		}
 	}
 	channel = ch;
+	SIM_SCGC7 |= SIM_SCGC7_DMA;
+	SIM_SCGC6 |= SIM_SCGC6_DMAMUX;
+	DMA_CR = DMA_CR_EMLM | DMA_CR_EDBG ; // minor loop mapping is available
+	DMA_CERQ = ch;
+	DMA_CERR = ch;
+	DMA_CEEI = ch;
+	DMA_CINT = ch;
+
 	TCD = *(TCD_t *)(0x40009000 + ch * 32);
 	TCD.CSR = 0;
 	TCD.ATTR = 0;
 	TCD.NBYTES = 0;
 	TCD.BITER = 0;
 	TCD.CITER = 0;
-	SIM_SCGC7 |= SIM_SCGC7_DMA;
-	SIM_SCGC6 |= SIM_SCGC6_DMAMUX;
-	DMA_CR = 0;
 }
 

teensy3/DMAChannel.h

@@ -24,15 +24,20 @@ class DMAChannel {
 	typedef struct __attribute__((packed)) {
 		volatile const void * volatile SADDR;
 		int16_t SOFF;
-		union { uint16_t ATTR; struct { uint8_t ATTR_DST; uint8_t ATTR_SRC; }; };
-		uint32_t NBYTES;
+		union { uint16_t ATTR;
+			struct { uint8_t ATTR_DST; uint8_t ATTR_SRC; }; };
+		union { uint32_t NBYTES; uint32_t NBYTES_MLNO;
+			uint32_t NBYTES_MLOFFNO; uint32_t NBYTES_MLOFFYES; };
 		int32_t SLAST;
 		volatile void * volatile DADDR;
 		int16_t DOFF;
-		volatile uint16_t CITER;
+		union { volatile uint16_t CITER;
+			volatile uint16_t CITER_ELINKYES; volatile uint16_t CITER_ELINKNO; };
 		int32_t DLASTSGA;
 		volatile uint16_t CSR;
-		volatile uint16_t BITER;
+		union { volatile uint16_t BITER;
+			volatile uint16_t BITER_ELINKYES; volatile uint16_t BITER_ELINKNO; };
+
 	} TCD_t;
 public:
 	/*************************************************/
@@ -48,36 +53,62 @@ public:
 	/**    Triggering                     **/
 	/***************************************/
 
-	// Triggers cause the DMA channel to actually move data.
+	// Triggers cause the DMA channel to actually move data.  Each
+	// trigger moves a single data unit, which is typically 8, 16 or 32 bits.
 
 	// Use a hardware trigger to make the DMA channel run
 	void attachTrigger(uint8_t source) {
 		volatile uint8_t *mux;
 		mux = (volatile uint8_t *)&(DMAMUX0_CHCFG0) + channel;
 		*mux = 0;
-		*mux = source | DMAMUX_ENABLE;
+		*mux = (source & 63) | DMAMUX_ENABLE;
 	}
 
 	// Use another DMA channel as the trigger, causing this
-	// channel to trigger every time it triggers.  This
-	// effectively makes the 2 channels run in parallel.
-	void attachTrigger(DMAChannel &channel) {
-
+	// channel to trigger after each transfer is makes, except
+	// the its last transfer.  This effectively makes the 2
+	// channels run in parallel.
+	void attachTriggerBeforeCompletion(DMAChannel &ch) {
+		ch.TCD.BITER = (ch.TCD.BITER & ~DMA_TCD_BITER_ELINKYES_LINKCH_MASK)
+		  | DMA_TCD_BITER_ELINKYES_LINKCH(channel) | DMA_TCD_BITER_ELINKYES_ELINK;
+		ch.TCD.CITER = ch.TCD.BITER ;
 	}
 
 	// Use another DMA channel as the trigger, causing this
 	// channel to trigger when the other channel completes.
-	void attachTriggerOnCompletion(DMAChannel &channel) {
-
+	void attachTriggerAtCompletion(DMAChannel &ch) {
+		ch.TCD.CSR = (ch.TCD.CSR & ~DMA_TCD_CSR_MAJORLINKCH_MASK)
+		  | DMA_TCD_CSR_MAJORLINKCH(channel) | DMA_TCD_CSR_MAJORELINK;
 	}
 
-	void attachTriggerContinuous(DMAChannel &channel) {
-
+	// Cause this DMA channel to be continuously triggered, so
+	// it will move data as rapidly as possible, without waiting.
+	// Normally this would be used with disableOnCompletion().
+	void attachTriggerContinuous(void) {
+		volatile uint8_t *mux = (volatile uint8_t *)&DMAMUX0_CHCFG0;
+		mux[channel] = 0;
+#if DMAMUX_NUM_SOURCE_ALWAYS >= DMA_NUM_CHANNELS
+		mux[channel] = DMAMUX_SOURCE_ALWAYS0 + channel;	
+#else
+		// search for an unused "always on" source
+		unsigned int i = DMAMUX_SOURCE_ALWAYS0;
+		for (i = DMAMUX_SOURCE_ALWAYS0;
+		  i < DMAMUX_SOURCE_ALWAYS0 + DMAMUX_NUM_SOURCE_ALWAYS; i++) {
+			unsigned int ch;
+			for (ch=0; ch < DMA_NUM_CHANNELS; ch++) {
+				if (mux[ch] == i) break;
+			}
+			if (ch >= DMA_NUM_CHANNELS) {
+				mux[channel] = i;
+				return;
+			}
+		}
+#endif
 	}
 
 	// Manually trigger the DMA channel.
 	void trigger(void) {
-
+		DMA_SSRT = channel;
 	}
 
 
@@ -86,19 +117,24 @@ public:
 	/***************************************/
 
 	// An interrupt routine can be run when the DMA channel completes
-	// the entire transfer.
+	// the entire transfer, and also optionally when half of the
+	// transfer is completed.
 	void attachInterrupt(void (*isr)(void)) {
 		_VectorsRam[channel + IRQ_DMA_CH0 + 16] = isr;
 		NVIC_ENABLE_IRQ(IRQ_DMA_CH0 + channel);
+		TCD.CSR |= DMA_TCD_CSR_INTMAJOR;
 	}
 
-	void interruptAtHalf(void) {
+	void detachInterrupt(void) {
+		NVIC_DISABLE_IRQ(IRQ_DMA_CH0 + channel);
+	}
 
+	void interruptAtHalf(void) {
+		TCD.CSR |= DMA_TCD_CSR_INTHALF;
 	}
 
 	void clearInterrupt(void) {
-
-
+		DMA_CINT = channel;
 	}
 
 
@@ -107,15 +143,15 @@ public:
 	/***************************************/
 
 	void enable(void) {
-
+		DMA_SERQ = channel;
 	}
 
 	void disable(void) {
-
+		DMA_CERQ = channel;
 	}
 
 	void disableOnCompletion(void) {
-
+		TCD.CSR |= DMA_TCD_CSR_DREQ;
 	}
 
 
@@ -154,7 +190,8 @@ public:
 
 	// Use a buffer (array of data) as the data source.  Typically a
 	// buffer for transmitting data is used.
-	void sourceBuffer(const signed char p[], unsigned int len) { sourceBuffer((uint8_t *)p, len); }
+	void sourceBuffer(const signed char p[], unsigned int len) {
+		sourceBuffer((uint8_t *)p, len); }
 	void sourceBuffer(const unsigned char p[], unsigned int len) {
 		TCD.SADDR = p;
 		TCD.SOFF = 1;
@@ -164,7 +201,8 @@ public:
 		TCD.BITER = len;
 		TCD.CITER = len;
 	}
-	void sourceBuffer(const signed short p[], unsigned int len) { sourceBuffer((uint16_t *)p, len); }
+	void sourceBuffer(const signed short p[], unsigned int len) {
+		sourceBuffer((uint16_t *)p, len); }
 	void sourceBuffer(const unsigned short p[], unsigned int len) {
 		TCD.SADDR = p;
 		TCD.SOFF = 2;
@@ -174,9 +212,12 @@ public:
 		TCD.BITER = len / 2;
 		TCD.CITER = len / 2;
 	}
-	void sourceBuffer(const signed int p[], unsigned int len) { sourceBuffer((uint32_t *)p, len); }
-	void sourceBuffer(const unsigned int p[], unsigned int len) {sourceBuffer((uint32_t *)p, len); } 
-	void sourceBuffer(const signed long p[], unsigned int len) { sourceBuffer((uint32_t *)p, len); }
+	void sourceBuffer(const signed int p[], unsigned int len) {
+		sourceBuffer((uint32_t *)p, len); }
+	void sourceBuffer(const unsigned int p[], unsigned int len) {
+		sourceBuffer((uint32_t *)p, len); } 
+	void sourceBuffer(const signed long p[], unsigned int len) {
+		sourceBuffer((uint32_t *)p, len); }
 	void sourceBuffer(const unsigned long p[], unsigned int len) {
 		TCD.SADDR = p;
 		TCD.SOFF = 4;
@@ -188,7 +229,8 @@ public:
 	}
 
 	// Use a circular buffer as the data source
-	void sourceCircular(const signed char p[], unsigned int len) { sourceCircular((uint8_t *)p, len); }
+	void sourceCircular(const signed char p[], unsigned int len) {
+		sourceCircular((uint8_t *)p, len); }
 	void sourceCircular(const unsigned char p[], unsigned int len) {
 		TCD.SADDR = p;
 		TCD.SOFF = 1;
@@ -198,7 +240,8 @@ public:
 		TCD.BITER = len;
 		TCD.CITER = len;
 	}
-	void sourceCircular(const signed short p[], unsigned int len) { sourceCircular((uint16_t *)p, len); }
+	void sourceCircular(const signed short p[], unsigned int len) {
+		sourceCircular((uint16_t *)p, len); }
 	void sourceCircular(const unsigned short p[], unsigned int len) {
 		TCD.SADDR = p;
 		TCD.SOFF = 2;
@@ -208,9 +251,12 @@ public:
 		TCD.BITER = len / 2;
 		TCD.CITER = len / 2;
 	}
-	void sourceCircular(const signed int p[], unsigned int len) { sourceCircular((uint32_t *)p, len); }
-	void sourceCircular(const unsigned int p[], unsigned int len) { sourceCircular((uint32_t *)p, len); }
-	void sourceCircular(const signed long p[], unsigned int len) { sourceCircular((uint32_t *)p, len); }
+	void sourceCircular(const signed int p[], unsigned int len) {
+		sourceCircular((uint32_t *)p, len); }
+	void sourceCircular(const unsigned int p[], unsigned int len) {
+		sourceCircular((uint32_t *)p, len); }
+	void sourceCircular(const signed long p[], unsigned int len) {
+		sourceCircular((uint32_t *)p, len); }
 	void sourceCircular(const unsigned long p[], unsigned int len) {
 		TCD.SADDR = p;
 		TCD.SOFF = 4;
@@ -252,7 +298,8 @@ public:
 
 	// Use a buffer (array of data) as the data destination.  Typically a
 	// buffer for receiving data is used.
-	void destinationBuffer(signed char p[], unsigned int len) { destinationBuffer((uint8_t *)p, len); }
+	void destinationBuffer(signed char p[], unsigned int len) {
+		destinationBuffer((uint8_t *)p, len); }
 	void destinationBuffer(unsigned char p[], unsigned int len) {
 		TCD.DADDR = p;
 		TCD.DOFF = 1;
@@ -262,7 +309,8 @@ public:
 		TCD.BITER = len;
 		TCD.CITER = len;
 	}
-	void destinationBuffer(signed short p[], unsigned int len) { destinationBuffer((uint16_t *)p, len); }
+	void destinationBuffer(signed short p[], unsigned int len) {
+		destinationBuffer((uint16_t *)p, len); }
 	void destinationBuffer(unsigned short p[], unsigned int len) {
 		TCD.DADDR = p;
 		TCD.DOFF = 2;
@@ -272,9 +320,12 @@ public:
 		TCD.BITER = len / 2;
 		TCD.CITER = len / 2;
 	}
-	void destinationBuffer(signed int p[], unsigned int len) { destinationBuffer((uint32_t *)p, len); }
-	void destinationBuffer(unsigned int p[], unsigned int len) { destinationBuffer((uint32_t *)p, len); }
-	void destinationBuffer(signed long p[], unsigned int len) { destinationBuffer((uint32_t *)p, len); }
+	void destinationBuffer(signed int p[], unsigned int len) {
+		destinationBuffer((uint32_t *)p, len); }
+	void destinationBuffer(unsigned int p[], unsigned int len) {
+		destinationBuffer((uint32_t *)p, len); }
+	void destinationBuffer(signed long p[], unsigned int len) {
+		destinationBuffer((uint32_t *)p, len); }
 	void destinationBuffer(unsigned long p[], unsigned int len) {
 		TCD.DADDR = p;
 		TCD.DOFF = 4;
@@ -286,7 +337,8 @@ public:
 	}
 
 	// Use a circular buffer as the data destination
-	void destinationCircular(signed char p[], unsigned int len) { destinationCircular((uint8_t *)p, len); }
+	void destinationCircular(signed char p[], unsigned int len) {
+		destinationCircular((uint8_t *)p, len); }
 	void destinationCircular(unsigned char p[], unsigned int len) {
 		TCD.DADDR = p;
 		TCD.DOFF = 1;
@@ -296,7 +348,8 @@ public:
 		TCD.BITER = len;
 		TCD.CITER = len;
 	}
-	void destinationCircular(signed short p[], unsigned int len) { destinationCircular((uint16_t *)p, len); }
+	void destinationCircular(signed short p[], unsigned int len) {
+		destinationCircular((uint16_t *)p, len); }
 	void destinationCircular(unsigned short p[], unsigned int len) {
 		TCD.DADDR = p;
 		TCD.DOFF = 2;
@@ -306,9 +359,12 @@ public:
 		TCD.BITER = len / 2;
 		TCD.CITER = len / 2;
 	}
-	void destinationCircular(signed int p[], unsigned int len) { destinationCircular((uint32_t *)p, len); }
-	void destinationCircular(unsigned int p[], unsigned int len) { destinationCircular((uint32_t *)p, len); }
-	void destinationCircular(signed long p[], unsigned int len) { destinationCircular((uint32_t *)p, len); }
+	void destinationCircular(signed int p[], unsigned int len) {
+		destinationCircular((uint32_t *)p, len); }
+	void destinationCircular(unsigned int p[], unsigned int len) {
+		destinationCircular((uint32_t *)p, len); }
+	void destinationCircular(signed long p[], unsigned int len) {
+		destinationCircular((uint32_t *)p, len); }
 	void destinationCircular(unsigned long p[], unsigned int len) {
 		TCD.DADDR = p;
 		TCD.DOFF = 4;

teensy3/mk20dx128.h

@@ -519,6 +519,7 @@ extern "C" {
 #define DMAMUX_SOURCE_ALWAYS7		61
 #define DMAMUX_SOURCE_ALWAYS8		62
 #define DMAMUX_SOURCE_ALWAYS9		63
+#define DMAMUX_NUM_SOURCE_ALWAYS	10
 
 // Chapter 21: Direct Memory Access Controller (eDMA)
 #define DMA_CR			(*(volatile uint32_t *)0x40008000) // Control Register
@@ -679,7 +680,9 @@ extern "C" {
 #define DMA_TCD_ATTR_SIZE_16BYTE	4
 #define DMA_TCD_ATTR_SIZE_32BYTE	5
 #define DMA_TCD_CSR_BWC(n)		(((n) & 0x3) << 14)
-#define DMA_TCD_CSR_MAJORLINKCH(n)	(((n) & 0x3) << 8)
+#define DMA_TCD_CSR_BWC_MASK		0xC000
+#define DMA_TCD_CSR_MAJORLINKCH(n)	(((n) & 0xF) << 8)
+#define DMA_TCD_CSR_MAJORLINKCH_MASK	0x0F00
 #define DMA_TCD_CSR_DONE		0x0080
 #define DMA_TCD_CSR_ACTIVE		0x0040
 #define DMA_TCD_CSR_MAJORELINK		0x0020
@@ -688,10 +691,20 @@ extern "C" {
 #define DMA_TCD_CSR_INTHALF		0x0004
 #define DMA_TCD_CSR_INTMAJOR		0x0002
 #define DMA_TCD_CSR_START		0x0001
-#define DMA_TCD_CITER_MASK		    ((uint16_t)0x7FFF)	   // Loop count mask
-#define DMA_TCD_CITER_ELINK		    ((uint16_t)1<<15)	   // Enable channel linking on minor-loop complete
-#define DMA_TCD_BITER_MASK		    ((uint16_t)0x7FFF)	   // Loop count mask
-#define DMA_TCD_BITER_ELINK		    ((uint16_t)1<<15)	   // Enable channel linking on minor-loop complete
+#define DMA_TCD_CITER_MASK		((uint16_t)0x7FFF)	   // Loop count mask
+#define DMA_TCD_CITER_ELINK		((uint16_t)1<<15)	   // Enable channel linking on minor-loop complete
+#define DMA_TCD_BITER_MASK		((uint16_t)0x7FFF)	   // Loop count mask
+#define DMA_TCD_BITER_ELINK		((uint16_t)1<<15)	   // Enable channel linking on minor-loop complete
+#define DMA_TCD_BITER_ELINKYES_ELINK		0x8000
+#define DMA_TCD_BITER_ELINKYES_LINKCH(n)	(((n) & 0xF) << 9)
+#define DMA_TCD_BITER_ELINKYES_LINKCH_MASK	0x1E00
+#define DMA_TCD_BITER_ELINKYES_BITER(n)		(((n) & 0x1FF) << 0)
+#define DMA_TCD_BITER_ELINKYES_BITER_MASK	0x01FF
+#define DMA_TCD_CITER_ELINKYES_ELINK		0x8000
+#define DMA_TCD_CITER_ELINKYES_LINKCH(n)	(((n) & 0xF) << 9)
+#define DMA_TCD_CITER_ELINKYES_LINKCH_MASK	0x1E00
+#define DMA_TCD_CITER_ELINKYES_CITER(n)		(((n) & 0x1FF) << 0)
+#define DMA_TCD_CITER_ELINKYES_CITER_MASK	0x01FF
 #define DMA_TCD_NBYTES_SMLOE		    ((uint32_t)1<<31)		    // Source Minor Loop Offset Enable
 #define DMA_TCD_NBYTES_DMLOE		    ((uint32_t)1<<30)		    // Destination Minor Loop Offset Enable
 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES(n)    ((uint32_t)(n))		    // NBytes transfer count when minor loop disabled
@@ -1296,7 +1309,9 @@ extern "C" {
 #define FTM_SC_TOIE			0x40				// Timer Overflow Interrupt Enable
 #define FTM_SC_CPWMS			0x20				// Center-Aligned PWM Select
 #define FTM_SC_CLKS(n)			(((n) & 3) << 3)		// Clock Source Selection
+#define FTM_SC_CLKS_MASK		0x18
 #define FTM_SC_PS(n)			(((n) & 7) << 0)		// Prescale Factor Selection
+#define FTM_SC_PS_MASK			0x07
 #define FTM0_CNT		(*(volatile uint32_t *)0x40038004) // Counter
 #define FTM0_MOD		(*(volatile uint32_t *)0x40038008) // Modulo
 #define FTM0_C0SC		(*(volatile uint32_t *)0x4003800C) // Channel 0 Status And Control
@@ -1324,9 +1339,18 @@ extern "C" {
 #define FTM0_C7V		(*(volatile uint32_t *)0x40038048) // Channel 7 Value
 #define FTM0_CNTIN		(*(volatile uint32_t *)0x4003804C) // Counter Initial Value
 #define FTM0_STATUS		(*(volatile uint32_t *)0x40038050) // Capture And Compare Status
+#define FTM_STATUS_CH7F			0x80				//
+#define FTM_STATUS_CH6F			0x40				//
+#define FTM_STATUS_CH5F			0x20				//
+#define FTM_STATUS_CH4F			0x10				//
+#define FTM_STATUS_CH3F			0x08				//
+#define FTM_STATUS_CH2F			0x04				//
+#define FTM_STATUS_CH1F			0x02				//
+#define FTM_STATUS_CH0F			0x01				//
 #define FTM0_MODE		(*(volatile uint32_t *)0x40038054) // Features Mode Selection
 #define FTM_MODE_FAULTIE		0x80				// Fault Interrupt Enable
 #define FTM_MODE_FAULTM(n)		(((n) & 3) << 5)		// Fault Control Mode
+#define FTM_MODE_FAULTM_MASK		0x60
 #define FTM_MODE_CAPTEST		0x10				// Capture Test Mode Enable
 #define FTM_MODE_PWMSYNC		0x08				// PWM Synchronization Mode
 #define FTM_MODE_WPDIS			0x04				// Write Protection Disable
@@ -1342,21 +1366,170 @@ extern "C" {
 #define FTM_SYNC_CNTMAX			0x02				//
 #define FTM_SYNC_CNTMIN			0x01				//
 #define FTM0_OUTINIT		(*(volatile uint32_t *)0x4003805C) // Initial State For Channels Output
+#define FTM_OUTINIT_CH7OI		0x80				//
+#define FTM_OUTINIT_CH6OI		0x40				//
+#define FTM_OUTINIT_CH5OI		0x20				//
+#define FTM_OUTINIT_CH4OI		0x10				//
+#define FTM_OUTINIT_CH3OI		0x08				//
+#define FTM_OUTINIT_CH2OI		0x04				//
+#define FTM_OUTINIT_CH1OI		0x02				//
+#define FTM_OUTINIT_CH0OI		0x01				//
 #define FTM0_OUTMASK		(*(volatile uint32_t *)0x40038060) // Output Mask
+#define FTM_OUTMASK_CH7OM		0x80				//
+#define FTM_OUTMASK_CH6OM		0x40				//
+#define FTM_OUTMASK_CH5OM		0x20				//
+#define FTM_OUTMASK_CH4OM		0x10				//
+#define FTM_OUTMASK_CH3OM		0x08				//
+#define FTM_OUTMASK_CH2OM		0x04				//
+#define FTM_OUTMASK_CH1OM		0x02				//
+#define FTM_OUTMASK_CH0OM		0x01				//
 #define FTM0_COMBINE		(*(volatile uint32_t *)0x40038064) // Function For Linked Channels
+#define FTM_COMBINE_FAULTEN3		0x40000000			// Enable the fault control, ch #6 & #7
+#define FTM_COMBINE_SYNCEN3		0x20000000			// Enable PWM sync of C6V & C7V
+#define FTM_COMBINE_DTEN3		0x10000000			// Enable deadtime insertion, ch #6 & #7
+#define FTM_COMBINE_DECAP3		0x08000000			// Dual Edge Capture Mode
+#define FTM_COMBINE_DECAPEN3		0x04000000			// Dual Edge Capture Mode Enable
+#define FTM_COMBINE_COMP3		0x02000000			// Complement Of Channel #6 & #7
+#define FTM_COMBINE_COMBINE3		0x01000000			// Combine Channels #6 & #7
+#define FTM_COMBINE_FAULTEN2		0x00400000			// Enable the fault control, ch #4 & #5
+#define FTM_COMBINE_SYNCEN2		0x00200000			// Enable PWM sync of C4V & C5V
+#define FTM_COMBINE_DTEN2		0x00100000			// Enable deadtime insertion, ch #4 & #5
+#define FTM_COMBINE_DECAP2		0x00080000			// Dual Edge Capture Mode
+#define FTM_COMBINE_DECAPEN2		0x00040000			// Dual Edge Capture Mode Enable
+#define FTM_COMBINE_COMP2		0x00020000			// Complement Of Channel #4 & #5
+#define FTM_COMBINE_COMBINE2		0x00010000			// Combine Channels #4 & #5
+#define FTM_COMBINE_FAULTEN1		0x00004000			// Enable the fault control, ch #2 & #3
+#define FTM_COMBINE_SYNCEN1		0x00002000			// Enable PWM sync of C2V & C3V
+#define FTM_COMBINE_DTEN1		0x00001000			// Enable deadtime insertion, ch #2 & #3
+#define FTM_COMBINE_DECAP1		0x00000800			// Dual Edge Capture Mode
+#define FTM_COMBINE_DECAPEN1		0x00000400			// Dual Edge Capture Mode Enable
+#define FTM_COMBINE_COMP1		0x00000200			// Complement Of Channel #2 & #3
+#define FTM_COMBINE_COMBINE1		0x00000100			// Combine Channels #2 & #3
+#define FTM_COMBINE_FAULTEN0		0x00000040			// Enable the fault control, ch #0 & #1
+#define FTM_COMBINE_SYNCEN0		0x00000020			// Enable PWM sync of C0V & C1V
+#define FTM_COMBINE_DTEN0		0x00000010			// Enable deadtime insertion, ch #0 & #1
+#define FTM_COMBINE_DECAP0		0x00000008			// Dual Edge Capture Mode
+#define FTM_COMBINE_DECAPEN0		0x00000004			// Dual Edge Capture Mode Enable
+#define FTM_COMBINE_COMP0		0x00000002			// Complement Of Channel #0 & #1
+#define FTM_COMBINE_COMBINE0		0x00000001			// Combine Channels #0 & #1
 #define FTM0_DEADTIME		(*(volatile uint32_t *)0x40038068) // Deadtime Insertion Control
+#define FTM_DEADTIME_DTPS(n)		(((n) & 3) << 6)		// Prescaler Value, 0=1x, 2=4x, 3=16x
+#define FTM_DEADTIME_DTPS_MASK		0xC0
+#define FTM_DEADTIME_DTVAL(n)		(((n) & 63) << 0)		// Deadtime Value
+#define FTM_DEADTIME_DTVAL_MASK		0x3F
 #define FTM0_EXTTRIG		(*(volatile uint32_t *)0x4003806C) // FTM External Trigger
+#define FTM_EXTTRIG_TRIGF		0x80				// Channel Trigger Flag
+#define FTM_EXTTRIG_INITTRIGEN		0x40				// Initialization Trigger Enable
+#define FTM_EXTTRIG_CH1TRIG		0x20				// Channel 1 Trigger Enable
+#define FTM_EXTTRIG_CH0TRIG		0x10				// Channel 0 Trigger Enable
+#define FTM_EXTTRIG_CH5TRIG		0x08				// Channel 5 Trigger Enable
+#define FTM_EXTTRIG_CH4TRIG		0x04				// Channel 4 Trigger Enable
+#define FTM_EXTTRIG_CH3TRIG		0x02				// Channel 3 Trigger Enable
+#define FTM_EXTTRIG_CH2TRIG		0x01				// Channel 2 Trigger Enable
 #define FTM0_POL		(*(volatile uint32_t *)0x40038070) // Channels Polarity
+#define FTM_POL_POL7			0x80				// Channel 7 Polarity, 0=active high, 1=active low
+#define FTM_POL_POL6			0x40				// Channel 6 Polarity, 0=active high, 1=active low
+#define FTM_POL_POL5			0x20				// Channel 5 Polarity, 0=active high, 1=active low
+#define FTM_POL_POL4			0x10				// Channel 4 Polarity, 0=active high, 1=active low
+#define FTM_POL_POL3			0x08				// Channel 3 Polarity, 0=active high, 1=active low
+#define FTM_POL_POL2			0x04				// Channel 2 Polarity, 0=active high, 1=active low
+#define FTM_POL_POL1			0x02				// Channel 1 Polarity, 0=active high, 1=active low
+#define FTM_POL_POL0			0x01				// Channel 0 Polarity, 0=active high, 1=active low
 #define FTM0_FMS		(*(volatile uint32_t *)0x40038074) // Fault Mode Status
+#define FTM_FMS_FAULTF			0x80				// Fault Detection Flag
+#define FTM_FMS_WPEN			0x40				// Write Protection Enable
+#define FTM_FMS_FAULTIN			0x20				// Fault Inputs
+#define FTM_FMS_FAULTF3			0x08				// Fault Detection Flag 3
+#define FTM_FMS_FAULTF2			0x04				// Fault Detection Flag 2
+#define FTM_FMS_FAULTF1			0x02				// Fault Detection Flag 1
+#define FTM_FMS_FAULTF0			0x01				// Fault Detection Flag 0
 #define FTM0_FILTER		(*(volatile uint32_t *)0x40038078) // Input Capture Filter Control
+#define FTM_FILTER_CH3FVAL(n)		(((n) & 15) << 12)		// Channel 3 Input Filter
+#define FTM_FILTER_CH2FVAL(n)		(((n) & 15) << 8)		// Channel 2 Input Filter
+#define FTM_FILTER_CH1FVAL(n)		(((n) & 15) << 4)		// Channel 1 Input Filter
+#define FTM_FILTER_CH0FVAL(n)		(((n) & 15) << 0)		// Channel 0 Input Filter
+#define FTM_FILTER_CH3FVAL_MASK		0xF000
+#define FTM_FILTER_CH2FVAL_MASK		0x0F00
+#define FTM_FILTER_CH1FVAL_MASK		0x00F0
+#define FTM_FILTER_CH0FVAL_MASK		0x000F
 #define FTM0_FLTCTRL		(*(volatile uint32_t *)0x4003807C) // Fault Control
+#define FTM_FLTCTRL_FFVAL(n)		(((n) & 15) << 8)		// Fault Input Filter Value, 0=disable
+#define FTM_FLTCTRL_FFVAL_MASK		0xF00
+#define FTM_FLTCTRL_FFLTR3EN		0x80				// Fault Input 3 Filter Enable
+#define FTM_FLTCTRL_FFLTR2EN		0x40				// Fault Input 2 Filter Enable
+#define FTM_FLTCTRL_FFLTR1EN		0x20				// Fault Input 1 Filter Enable
+#define FTM_FLTCTRL_FFLTR0EN		0x10				// Fault Input 0 Filter Enable
+#define FTM_FLTCTRL_FAULT3EN		0x08				// Fault Input 3 Enable
+#define FTM_FLTCTRL_FAULT2EN		0x04				// Fault Input 2 Enable
+#define FTM_FLTCTRL_FAULT1EN		0x02				// Fault Input 1 Enable
+#define FTM_FLTCTRL_FAULT0EN		0x01				// Fault Input 0 Enable
 #define FTM0_QDCTRL		(*(volatile uint32_t *)0x40038080) // Quadrature Decoder Control And Status
+#define FTM_QDCTRL_PHAFLTREN		0x80				// Phase A Input Filter Enable
+#define FTM_QDCTRL_PHBFLTREN		0x40				// Phase B Input Filter Enable
+#define FTM_QDCTRL_PHAPOL		0x20				// Phase A Input Polarity
+#define FTM_QDCTRL_PHBPOL		0x10				// Phase B Input Polarity
+#define FTM_QDCTRL_QUADMODE		0x08				// Quadrature Decoder Mode
+#define FTM_QDCTRL_QUADIR		0x04				// FTM Counter Direction In Quadrature Decoder Mode
+#define FTM_QDCTRL_TOFDIR		0x02				// Timer Overflow Direction In Quadrature Decoder Mode
+#define FTM_QDCTRL_QUADEN		0x01				// Quadrature Decoder Mode Enable
 #define FTM0_CONF		(*(volatile uint32_t *)0x40038084) // Configuration
+#define FTM_CONF_GTBEOUT		0x400				// Global Time Base Output
+#define FTM_CONF_GTBEEN			0x200				// Global Time Base Enable
+#define FTM_CONF_BDMMODE		(((n) & 3) << 6)		// Behavior when in debug mode
+#define FTM_CONF_NUMTOF			(((n) & 31) << 0)		// ratio of counter overflows to TOF bit set
 #define FTM0_FLTPOL		(*(volatile uint32_t *)0x40038088) // FTM Fault Input Polarity
+#define FTM_FLTPOL_FLT3POL		0x08				// Fault Input 3 Polarity
+#define FTM_FLTPOL_FLT2POL		0x04				// Fault Input 2 Polarity
+#define FTM_FLTPOL_FLT1POL		0x02				// Fault Input 1 Polarity
+#define FTM_FLTPOL_FLT0POL		0x01				// Fault Input 0 Polarity
 #define FTM0_SYNCONF		(*(volatile uint32_t *)0x4003808C) // Synchronization Configuration
+#define FTM_SYNCONF_HWSOC		0x100000			// Software output control synchronization is activated by a hardware trigger.
+#define FTM_SYNCONF_HWINVC		0x080000			// Inverting control synchronization is activated by a hardware trigger.
+#define FTM_SYNCONF_HWOM		0x040000			// Output mask synchronization is activated by a hardware trigger.
+#define FTM_SYNCONF_HWWRBUF		0x020000			// MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger.
+#define FTM_SYNCONF_HWRSTCNT		0x010000			// FTM counter synchronization is activated by a hardware trigger.
+#define FTM_SYNCONF_SWSOC		0x001000			// Software output control synchronization is activated by the software trigger.
+#define FTM_SYNCONF_SWINVC		0x000800			// Inverting control synchronization is activated by the software trigger.
+#define FTM_SYNCONF_SWOM		0x000400			// Output mask synchronization is activated by the software trigger.
+#define FTM_SYNCONF_SWWRBUF		0x000200			// MOD, CNTIN, and CV registers synchronization is activated by the software trigger.
+#define FTM_SYNCONF_SWRSTCNT		0x000100			// FTM counter synchronization is activated by the software trigger.
+#define FTM_SYNCONF_SYNCMODE		0x000080			// Synchronization Mode, 0=Legacy, 1=Enhanced PWM
+#define FTM_SYNCONF_SWOC		0x000020			// SWOCTRL Register Synchronization
+#define FTM_SYNCONF_INVC		0x000010			// INVCTRL Register Synchronization
+#define FTM_SYNCONF_CNTINC		0x000004			// CNTIN Register Synchronization
+#define FTM_SYNCONF_HWTRIGMODE		0x000001			// Hardware Trigger Mode
 #define FTM0_INVCTRL		(*(volatile uint32_t *)0x40038090) // FTM Inverting Control
+#define FTM_INVCTRL_INV3EN		0x08				// Pair Channels 3 Inverting Enable
+#define FTM_INVCTRL_INV2EN		0x04				// Pair Channels 2 Inverting Enable
+#define FTM_INVCTRL_INV1EN		0x02				// Pair Channels 1 Inverting Enable
+#define FTM_INVCTRL_INV0EN		0x01				// Pair Channels 0 Inverting Enable
 #define FTM0_SWOCTRL		(*(volatile uint32_t *)0x40038094) // FTM Software Output Control
+#define FTM_SWOCTRL_CH7OCV		0x8000				// Channel 7 Software Output Control Value
+#define FTM_SWOCTRL_CH6OCV		0x4000				// Channel 6 Software Output Control Value
+#define FTM_SWOCTRL_CH5OCV		0x2000				// Channel 5 Software Output Control Value
+#define FTM_SWOCTRL_CH4OCV		0x1000				// Channel 4 Software Output Control Value
+#define FTM_SWOCTRL_CH3OCV		0x0800				// Channel 3 Software Output Control Value
+#define FTM_SWOCTRL_CH2OCV		0x0400				// Channel 2 Software Output Control Value
+#define FTM_SWOCTRL_CH1OCV		0x0200				// Channel 1 Software Output Control Value
+#define FTM_SWOCTRL_CH0OCV		0x0100				// Channel 0 Software Output Control Value
+#define FTM_SWOCTRL_CH7OC		0x0080				// Channel 7 Software Output Control Enable
+#define FTM_SWOCTRL_CH6OC		0x0040				// Channel 6 Software Output Control Enable
+#define FTM_SWOCTRL_CH5OC		0x0020				// Channel 5 Software Output Control Enable
+#define FTM_SWOCTRL_CH4OC		0x0010				// Channel 4 Software Output Control Enable
+#define FTM_SWOCTRL_CH3OC		0x0008				// Channel 3 Software Output Control Enable
+#define FTM_SWOCTRL_CH2OC		0x0004				// Channel 2 Software Output Control Enable
+#define FTM_SWOCTRL_CH1OC		0x0002				// Channel 1 Software Output Control Enable
+#define FTM_SWOCTRL_CH0OC		0x0001				// Channel 0 Software Output Control Enable
 #define FTM0_PWMLOAD		(*(volatile uint32_t *)0x40038098) // FTM PWM Load
+#define FTM_PWMLOAD_LDOK		0x200				// Enables the loading of the MOD, CNTIN, and CV registers with the values of their write buffers
+#define FTM_PWMLOAD_CH7SEL		0x80				// Channel 7 Select
+#define FTM_PWMLOAD_CH6SEL		0x40				// Channel 6 Select
+#define FTM_PWMLOAD_CH5SEL		0x20				// Channel 5 Select
+#define FTM_PWMLOAD_CH4SEL		0x10				// Channel 4 Select
+#define FTM_PWMLOAD_CH3SEL		0x08				// Channel 4 Select
+#define FTM_PWMLOAD_CH2SEL		0x04				// Channel 3 Select
+#define FTM_PWMLOAD_CH1SEL		0x02				// Channel 2 Select
+#define FTM_PWMLOAD_CH0SEL		0x01				// Channel 1 Select
 #define FTM1_SC			(*(volatile uint32_t *)0x40039000) // Status And Control
 #define FTM1_CNT		(*(volatile uint32_t *)0x40039004) // Counter
 #define FTM1_MOD		(*(volatile uint32_t *)0x40039008) // Modulo
@@ -2186,6 +2359,7 @@ typedef struct {
 #define IRQ_PORTE		44
 #define IRQ_SOFTWARE		45
 #define NVIC_NUM_INTERRUPTS	46
+#define DMA_NUM_CHANNELS	4
 
 #elif defined(__MK20DX256__)
 #define IRQ_DMA_CH0		0
@@ -2258,6 +2432,7 @@ typedef struct {
 #define IRQ_PORTE		91
 #define IRQ_SOFTWARE		94
 #define NVIC_NUM_INTERRUPTS	95
+#define DMA_NUM_CHANNELS	16
 
 #endif