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*(portControlRegister(hardware->tx_pins[tx_pin_index_].pin)) = IOMUXC_PAD_SRE | IOMUXC_PAD_DSE(3) | IOMUXC_PAD_SPEED(3); |
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*(portControlRegister(hardware->tx_pins[tx_pin_index_].pin)) = IOMUXC_PAD_SRE | IOMUXC_PAD_DSE(3) | IOMUXC_PAD_SPEED(3); |
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*(portConfigRegister(hardware->tx_pins[tx_pin_index_].pin)) = hardware->tx_pins[tx_pin_index_].mux_val; |
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*(portConfigRegister(hardware->tx_pins[tx_pin_index_].pin)) = hardware->tx_pins[tx_pin_index_].mux_val; |
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if (hardware->tx_pins[tx_pin_index_].select_input_register) { |
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*(hardware->tx_pins[tx_pin_index_].select_input_register) = hardware->tx_pins[tx_pin_index_].select_val; |
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} |
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//hardware->rx_mux_register = hardware->rx_mux_val; |
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//hardware->rx_mux_register = hardware->rx_mux_val; |
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//hardware->tx_mux_register = hardware->tx_mux_val; |
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//hardware->tx_mux_register = hardware->tx_mux_val; |
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{ |
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{ |
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uint32_t head, tail; |
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uint32_t head, tail; |
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// WATER> 0 so IDLE involved may want to check if port has already has RX data to retrieve |
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__disable_irq(); |
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head = rx_buffer_head_; |
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head = rx_buffer_head_; |
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tail = rx_buffer_tail_; |
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tail = rx_buffer_tail_; |
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if (head >= tail) return head - tail; |
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return rx_buffer_total_size_ + head - tail; |
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int avail; |
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if (head >= tail) avail = head - tail; |
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else avail = rx_buffer_total_size_ + head - tail; |
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avail += (port->WATER >> 24) & 0x7; |
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__enable_irq(); |
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return avail; |
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} |
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} |
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void HardwareSerial::addStorageForRead(void *buffer, size_t length) |
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void HardwareSerial::addStorageForRead(void *buffer, size_t length) |
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head = rx_buffer_head_; |
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head = rx_buffer_head_; |
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tail = rx_buffer_tail_; |
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tail = rx_buffer_tail_; |
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if (head == tail) return -1; |
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if (head == tail) { |
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__disable_irq(); |
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head = rx_buffer_head_; // reread head to make sure no ISR happened |
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if (head == tail) { |
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// Still empty Now check for stuff in FIFO Queue. |
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int c = -1; // assume nothing to return |
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if (port->WATER & 0x7000000) { |
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c = port->DATA & 0x3ff; // Use only up to 10 bits of data |
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// But we don't want to throw it away... |
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// since queue is empty, just going to reset to front of queue... |
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rx_buffer_head_ = 1; |
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rx_buffer_tail_ = 0; |
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rx_buffer_[1] = c; |
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} |
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__enable_irq(); |
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return c; |
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} |
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__enable_irq(); |
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} |
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if (++tail >= rx_buffer_total_size_) tail = 0; |
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if (++tail >= rx_buffer_total_size_) tail = 0; |
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if (tail < rx_buffer_size_) { |
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if (tail < rx_buffer_size_) { |
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return rx_buffer_[tail]; |
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return rx_buffer_[tail]; |
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head = rx_buffer_head_; |
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head = rx_buffer_head_; |
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tail = rx_buffer_tail_; |
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tail = rx_buffer_tail_; |
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if (head == tail) return -1; |
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if (head == tail) { |
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__disable_irq(); |
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head = rx_buffer_head_; // reread head to make sure no ISR happened |
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if (head == tail) { |
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// Still empty Now check for stuff in FIFO Queue. |
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c = -1; // assume nothing to return |
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if (port->WATER & 0x7000000) { |
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c = port->DATA & 0x3ff; // Use only up to 10 bits of data |
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} |
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__enable_irq(); |
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return c; |
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} |
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__enable_irq(); |
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} |
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if (++tail >= rx_buffer_total_size_) tail = 0; |
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if (++tail >= rx_buffer_total_size_) tail = 0; |
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|
if (tail < rx_buffer_size_) { |
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if (tail < rx_buffer_size_) { |
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|
c = rx_buffer_[tail]; |
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c = rx_buffer_[tail]; |