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Use shift syntax for bitmasks in imxrt.h

teensy4-core
PaulStoffregen 6 years ago
parent
cc57a9cb30
commit
5d1ca45176
1 changed files with 361 additions and 361 deletions
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  1. +361
    -361
      teensy4/imxrt.h

+ 361
- 361
teensy4/imxrt.h View File

@@ -955,22 +955,22 @@ typedef struct {
#define CCM_CCGR5 (IMXRT_CCM.offset07C)
#define CCM_CCGR6 (IMXRT_CCM.offset080)
#define CCM_CMEOR (IMXRT_CCM.offset088)
#define CCM_CCR_RBC_EN ((uint32_t)0x08000000)
#define CCM_CCR_RBC_EN ((uint32_t)(1<<27))
#define CCM_CCR_REG_BYPASS_COUNT(n) ((uint32_t)(((n) & 0x3F) << 21))
#define CCM_CCR_COSC_EN ((uint32_t)0x00001000)
#define CCM_CCR_COSC_EN ((uint32_t)(1<<12))
#define CCM_CCR_OSCNT(n) ((uint32_t)(((n) & 0xFF) << 0))
#define CCM_CSR_COSC_READY ((uint32_t)0x00000020)
#define CCM_CSR_CAMP2_READY ((uint32_t)0x00000008)
#define CCM_CSR_REF_EN_B ((uint32_t)0x00000001)
#define CCM_CCSR_PLL3_SW_CLK_SEL ((uint32_t)0x00000001)
#define CCM_CSR_COSC_READY ((uint32_t)(1<<5))
#define CCM_CSR_CAMP2_READY ((uint32_t)(1<<3))
#define CCM_CSR_REF_EN_B ((uint32_t)(1<<0))
#define CCM_CCSR_PLL3_SW_CLK_SEL ((uint32_t)(1<<0))
#define CCM_CACRR_ARM_PODF(n) ((uint32_t)(((n) & 0x07) << 0))
#define CCM_CBCDR_PERIPH_CLK2_PODF(n) ((uint32_t)(((n) & 0x07) << 27))
#define CCM_CBCDR_PERIPH_CLK_SEL ((uint32_t)0x02000000)
#define CCM_CBCDR_PERIPH_CLK_SEL ((uint32_t)(1<<25))
#define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(((n) & 0x07) << 16))
#define CCM_CBCDR_AHB_PODF(n) ((uint32_t)(((n) & 0x07) << 10))
#define CCM_CBCDR_IPG_PODF(n) ((uint32_t)(((n) & 0x03) << 8))
#define CCM_CBCDR_SEMC_ALT_CLK_SEL ((uint32_t)0x00000080)
#define CCM_CBCDR_SEMC_CLK_SEL ((uint32_t)0x00000040)
#define CCM_CBCDR_SEMC_ALT_CLK_SEL ((uint32_t)(1<<7))
#define CCM_CBCDR_SEMC_CLK_SEL ((uint32_t)(1<<6))
#define CCM_CBCMR_LPSPI_PODF(n) ((uint32_t)(((n) & 0x07) << 26))
#define CCM_CBCMR_LCDIF_PODF(n) ((uint32_t)(((n) & 0x07) << 23))
#define CCM_CBCMR_PRE_PERIPH_CLK_SEL(n) ((uint32_t)(((n) & 0x03) << 18))
@@ -979,12 +979,12 @@ typedef struct {
#define CCM_CBCMR_LPSPI_CLK_SEL(n) ((uint32_t)(((n) & 0x03) << 5))
#define CCM_CSCMR1_FLEXSPI_CLK_SEL(n) ((uint32_t)(((n) & 0x03) << 29))
#define CCM_CSCMR1_FLEXSPI_PODF(n) ((uint32_t)(((n) & 0x07) << 23))
#define CCM_CSCMR1_USDHC2_CLK_SEL ((uint32_t)0x00020000)
#define CCM_CSCMR1_USDHC1_CLK_SEL ((uint32_t)0x00010000)
#define CCM_CSCMR1_USDHC2_CLK_SEL ((uint32_t)(1<<17))
#define CCM_CSCMR1_USDHC1_CLK_SEL ((uint32_t)(1<<16))
#define CCM_CSCMR1_SAI3_CLK_SEL(n) ((uint32_t)(((n) & 0x03) << 14))
#define CCM_CSCMR1_SAI2_CLK_SEL(n) ((uint32_t)(((n) & 0x03) << 12))
#define CCM_CSCMR1_SAI1_CLK_SEL(n) ((uint32_t)(((n) & 0x03) << 10))
#define CCM_CSCMR1_PERCLK_CLK_SEL ((uint32_t)0x00000040)
#define CCM_CSCMR1_PERCLK_CLK_SEL ((uint32_t)(1<<6))
#define CCM_CSCMR1_PERCLK_PODF(n) ((uint32_t)(((n) & 0x3F) << 0))
#define CCM_CSCMR2_FLEXIO2_CLK_SEL(n) ((uint32_t)(((n) & 0x03) << 19))
#define CCM_CSCMR2_CAN_CLK_SEL(n) ((uint32_t)(((n) & 0x03) << 8))
@@ -992,7 +992,7 @@ typedef struct {
#define CCM_CSCDR1_TRACE_PODF(n) ((uint32_t)(((n) & 0x07) << 25))
#define CCM_CSCDR1_USDHC2_PODF(n) ((uint32_t)(((n) & 0x07) << 16))
#define CCM_CSCDR1_USDHC1_PODF(n) ((uint32_t)(((n) & 0x07) << 11))
#define CCM_CSCDR1_UART_CLK_SEL ((uint32_t)0x00000040)
#define CCM_CSCDR1_UART_CLK_SEL ((uint32_t)(1<<6))
#define CCM_CSCDR1_UART_CLK_PODF(n) ((uint32_t)(((n) & 0x3F) << 0))
#define CCM_CS1CDR_FLEXIO2_CLK_PODF(n) ((uint32_t)(((n) & 0x07) << 25))
#define CCM_CS1CDR_SAI3_CLK_PRED(n) ((uint32_t)(((n) & 0x07) << 22))
@@ -1009,55 +1009,55 @@ typedef struct {
#define CCM_CDCDR_FLEXIO1_CLK_PODF(n) ((uint32_t)(((n) & 0x07) << 9))
#define CCM_CDCDR_FLEXIO1_CLK_SEL(n) ((uint32_t)(((n) & 0x03) << 7))
#define CCM_CSCDR2_LPI2C_CLK_PODF(n) ((uint32_t)(((n) & 0x1F) << 19))
#define CCM_CSCDR2_LPI2C_CLK_SEL ((uint32_t)0x00040000)
#define CCM_CSCDR2_LPI2C_CLK_SEL ((uint32_t)(1<<18))
#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL(n) ((uint32_t)(((n) & 0x07) << 15))
#define CCM_CSCDR2_LCDIF_PRED(n) ((uint32_t)(((n) & 0x07) << 12))
#define CCM_CSCDR2_LCDIF_CLK_SEL(n) ((uint32_t)(((n) & 0x07) << 9))
#define CCM_CSCDR3_CSI_PODF(n) ((uint32_t)(((n) & 0x07) << 11))
#define CCM_CSCDR3_CSI_CLK_SEL(n) ((uint32_t)(((n) & 0x03) << 9))
#define CCM_CDHIPR_ARM_PODF_BUSY ((uint32_t)0x00010000)
#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY ((uint32_t)0x00000020)
#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY ((uint32_t)0x00000008)
#define CCM_CDHIPR_AHB_PODF_BUSY ((uint32_t)0x00000002)
#define CCM_CDHIPR_SEMC_PODF_BUSY ((uint32_t)0x00000001)
#define CCM_CLPCR_MASK_L2CC_IDLE ((uint32_t)0x08000000)
#define CCM_CLPCR_MASK_SCU_IDLE ((uint32_t)0x04000000)
#define CCM_CLPCR_MASK_CORE0_WFI ((uint32_t)0x00400000)
#define CCM_CLPCR_BYPASS_LPM_HS0 ((uint32_t)0x00200000)
#define CCM_CLPCR_BYPASS_LPM_HS1 ((uint32_t)0x00080000)
#define CCM_CLPCR_COSC_PWRDOWN ((uint32_t)0x00000800)
#define CCM_CDHIPR_ARM_PODF_BUSY ((uint32_t)(1<<16))
#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY ((uint32_t)(1<<5))
#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY ((uint32_t)(1<<3))
#define CCM_CDHIPR_AHB_PODF_BUSY ((uint32_t)(1<<1))
#define CCM_CDHIPR_SEMC_PODF_BUSY ((uint32_t)(1<<0))
#define CCM_CLPCR_MASK_L2CC_IDLE ((uint32_t)(1<<27))
#define CCM_CLPCR_MASK_SCU_IDLE ((uint32_t)(1<<26))
#define CCM_CLPCR_MASK_CORE0_WFI ((uint32_t)(1<<22))
#define CCM_CLPCR_BYPASS_LPM_HS0 ((uint32_t)(1<<21))
#define CCM_CLPCR_BYPASS_LPM_HS1 ((uint32_t)(1<<19))
#define CCM_CLPCR_COSC_PWRDOWN ((uint32_t)(1<<11))
#define CCM_CLPCR_STBY_COUNT(n) ((uint32_t)(((n) & 0x03) << 9))
#define CCM_CLPCR_VSTBY ((uint32_t)0x00000100)
#define CCM_CLPCR_DIS_REF_OSC ((uint32_t)0x00000080)
#define CCM_CLPCR_SBYOS ((uint32_t)0x00000040)
#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM ((uint32_t)0x00000020)
#define CCM_CLPCR_VSTBY ((uint32_t)(1<<8))
#define CCM_CLPCR_DIS_REF_OSC ((uint32_t)(1<<7))
#define CCM_CLPCR_SBYOS ((uint32_t)(1<<6))
#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM ((uint32_t)(1<<5))
#define CCM_CLPCR_LPM(n) ((uint32_t)(((n) & 0x03) << 0))
#define CCM_CISR_ARM_PODF_LOADED ((uint32_t)0x04000000)
#define CCM_CISR_PERIPH_CLK_SEL_LOADED ((uint32_t)0x00400000)
#define CCM_CISR_AHB_PODF_LOADED ((uint32_t)0x00100000)
#define CCM_CISR_PERIPH2_CLK_SEL_LOADED ((uint32_t)0x00080000)
#define CCM_CISR_SEMC_PODF_LOADED ((uint32_t)0x00020000)
#define CCM_CISR_COSC_READY ((uint32_t)0x00000040)
#define CCM_CISR_LRF_PLL ((uint32_t)0x00000001)
#define CCM_CIMR_ARM_PODF_LOADED ((uint32_t)0x04000000)
#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED ((uint32_t)0x00400000)
#define CCM_CIMR_MASK_AHB_PODF_LOADED ((uint32_t)0x00100000)
#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED ((uint32_t)0x00080000)
#define CCM_CIMR_MASK_SEMC_PODF_LOADED ((uint32_t)0x00020000)
#define CCM_CIMR_MASK_COSC_READY ((uint32_t)0x00000040)
#define CCM_CIMR_MASK_LRF_PLL ((uint32_t)0x00000001)
#define CCM_CCOSR_CLKO2_EN ((uint32_t)0x01000000)
#define CCM_CISR_ARM_PODF_LOADED ((uint32_t)(1<<26))
#define CCM_CISR_PERIPH_CLK_SEL_LOADED ((uint32_t)(1<<22))
#define CCM_CISR_AHB_PODF_LOADED ((uint32_t)(1<<20))
#define CCM_CISR_PERIPH2_CLK_SEL_LOADED ((uint32_t)(1<<19))
#define CCM_CISR_SEMC_PODF_LOADED ((uint32_t)(1<<17))
#define CCM_CISR_COSC_READY ((uint32_t)(1<<6))
#define CCM_CISR_LRF_PLL ((uint32_t)(1<<0))
#define CCM_CIMR_ARM_PODF_LOADED ((uint32_t)(1<<26))
#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED ((uint32_t)(1<<22))
#define CCM_CIMR_MASK_AHB_PODF_LOADED ((uint32_t)(1<<20))
#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED ((uint32_t)(1<<19))
#define CCM_CIMR_MASK_SEMC_PODF_LOADED ((uint32_t)(1<<17))
#define CCM_CIMR_MASK_COSC_READY ((uint32_t)(1<<6))
#define CCM_CIMR_MASK_LRF_PLL ((uint32_t)(1<<0))
#define CCM_CCOSR_CLKO2_EN ((uint32_t)(1<<24))
#define CCM_CCOSR_CLKO2_DIV(n) ((uint32_t)(((n) & 0x07) << 21))
#define CCM_CCOSR_CLKO2_SEL(n) ((uint32_t)(((n) & 0x1F) << 16))
#define CCM_CCOSR_CLK_OUT_SEL ((uint32_t)0x00000100)
#define CCM_CCOSR_CLKO1_EN ((uint32_t)0x00000080)
#define CCM_CCOSR_CLK_OUT_SEL ((uint32_t)(1<<8))
#define CCM_CCOSR_CLKO1_EN ((uint32_t)(1<<7))
#define CCM_CCOSR_CLKO1_DIV(n) ((uint32_t)(((n) & 0x07) << 4))
#define CCM_CCOSR_CLKO1_SEL(n) ((uint32_t)(((n) & 0x0F) << 0))
#define CCM_CGPR_INT_MEM_CLK_LPM ((uint32_t)0x00020000)
#define CCM_CGPR_FPL ((uint32_t)0x00010000)
#define CCM_CGPR_INT_MEM_CLK_LPM ((uint32_t)(1<<17))
#define CCM_CGPR_FPL ((uint32_t)(1<<16))
#define CCM_CGPR_SYS_MEM_DS_CTRL(n) ((uint32_t)(((n) & 0x03) << 14))
#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE ((uint32_t)0x00000010)
#define CCM_CGPR_PMIC_DELAY_SCALER ((uint32_t)0x00000001)
#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE ((uint32_t)(1<<4))
#define CCM_CGPR_PMIC_DELAY_SCALER ((uint32_t)(1<<0))
#define CCM_CCGR_OFF 0
#define CCM_CCGR_ON_RUNONLY 1
#define CCM_CCGR_ON 3
@@ -1167,12 +1167,12 @@ typedef struct {
#define CCM_CCGR6_USDHC2(n) ((uint32_t)(((n) & 0x03) << 4))
#define CCM_CCGR6_USDHC1(n) ((uint32_t)(((n) & 0x03) << 2))
#define CCM_CCGR6_USBOH3(n) ((uint32_t)(((n) & 0x03) << 0))
#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI ((uint32_t)0x40000000)
#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI ((uint32_t)0x10000000)
#define CCM_CMEOR_MOD_EN_OV_TRNG ((uint32_t)0x00000200)
#define CCM_CMEOR_MOD_EN_USDHC ((uint32_t)0x00000080)
#define CCM_CMEOR_MOD_EN_OV_PIT ((uint32_t)0x00000040)
#define CCM_CMEOR_MOD_EN_OV_GPT ((uint32_t)0x00000020)
#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI ((uint32_t)(1<<30))
#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI ((uint32_t)(1<<28))
#define CCM_CMEOR_MOD_EN_OV_TRNG ((uint32_t)(1<<9))
#define CCM_CMEOR_MOD_EN_USDHC ((uint32_t)(1<<7))
#define CCM_CMEOR_MOD_EN_OV_PIT ((uint32_t)(1<<6))
#define CCM_CMEOR_MOD_EN_OV_GPT ((uint32_t)(1<<5))

// 18.8: page 752
#define IMXRT_CCM_ANALOG (*(IMXRT_REGISTER32_t *)0x400D8000)
@@ -2538,18 +2538,18 @@ typedef struct {
#define FLEXRAM_INT_STATUS (IMXRT_FLEXRAM.offset010)
#define FLEXRAM_INT_STAT_EN (IMXRT_FLEXRAM.offset014)
#define FLEXRAM_INT_SIG_EN (IMXRT_FLEXRAM.offset018)
#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON ((uint32_t)0x00000004)
#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN ((uint32_t)0x00000002)
#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN ((uint32_t)0x00000001)
#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS ((uint32_t)0x00000020)
#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS ((uint32_t)0x00000010)
#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS ((uint32_t)0x00000008)
#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN ((uint32_t)0x00000020)
#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN ((uint32_t)0x00000010)
#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN ((uint32_t)0x00000008)
#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN ((uint32_t)0x00000020)
#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN ((uint32_t)0x00000010)
#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN ((uint32_t)0x00000008)
#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON ((uint32_t)(1<<2))
#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN ((uint32_t)(1<<1))
#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN ((uint32_t)(1<<0))
#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS ((uint32_t)(1<<5))
#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS ((uint32_t)(1<<4))
#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS ((uint32_t)(1<<3))
#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN ((uint32_t)(1<<5))
#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN ((uint32_t)(1<<4))
#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN ((uint32_t)(1<<3))
#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN ((uint32_t)(1<<5))
#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN ((uint32_t)(1<<4))
#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN ((uint32_t)(1<<3))

// 30.5.2.1: page 1481
#define IMXRT_FLEXSPI (*(IMXRT_REGISTER32_t *)0x402A8000)
@@ -2893,9 +2893,9 @@ typedef struct {
#define GPC_ISR4 (IMXRT_GPC.offset024)
#define GPC_IMR5 (IMXRT_GPC.offset034)
#define GPC_ISR5 (IMXRT_GPC.offset038)
#define GPC_CNTR_PDRAM0_PGE ((uint32_t)0x00400000)
#define GPC_CNTR_MEGA_PUP_REQ ((uint32_t)0x00000008)
#define GPC_CNTR_MEGA_PDN_REQ ((uint32_t)0x00000004)
#define GPC_CNTR_PDRAM0_PGE ((uint32_t)(1<<22))
#define GPC_CNTR_MEGA_PUP_REQ ((uint32_t)(1<<3))
#define GPC_CNTR_MEGA_PDN_REQ ((uint32_t)(1<<2))
// page 1602
#define PGC_MEGA_CTRL (IMXRT_GPC.offset220)
#define PGC_MEGA_PUPSCR (IMXRT_GPC.offset224)
@@ -2905,18 +2905,18 @@ typedef struct {
#define PGC_CPU_PUPSCR (IMXRT_GPC.offset2A4)
#define PGC_CPU_PDNSCR (IMXRT_GPC.offset2A8)
#define PGC_CPU_SR (IMXRT_GPC.offset2AC)
#define PGC_MEGA_CTRL_PCR ((uint32_t)0x00000001)
#define PGC_MEGA_CTRL_PCR ((uint32_t)(1<<0))
#define PGC_MEGA_PUPSCR_SW2ISO(n) ((uint32_t)(((n) & 0x3F) << 8))
#define PGC_MEGA_PUPSCR_SW(n) ((uint32_t)(((n) & 0x3F) << 0))
#define PGC_MEGA_PDNSCR_ISO2SW(n) ((uint32_t)(((n) & 0x3F) << 8))
#define PGC_MEGA_PDNSCR_ISO(n) ((uint32_t)(((n) & 0x3F) << 0))
#define PGC_MEGA_SR_PSR ((uint32_t)0x00000001)
#define PGC_CPU_CTRL_PCR ((uint32_t)0x00000001)
#define PGC_MEGA_SR_PSR ((uint32_t)(1<<0))
#define PGC_CPU_CTRL_PCR ((uint32_t)(1<<0))
#define PGC_CPU_PUPSCR_SW2ISO(n) ((uint32_t)(((n) & 0x3F) << 8))
#define PGC_CPU_PUPSCR_SW(n) ((uint32_t)(((n) & 0x3F) << 0))
#define PGC_CPU_PDNSCR_ISO2SW(n) ((uint32_t)(((n) & 0x3F) << 8))
#define PGC_CPU_PDNSCR_ISO(n) ((uint32_t)(((n) & 0x3F) << 0))
#define PGC_CPU_SR_PSR ((uint32_t)0x00000001)
#define PGC_CPU_SR_PSR ((uint32_t)(1<<0))

// 32.4.1: page 1620
#define IMXRT_GPIO1 (*(IMXRT_REGISTER32_t *)0x401B8000)
@@ -3032,16 +3032,16 @@ typedef struct {
#define IOMUXC_GPR_GPR23 (IMXRT_IOMUXC_GPR.offset05C)
#define IOMUXC_GPR_GPR24 (IMXRT_IOMUXC_GPR.offset060)
#define IOMUXC_GPR_GPR25 (IMXRT_IOMUXC_GPR.offset064)
#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN ((uint32_t)0x80000000)
#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN ((uint32_t)0x00800000)
#define IOMUXC_GPR_GPR1_EXC_MON ((uint32_t)0x00400000)
#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR ((uint32_t)0x00200000)
#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR ((uint32_t)0x00100000)
#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR ((uint32_t)0x00080000)
#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR ((uint32_t)0x00020000)
#define IOMUXC_GPR_GPR1_USB_EXP_MODE ((uint32_t)0x00008000)
#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL ((uint32_t)0x00002000)
#define IOMUXC_GPR_GPR1_GINT ((uint32_t)0x00001000)
#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN ((uint32_t)(1<<31))
#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN ((uint32_t)(1<<23))
#define IOMUXC_GPR_GPR1_EXC_MON ((uint32_t)(1<<22))
#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR ((uint32_t)(1<<21))
#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR ((uint32_t)(1<<20))
#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR ((uint32_t)(1<<19))
#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR ((uint32_t)(1<<17))
#define IOMUXC_GPR_GPR1_USB_EXP_MODE ((uint32_t)(1<<15))
#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL ((uint32_t)(1<<13))
#define IOMUXC_GPR_GPR1_GINT ((uint32_t)(1<<12))
#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(n) ((uint32_t)(((n) & 0x03) << 10))
#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(n) ((uint32_t)(((n) & 0x03) << 8))
#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(n) ((uint32_t)(((n) & 0x03) << 6))
@@ -3052,161 +3052,161 @@ typedef struct {
#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(3)
#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(7)
#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(7)
#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE ((uint32_t)0x80000000)
#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE ((uint32_t)0x40000000)
#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE ((uint32_t)0x20000000)
#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE ((uint32_t)0x10000000)
#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE ((uint32_t)0x04000000)
#define IOMUXC_GPR_GPR2_MQS_EN ((uint32_t)0x02000000)
#define IOMUXC_GPR_GPR2_MQS_SW_RST ((uint32_t)0x01000000)
#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE ((uint32_t)(1<<31))
#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE ((uint32_t)(1<<30))
#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE ((uint32_t)(1<<29))
#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE ((uint32_t)(1<<28))
#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE ((uint32_t)(1<<26))
#define IOMUXC_GPR_GPR2_MQS_EN ((uint32_t)(1<<25))
#define IOMUXC_GPR_GPR2_MQS_SW_RST ((uint32_t)(1<<24))
#define IOMUXC_GPR_GPR2_MQS_CLK_DIV(n) ((uint32_t)(((n) & 0xFF) << 16))
#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP ((uint32_t)0x00004000)
#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING ((uint32_t)0x00001000)
#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP ((uint32_t)(1<<14))
#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING ((uint32_t)(1<<12))
#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK IOMUXC_GPR_GPR2_MQS_CLK_DIV(255)
#define IOMUXC_GPR_GPR3_OCRAM_STATUS(n) ((uint32_t)(((n) & 0x0F) << 16))
#define IOMUXC_GPR_GPR3_DCP_KEY_SEL ((uint32_t)0x00000010)
#define IOMUXC_GPR_GPR3_DCP_KEY_SEL ((uint32_t)(1<<4))
#define IOMUXC_GPR_GPR3_OCRAM_CTL(n) ((uint32_t)(((n) & 0x0F) << 0))
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK ((uint32_t)0x20000000)
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK ((uint32_t)0x10000000)
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK ((uint32_t)0x08000000)
#define IOMUXC_GPR_GPR4_PIT_STOP_ACK ((uint32_t)0x04000000)
#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK ((uint32_t)0x02000000)
#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK ((uint32_t)0x00800000)
#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK ((uint32_t)0x00400000)
#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK ((uint32_t)0x00200000)
#define IOMUXC_GPR_GPR4_ENET_STOP_ACK ((uint32_t)0x00100000)
#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK ((uint32_t)0x00080000)
#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK ((uint32_t)0x00040000)
#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK ((uint32_t)0x00020000)
#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK ((uint32_t)0x00010000)
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ ((uint32_t)0x00002000)
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ ((uint32_t)0x00001000)
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ ((uint32_t)0x00000800)
#define IOMUXC_GPR_GPR4_PIT_STOP_REQ ((uint32_t)0x00000400)
#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ ((uint32_t)0x00000200)
#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ ((uint32_t)0x00000080)
#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ ((uint32_t)0x00000040)
#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ ((uint32_t)0x00000020)
#define IOMUXC_GPR_GPR4_ENET_STOP_REQ ((uint32_t)0x00000010)
#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ ((uint32_t)0x00000008)
#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ ((uint32_t)0x00000004)
#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ ((uint32_t)0x00000002)
#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2 ((uint32_t)0x20000000)
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1 ((uint32_t)0x10000000)
#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL ((uint32_t)0x02000000)
#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL ((uint32_t)0x01000000)
#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL ((uint32_t)0x00800000)
#define IOMUXC_GPR_GPR5_WDOG2_MASK ((uint32_t)0x00000080)
#define IOMUXC_GPR_GPR5_WDOG1_MASK ((uint32_t)0x00000040)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19 ((uint32_t)0x80000000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18 ((uint32_t)0x40000000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17 ((uint32_t)0x20000000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16 ((uint32_t)0x10000000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15 ((uint32_t)0x08000000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14 ((uint32_t)0x04000000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13 ((uint32_t)0x02000000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12 ((uint32_t)0x01000000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11 ((uint32_t)0x00800000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10 ((uint32_t)0x00400000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9 ((uint32_t)0x00200000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8 ((uint32_t)0x00100000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7 ((uint32_t)0x00080000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6 ((uint32_t)0x00040000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5 ((uint32_t)0x00020000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4 ((uint32_t)0x00010000)
#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL ((uint32_t)0x00008000)
#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL ((uint32_t)0x00004000)
#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL ((uint32_t)0x00002000)
#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL ((uint32_t)0x00001000)
#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL ((uint32_t)0x00000800)
#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL ((uint32_t)0x00000400)
#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL ((uint32_t)0x00000200)
#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL ((uint32_t)0x00000100)
#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL ((uint32_t)0x00000080)
#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL ((uint32_t)0x00000040)
#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL ((uint32_t)0x00000020)
#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL ((uint32_t)0x00000010)
#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL ((uint32_t)0x00000008)
#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL ((uint32_t)0x00000004)
#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL ((uint32_t)0x00000002)
#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK ((uint32_t)0x80000000)
#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK ((uint32_t)0x40000000)
#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK ((uint32_t)0x20000000)
#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK ((uint32_t)0x10000000)
#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK ((uint32_t)0x08000000)
#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK ((uint32_t)0x04000000)
#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK ((uint32_t)0x02000000)
#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK ((uint32_t)0x01000000)
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK ((uint32_t)0x00800000)
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK ((uint32_t)0x00400000)
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK ((uint32_t)0x00200000)
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK ((uint32_t)0x00100000)
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK ((uint32_t)0x00080000)
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK ((uint32_t)0x00040000)
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK ((uint32_t)0x00020000)
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK ((uint32_t)0x00010000)
#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ ((uint32_t)0x00008000)
#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ ((uint32_t)0x00004000)
#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ ((uint32_t)0x00002000)
#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ ((uint32_t)0x00001000)
#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ ((uint32_t)0x00000800)
#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ ((uint32_t)0x00000400)
#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ ((uint32_t)0x00000200)
#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ ((uint32_t)0x00000100)
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ ((uint32_t)0x00000080)
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ ((uint32_t)0x00000040)
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ ((uint32_t)0x00000020)
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ ((uint32_t)0x00000010)
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ ((uint32_t)0x00000008)
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ ((uint32_t)0x00000004)
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ ((uint32_t)0x00000002)
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE ((uint32_t)0x80000000)
#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE ((uint32_t)0x40000000)
#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE ((uint32_t)0x20000000)
#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE ((uint32_t)0x10000000)
#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE ((uint32_t)0x08000000)
#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE ((uint32_t)0x04000000)
#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE ((uint32_t)0x02000000)
#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE ((uint32_t)0x01000000)
#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE ((uint32_t)0x00800000)
#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE ((uint32_t)0x00400000)
#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE ((uint32_t)0x00200000)
#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE ((uint32_t)0x00100000)
#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE ((uint32_t)0x00080000)
#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE ((uint32_t)0x00040000)
#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE ((uint32_t)0x00020000)
#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE ((uint32_t)0x00010000)
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE ((uint32_t)0x00008000)
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE ((uint32_t)0x00004000)
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE ((uint32_t)0x00002000)
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE ((uint32_t)0x00001000)
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE ((uint32_t)0x00000800)
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE ((uint32_t)0x00000400)
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE ((uint32_t)0x00000200)
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE ((uint32_t)0x00000100)
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE ((uint32_t)0x00000080)
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE ((uint32_t)0x00000040)
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE ((uint32_t)0x00000020)
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE ((uint32_t)0x00000010)
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE ((uint32_t)0x00000008)
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE ((uint32_t)0x00000004)
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE ((uint32_t)0x00000002)
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK ((uint32_t)(1<<29))
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK ((uint32_t)(1<<28))
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK ((uint32_t)(1<<27))
#define IOMUXC_GPR_GPR4_PIT_STOP_ACK ((uint32_t)(1<<26))
#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK ((uint32_t)(1<<25))
#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK ((uint32_t)(1<<23))
#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK ((uint32_t)(1<<22))
#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK ((uint32_t)(1<<21))
#define IOMUXC_GPR_GPR4_ENET_STOP_ACK ((uint32_t)(1<<20))
#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK ((uint32_t)(1<<19))
#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK ((uint32_t)(1<<18))
#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK ((uint32_t)(1<<17))
#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK ((uint32_t)(1<<16))
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ ((uint32_t)(1<<13))
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ ((uint32_t)(1<<12))
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ ((uint32_t)(1<<11))
#define IOMUXC_GPR_GPR4_PIT_STOP_REQ ((uint32_t)(1<<10))
#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ ((uint32_t)(1<<9))
#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ ((uint32_t)(1<<7))
#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ ((uint32_t)(1<<6))
#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ ((uint32_t)(1<<5))
#define IOMUXC_GPR_GPR4_ENET_STOP_REQ ((uint32_t)(1<<4))
#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ ((uint32_t)(1<<3))
#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ ((uint32_t)(1<<2))
#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ ((uint32_t)(1<<1))
#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ ((uint32_t)(1<<0))
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2 ((uint32_t)(1<<29))
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1 ((uint32_t)(1<<28))
#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL ((uint32_t)(1<<25))
#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL ((uint32_t)(1<<24))
#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL ((uint32_t)(1<<23))
#define IOMUXC_GPR_GPR5_WDOG2_MASK ((uint32_t)(1<<7))
#define IOMUXC_GPR_GPR5_WDOG1_MASK ((uint32_t)(1<<6))
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19 ((uint32_t)(1<<31))
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18 ((uint32_t)(1<<30))
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17 ((uint32_t)(1<<29))
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16 ((uint32_t)(1<<28))
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15 ((uint32_t)(1<<27))
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14 ((uint32_t)(1<<26))
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13 ((uint32_t)(1<<25))
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12 ((uint32_t)(1<<24))
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11 ((uint32_t)(1<<23))
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10 ((uint32_t)(1<<22))
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9 ((uint32_t)(1<<21))
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8 ((uint32_t)(1<<20))
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7 ((uint32_t)(1<<19))
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6 ((uint32_t)(1<<18))
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5 ((uint32_t)(1<<17))
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4 ((uint32_t)(1<<16))
#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL ((uint32_t)(1<<15))
#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL ((uint32_t)(1<<14))
#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL ((uint32_t)(1<<13))
#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL ((uint32_t)(1<<12))
#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL ((uint32_t)(1<<11))
#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL ((uint32_t)(1<<10))
#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL ((uint32_t)(1<<9))
#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL ((uint32_t)(1<<8))
#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL ((uint32_t)(1<<7))
#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL ((uint32_t)(1<<6))
#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL ((uint32_t)(1<<5))
#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL ((uint32_t)(1<<4))
#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL ((uint32_t)(1<<3))
#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL ((uint32_t)(1<<2))
#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL ((uint32_t)(1<<1))
#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL ((uint32_t)(1<<0))
#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK ((uint32_t)(1<<31))
#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK ((uint32_t)(1<<30))
#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK ((uint32_t)(1<<29))
#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK ((uint32_t)(1<<28))
#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK ((uint32_t)(1<<27))
#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK ((uint32_t)(1<<26))
#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK ((uint32_t)(1<<25))
#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK ((uint32_t)(1<<24))
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK ((uint32_t)(1<<23))
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK ((uint32_t)(1<<22))
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK ((uint32_t)(1<<21))
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK ((uint32_t)(1<<20))
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK ((uint32_t)(1<<19))
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK ((uint32_t)(1<<18))
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK ((uint32_t)(1<<17))
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK ((uint32_t)(1<<16))
#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ ((uint32_t)(1<<15))
#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ ((uint32_t)(1<<14))
#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ ((uint32_t)(1<<13))
#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ ((uint32_t)(1<<12))
#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ ((uint32_t)(1<<11))
#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ ((uint32_t)(1<<10))
#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ ((uint32_t)(1<<9))
#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ ((uint32_t)(1<<8))
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ ((uint32_t)(1<<7))
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ ((uint32_t)(1<<6))
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ ((uint32_t)(1<<5))
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ ((uint32_t)(1<<4))
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ ((uint32_t)(1<<3))
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ ((uint32_t)(1<<2))
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ ((uint32_t)(1<<1))
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ ((uint32_t)(1<<0))
#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE ((uint32_t)(1<<31))
#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE ((uint32_t)(1<<30))
#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE ((uint32_t)(1<<29))
#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE ((uint32_t)(1<<28))
#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE ((uint32_t)(1<<27))
#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE ((uint32_t)(1<<26))
#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE ((uint32_t)(1<<25))
#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE ((uint32_t)(1<<24))
#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE ((uint32_t)(1<<23))
#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE ((uint32_t)(1<<22))
#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE ((uint32_t)(1<<21))
#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE ((uint32_t)(1<<20))
#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE ((uint32_t)(1<<19))
#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE ((uint32_t)(1<<18))
#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE ((uint32_t)(1<<17))
#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE ((uint32_t)(1<<16))
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE ((uint32_t)(1<<15))
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE ((uint32_t)(1<<14))
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE ((uint32_t)(1<<13))
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE ((uint32_t)(1<<12))
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE ((uint32_t)(1<<11))
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE ((uint32_t)(1<<10))
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE ((uint32_t)(1<<9))
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE ((uint32_t)(1<<8))
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE ((uint32_t)(1<<7))
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE ((uint32_t)(1<<6))
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE ((uint32_t)(1<<5))
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE ((uint32_t)(1<<4))
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE ((uint32_t)(1<<3))
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE ((uint32_t)(1<<2))
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE ((uint32_t)(1<<1))
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE ((uint32_t)(1<<0))
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(n) ((uint32_t)(((n) & 0x7F) << 25))
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN ((uint32_t)0x01000000)
#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX ((uint32_t)0x00100000)
#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP ((uint32_t)0x00040000)
#define IOMUXC_GPR_GPR10_LOCK_DBG_EN ((uint32_t)0x00020000)
#define IOMUXC_GPR_GPR10_LOCK_NIDEN ((uint32_t)0x00010000)
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN ((uint32_t)(1<<24))
#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX ((uint32_t)(1<<20))
#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP ((uint32_t)(1<<18))
#define IOMUXC_GPR_GPR10_LOCK_DBG_EN ((uint32_t)(1<<17))
#define IOMUXC_GPR_GPR10_LOCK_NIDEN ((uint32_t)(1<<16))
#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(n) ((uint32_t)(((n) & 0x7F) << 9))
#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN ((uint32_t)0x00000100)
#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX ((uint32_t)0x00000010)
#define IOMUXC_GPR_GPR10_SEC_ERR_RESP ((uint32_t)0x00000004)
#define IOMUXC_GPR_GPR10_DBG_EN ((uint32_t)0x00000002)
#define IOMUXC_GPR_GPR10_NIDEN ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN ((uint32_t)(1<<8))
#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX ((uint32_t)(1<<4))
#define IOMUXC_GPR_GPR10_SEC_ERR_RESP ((uint32_t)(1<<2))
#define IOMUXC_GPR_GPR10_DBG_EN ((uint32_t)(1<<1))
#define IOMUXC_GPR_GPR10_NIDEN ((uint32_t)(1<<0))
#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN(n) ((uint32_t)(((n) & 0x0F) << 24))
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL(n) ((uint32_t)(((n) & 0x03) << 22))
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL(n) ((uint32_t)(((n) & 0x03) << 20))
@@ -3217,49 +3217,49 @@ typedef struct {
#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(n) ((uint32_t)(((n) & 0x03) << 4))
#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(n) ((uint32_t)(((n) & 0x03) << 2))
#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(n) ((uint32_t)(((n) & 0x03) << 0))
#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE ((uint32_t)0x00000010)
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE ((uint32_t)0x00000008)
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE ((uint32_t)0x00000004)
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE ((uint32_t)0x00000002)
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR13_CACHE_USB ((uint32_t)0x00002000)
#define IOMUXC_GPR_GPR13_CACHE_ENET ((uint32_t)0x00000080)
#define IOMUXC_GPR_GPR13_AWCACHE_USDHC ((uint32_t)0x00000002)
#define IOMUXC_GPR_GPR13_ARCACHE_USDHC ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE ((uint32_t)(1<<4))
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE ((uint32_t)(1<<3))
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE ((uint32_t)(1<<2))
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE ((uint32_t)(1<<1))
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE ((uint32_t)(1<<0))
#define IOMUXC_GPR_GPR13_CACHE_USB ((uint32_t)(1<<13))
#define IOMUXC_GPR_GPR13_CACHE_ENET ((uint32_t)(1<<7))
#define IOMUXC_GPR_GPR13_AWCACHE_USDHC ((uint32_t)(1<<1))
#define IOMUXC_GPR_GPR13_ARCACHE_USDHC ((uint32_t)(1<<0))
#define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ(n) ((uint32_t)(((n) & 0x0F) << 20))
#define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ(n) ((uint32_t)(((n) & 0x0F) << 16))
#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN ((uint32_t)0x00000800)
#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN ((uint32_t)0x00000400)
#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN ((uint32_t)0x00000200)
#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN ((uint32_t)0x00000100)
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP ((uint32_t)0x00000080)
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP ((uint32_t)0x00000040)
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP ((uint32_t)0x00000020)
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP ((uint32_t)0x00000010)
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN ((uint32_t)0x00000008)
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN ((uint32_t)0x00000004)
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN ((uint32_t)0x00000002)
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN ((uint32_t)(1<<11))
#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN ((uint32_t)(1<<10))
#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN ((uint32_t)(1<<9))
#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN ((uint32_t)(1<<8))
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP ((uint32_t)(1<<7))
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP ((uint32_t)(1<<6))
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP ((uint32_t)(1<<5))
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP ((uint32_t)(1<<4))
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN ((uint32_t)(1<<3))
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN ((uint32_t)(1<<2))
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN ((uint32_t)(1<<1))
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN ((uint32_t)(1<<0))
#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR(n) ((uint32_t)(((n) & 0x1FFFFFF) << 7))
#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL ((uint32_t)0x00000004)
#define IOMUXC_GPR_GPR16_INIT_DTCM_EN ((uint32_t)0x00000002)
#define IOMUXC_GPR_GPR16_INIT_ITCM_EN ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL ((uint32_t)(1<<2))
#define IOMUXC_GPR_GPR16_INIT_DTCM_EN ((uint32_t)(1<<1))
#define IOMUXC_GPR_GPR16_INIT_ITCM_EN ((uint32_t)(1<<0))
#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(n) ((uint32_t)(((n) & 0x1FFFFFFF) << 3))
#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT ((uint32_t)(1<<0))
#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(n) ((uint32_t)(((n) & 0x1FFFFFFF) << 3))
#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP ((uint32_t)(1<<0))
#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(n) ((uint32_t)(((n) & 0x1FFFFFFF) << 3))
#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT ((uint32_t)(1<<0))
#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(n) ((uint32_t)(((n) & 0x1FFFFFFF) << 3))
#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP ((uint32_t)(1<<0))
#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(n) ((uint32_t)(((n) & 0x1FFFFFFF) << 3))
#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT ((uint32_t)(1<<0))
#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(n) ((uint32_t)(((n) & 0x1FFFFFFF) << 3))
#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP ((uint32_t)(1<<0))
#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT(n) ((uint32_t)(((n) & 0x1FFFFFFF) << 3))
#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT ((uint32_t)(1<<0))
#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(n) ((uint32_t)(((n) & 0x1FFFFFFF) << 3))
#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP ((uint32_t)(1<<0))

// 34.5: page 1717
#define IMXRT_IOMUXC_SNVS (*(IMXRT_REGISTER32_t *)0x400A8000)
@@ -3685,14 +3685,14 @@ typedef struct {
#define IOMUXC_XBAR1_IN25_SELECT_INPUT (IMXRT_IOMUXC_b.offset250)
#define IOMUXC_XBAR1_IN19_SELECT_INPUT (IMXRT_IOMUXC_b.offset254)
#define IOMUXC_XBAR1_IN21_SELECT_INPUT (IMXRT_IOMUXC_b.offset258)
#define IOMUXC_PAD_SRE ((uint32_t)0x00000001)
#define IOMUXC_PAD_SRE ((uint32_t)(1<<0))
#define IOMUXC_PAD_DSE(n) ((uint32_t)(((n) & 0x07) << 3))
#define IOMUXC_PAD_SPEED(n) ((uint32_t)(((n) & 0x03) << 6))
#define IOMUXC_PAD_ODE ((uint32_t)0x00000800)
#define IOMUXC_PAD_PKE ((uint32_t)0x00001000)
#define IOMUXC_PAD_PUE ((uint32_t)0x00002000)
#define IOMUXC_PAD_ODE ((uint32_t)(1<<11))
#define IOMUXC_PAD_PKE ((uint32_t)(1<<12))
#define IOMUXC_PAD_PUE ((uint32_t)(1<<13))
#define IOMUXC_PAD_PUS(n) ((uint32_t)(((n) & 0x03) << 14))
#define IOMUXC_PAD_HYS ((uint32_t)0x00010000)
#define IOMUXC_PAD_HYS ((uint32_t)(1<<16))

// 35.6: page 2301
#define IMXRT_KPP (*(IMXRT_REGISTER16_t *)0x401FC000)
@@ -4087,95 +4087,95 @@ typedef struct {
#define LPUART_VERID_FEATURE(n) ((uint32_t)(((n) & 0xFFFF) << 0))
#define LPUART_PARAM_RXFIFO(n) ((uint32_t)(((n) & 0xFF) << 8))
#define LPUART_PARAM_TXFIFO(n) ((uint32_t)(((n) & 0xFF) << 0))
#define LPUART_GLOBAL_RST ((uint32_t)0x00000002)
#define LPUART_GLOBAL_RST ((uint32_t)(1<<1))
#define LPUART_PINCFG_TRGSEL(n) ((uint32_t)(((n) & 0x03) << 0))
#define LPUART_BAUD_MAEN1 ((uint32_t)0x80000000)
#define LPUART_BAUD_MAEN2 ((uint32_t)0x40000000)
#define LPUART_BAUD_M10 ((uint32_t)0x20000000)
#define LPUART_BAUD_MAEN1 ((uint32_t)(1<<31))
#define LPUART_BAUD_MAEN2 ((uint32_t)(1<<30))
#define LPUART_BAUD_M10 ((uint32_t)(1<<29))
#define LPUART_BAUD_OSR(n) ((uint32_t)(((n) & 0x1F) << 24))
#define LPUART_BAUD_TDMAE ((uint32_t)0x00800000)
#define LPUART_BAUD_RDMAE ((uint32_t)0x00200000)
#define LPUART_BAUD_TDMAE ((uint32_t)(1<<23))
#define LPUART_BAUD_RDMAE ((uint32_t)(1<<21))
#define LPUART_BAUD_MATCFG(n) ((uint32_t)(((n) & 0x03) << 18))
#define LPUART_BAUD_BOTHEDGE ((uint32_t)0x00020000)
#define LPUART_BAUD_RESYNCDIS ((uint32_t)0x00010000)
#define LPUART_BAUD_LBKDIE ((uint32_t)0x00008000)
#define LPUART_BAUD_RXEDGIE ((uint32_t)0x00004000)
#define LPUART_BAUD_SBNS ((uint32_t)0x00002000)
#define LPUART_BAUD_BOTHEDGE ((uint32_t)(1<<17))
#define LPUART_BAUD_RESYNCDIS ((uint32_t)(1<<16))
#define LPUART_BAUD_LBKDIE ((uint32_t)(1<<15))
#define LPUART_BAUD_RXEDGIE ((uint32_t)(1<<14))
#define LPUART_BAUD_SBNS ((uint32_t)(1<<13))
#define LPUART_BAUD_SBR(n) ((uint32_t)(((n) & 0x01FFF) << 0))
#define LPUART_STAT_LBKDIF ((uint32_t)0x80000000)
#define LPUART_STAT_RXEDGIF ((uint32_t)0x40000000)
#define LPUART_STAT_MSBF ((uint32_t)0x20000000)
#define LPUART_STAT_RXINV ((uint32_t)0x10000000)
#define LPUART_STAT_RWUID ((uint32_t)0x08000000)
#define LPUART_STAT_BRK13 ((uint32_t)0x04000000)
#define LPUART_STAT_LBKDE ((uint32_t)0x02000000)
#define LPUART_STAT_RAF ((uint32_t)0x01000000)
#define LPUART_STAT_TDRE ((uint32_t)0x00800000)
#define LPUART_STAT_TC ((uint32_t)0x00400000)
#define LPUART_STAT_RDRF ((uint32_t)0x00200000)
#define LPUART_STAT_IDLE ((uint32_t)0x00100000)
#define LPUART_STAT_OR ((uint32_t)0x00080000)
#define LPUART_STAT_NF ((uint32_t)0x00040000)
#define LPUART_STAT_FE ((uint32_t)0x00020000)
#define LPUART_STAT_PF ((uint32_t)0x00010000)
#define LPUART_STAT_MA1F ((uint32_t)0x00008000)
#define LPUART_STAT_MA2F ((uint32_t)0x00004000)
#define LPUART_CTRL_R8T9 ((uint32_t)0x80000000)
#define LPUART_CTRL_R9T8 ((uint32_t)0x40000000)
#define LPUART_CTRL_TXDIR ((uint32_t)0x20000000)
#define LPUART_CTRL_TXINV ((uint32_t)0x10000000)
#define LPUART_CTRL_ORIE ((uint32_t)0x08000000)
#define LPUART_CTRL_NEIE ((uint32_t)0x04000000)
#define LPUART_CTRL_FEIE ((uint32_t)0x02000000)
#define LPUART_CTRL_PEIE ((uint32_t)0x01000000)
#define LPUART_CTRL_TIE ((uint32_t)0x00800000)
#define LPUART_CTRL_TCIE ((uint32_t)0x00400000)
#define LPUART_CTRL_RIE ((uint32_t)0x00200000)
#define LPUART_CTRL_ILIE ((uint32_t)0x00100000)
#define LPUART_CTRL_TE ((uint32_t)0x00080000)
#define LPUART_CTRL_RE ((uint32_t)0x00040000)
#define LPUART_CTRL_RWU ((uint32_t)0x00020000)
#define LPUART_CTRL_SBK ((uint32_t)0x00010000)
#define LPUART_CTRL_MA1IE ((uint32_t)0x00008000)
#define LPUART_CTRL_MA2IE ((uint32_t)0x00004000)
#define LPUART_CTRL_M7 ((uint32_t)0x00000800)
#define LPUART_STAT_LBKDIF ((uint32_t)(1<<31))
#define LPUART_STAT_RXEDGIF ((uint32_t)(1<<30))
#define LPUART_STAT_MSBF ((uint32_t)(1<<29))
#define LPUART_STAT_RXINV ((uint32_t)(1<<28))
#define LPUART_STAT_RWUID ((uint32_t)(1<<27))
#define LPUART_STAT_BRK13 ((uint32_t)(1<<26))
#define LPUART_STAT_LBKDE ((uint32_t)(1<<25))
#define LPUART_STAT_RAF ((uint32_t)(1<<24))
#define LPUART_STAT_TDRE ((uint32_t)(1<<23))
#define LPUART_STAT_TC ((uint32_t)(1<<22))
#define LPUART_STAT_RDRF ((uint32_t)(1<<21))
#define LPUART_STAT_IDLE ((uint32_t)(1<<20))
#define LPUART_STAT_OR ((uint32_t)(1<<19))
#define LPUART_STAT_NF ((uint32_t)(1<<18))
#define LPUART_STAT_FE ((uint32_t)(1<<17))
#define LPUART_STAT_PF ((uint32_t)(1<<16))
#define LPUART_STAT_MA1F ((uint32_t)(1<<15))
#define LPUART_STAT_MA2F ((uint32_t)(1<<14))
#define LPUART_CTRL_R8T9 ((uint32_t)(1<<31))
#define LPUART_CTRL_R9T8 ((uint32_t)(1<<30))
#define LPUART_CTRL_TXDIR ((uint32_t)(1<<29))
#define LPUART_CTRL_TXINV ((uint32_t)(1<<28))
#define LPUART_CTRL_ORIE ((uint32_t)(1<<27))
#define LPUART_CTRL_NEIE ((uint32_t)(1<<26))
#define LPUART_CTRL_FEIE ((uint32_t)(1<<25))
#define LPUART_CTRL_PEIE ((uint32_t)(1<<24))
#define LPUART_CTRL_TIE ((uint32_t)(1<<23))
#define LPUART_CTRL_TCIE ((uint32_t)(1<<22))
#define LPUART_CTRL_RIE ((uint32_t)(1<<21))
#define LPUART_CTRL_ILIE ((uint32_t)(1<<20))
#define LPUART_CTRL_TE ((uint32_t)(1<<19))
#define LPUART_CTRL_RE ((uint32_t)(1<<18))
#define LPUART_CTRL_RWU ((uint32_t)(1<<17))
#define LPUART_CTRL_SBK ((uint32_t)(1<<16))
#define LPUART_CTRL_MA1IE ((uint32_t)(1<<15))
#define LPUART_CTRL_MA2IE ((uint32_t)(1<<14))
#define LPUART_CTRL_M7 ((uint32_t)(1<<11))
#define LPUART_CTRL_IDLECFG(n) ((uint32_t)(((n) & 0x07) << 8))
#define LPUART_CTRL_LOOPS ((uint32_t)0x00000080)
#define LPUART_CTRL_DOZEEN ((uint32_t)0x00000040)
#define LPUART_CTRL_RSRC ((uint32_t)0x00000020)
#define LPUART_CTRL_M ((uint32_t)0x00000010)
#define LPUART_CTRL_WAKE ((uint32_t)0x00000008)
#define LPUART_CTRL_ILT ((uint32_t)0x00000004)
#define LPUART_CTRL_PE ((uint32_t)0x00000002)
#define LPUART_CTRL_PT ((uint32_t)0x00000001)
#define LPUART_DATA_NOISY ((uint32_t)0x00008000)
#define LPUART_DATA_PARITYE ((uint32_t)0x00004000)
#define LPUART_DATA_FRETSC ((uint32_t)0x00002000)
#define LPUART_DATA_RXEMPT ((uint32_t)0x00001000)
#define LPUART_DATA_IDLINE ((uint32_t)0x00000800)
#define LPUART_CTRL_LOOPS ((uint32_t)(1<<7))
#define LPUART_CTRL_DOZEEN ((uint32_t)(1<<6))
#define LPUART_CTRL_RSRC ((uint32_t)(1<<5))
#define LPUART_CTRL_M ((uint32_t)(1<<4))
#define LPUART_CTRL_WAKE ((uint32_t)(1<<3))
#define LPUART_CTRL_ILT ((uint32_t)(1<<2))
#define LPUART_CTRL_PE ((uint32_t)(1<<1))
#define LPUART_CTRL_PT ((uint32_t)(1<<0))
#define LPUART_DATA_NOISY ((uint32_t)(1<<15))
#define LPUART_DATA_PARITYE ((uint32_t)(1<<14))
#define LPUART_DATA_FRETSC ((uint32_t)(1<<13))
#define LPUART_DATA_RXEMPT ((uint32_t)(1<<12))
#define LPUART_DATA_IDLINE ((uint32_t)(1<<11))
#define LPUART_MATCH_MA2(n) ((uint32_t)(((n) & 0x3FF) << 16))
#define LPUART_MATCH_MA1(n) ((uint32_t)(((n) & 0x3FF) << 0))
#define LPUART_MODIR_IREN ((uint32_t)0x00040000)
#define LPUART_MODIR_IREN ((uint32_t)(1<<18))
#define LPUART_MODIR_TNP(n) ((uint32_t)(((n) & 0x03) << 16))
#define LPUART_MODIR_RTSWATER(n) ((uint32_t)(((n) & 0x03) << 8))
#define LPUART_MODIR_TXCTSSRC ((uint32_t)0x00000020)
#define LPUART_MODIR_TXCTSC ((uint32_t)0x00000010)
#define LPUART_MODIR_RXRTSE ((uint32_t)0x00000008)
#define LPUART_MODIR_TXRTSPOL ((uint32_t)0x00000004)
#define LPUART_MODIR_TXRTSE ((uint32_t)0x00000002)
#define LPUART_MODIR_TXCTSE ((uint32_t)0x00000001)
#define LPUART_FIFO_TXEMPT ((uint32_t)0x00800000)
#define LPUART_FIFO_RXEMPT ((uint32_t)0x00400000)
#define LPUART_FIFO_TXOF ((uint32_t)0x00020000)
#define LPUART_FIFO_RXUF ((uint32_t)0x00010000)
#define LPUART_FIFO_TXFLUSH ((uint32_t)0x00008000)
#define LPUART_FIFO_RXFLUSH ((uint32_t)0x00004000)
#define LPUART_MODIR_TXCTSSRC ((uint32_t)(1<<5))
#define LPUART_MODIR_TXCTSC ((uint32_t)(1<<4))
#define LPUART_MODIR_RXRTSE ((uint32_t)(1<<3))
#define LPUART_MODIR_TXRTSPOL ((uint32_t)(1<<2))
#define LPUART_MODIR_TXRTSE ((uint32_t)(1<<1))
#define LPUART_MODIR_TXCTSE ((uint32_t)(1<<0))
#define LPUART_FIFO_TXEMPT ((uint32_t)(1<<23))
#define LPUART_FIFO_RXEMPT ((uint32_t)(1<<22))
#define LPUART_FIFO_TXOF ((uint32_t)(1<<17))
#define LPUART_FIFO_RXUF ((uint32_t)(1<<16))
#define LPUART_FIFO_TXFLUSH ((uint32_t)(1<<15))
#define LPUART_FIFO_RXFLUSH ((uint32_t)(1<<14))
#define LPUART_FIFO_RXIDEN(n) ((uint32_t)(((n) & 0x07) << 10))
#define LPUART_FIFO_TXOFE ((uint32_t)0x00000200)
#define LPUART_FIFO_RXUFE ((uint32_t)0x00000100)
#define LPUART_FIFO_TXFE ((uint32_t)0x00000080)
#define LPUART_FIFO_TXOFE ((uint32_t)(1<<9))
#define LPUART_FIFO_RXUFE ((uint32_t)(1<<8))
#define LPUART_FIFO_TXFE ((uint32_t)(1<<7))
#define LPUART_FIFO_TXFIFOSIZE(n) ((uint32_t)(((n) & 0x07) << 4))
#define LPUART_FIFO_RXFE ((uint32_t)0x00000008)
#define LPUART_FIFO_RXFE ((uint32_t)(1<<3))
#define LPUART_FIFO_RXFIFOSIZE(n) ((uint32_t)(((n) & 0x07) << 0))
#define LPUART_WATER_RXCOUNT(n) ((uint32_t)(((n) & 0x07) << 24))
#define LPUART_WATER_RXWATER(n) ((uint32_t)(((n) & 0x03) << 16))
@@ -5769,14 +5769,14 @@ typedef struct {
// System Control Space (SCS), ARMv7 ref manual, B3.2, page 708
#define SCB_CPUID (*(const uint32_t *)0xE000ED00) // CPUID Base Register
#define SCB_ICSR (*(volatile uint32_t *)0xE000ED04) // Interrupt Control and State
#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000)
#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000)
#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000)
#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000)
#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000)
#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000)
#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000)
#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800)
#define SCB_ICSR_NMIPENDSET ((uint32_t)(1<<31))
#define SCB_ICSR_PENDSVSET ((uint32_t)(1<<28))
#define SCB_ICSR_PENDSVCLR ((uint32_t)(1<<27))
#define SCB_ICSR_PENDSTSET ((uint32_t)(1<<26))
#define SCB_ICSR_PENDSTCLR ((uint32_t)(1<<25))
#define SCB_ICSR_ISRPREEMPT ((uint32_t)(1<<23))
#define SCB_ICSR_ISRPENDING ((uint32_t)(1<<22))
#define SCB_ICSR_RETTOBASE ((uint32_t)(1<<11))
#define SCB_VTOR (*(volatile uint32_t *)0xE000ED08) // Vector Table Offset
#define SCB_AIRCR (*(volatile uint32_t *)0xE000ED0C) // Application Interrupt and Reset Control
#define SCB_SCR (*(volatile uint32_t *)0xE000ED10) // System Control Register
@@ -5803,10 +5803,10 @@ typedef struct {
#define SCB_MVFR2 (*(volatile uint32_t *)0xE000EF48) // Media & FP Feature 2

#define SYST_CSR (*(volatile uint32_t *)0xE000E010) // SysTick Control and Status
#define SYST_CSR_COUNTFLAG ((uint32_t)0x00010000)
#define SYST_CSR_CLKSOURCE ((uint32_t)0x00000004)
#define SYST_CSR_TICKINT ((uint32_t)0x00000002)
#define SYST_CSR_ENABLE ((uint32_t)0x00000001)
#define SYST_CSR_COUNTFLAG ((uint32_t)(1<<16))
#define SYST_CSR_CLKSOURCE ((uint32_t)(1<<2))
#define SYST_CSR_TICKINT ((uint32_t)(1<<1))
#define SYST_CSR_ENABLE ((uint32_t)(1<<0))
#define SYST_RVR (*(volatile uint32_t *)0xE000E014) // SysTick Reload Value Register
#define SYST_CVR (*(volatile uint32_t *)0xE000E018) // SysTick Current Value Register
#define SYST_CALIB (*(const uint32_t *)0xE000E01C) // SysTick Calibration Value

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