More IMXRT register defs

teensy4/imxrt.h

@@ -2423,7 +2423,7 @@ typedef struct {
 #define FLEXPWM4_FTST0			(IMXRT_FLEXPWM4.offset192)
 #define FLEXPWM4_FCTRL20		(IMXRT_FLEXPWM4.offset194)
 
-// page 1496
+// page 1470
 #define IMXRT_FLEXRAM		(*(IMXRT_REGISTER32_t *)0x400B0000)
 #define FLEXRAM_TCM_CTRL		(IMXRT_FLEXRAM.offset000)
 #define FLEXRAM_OCRAM_MAGIC_ADDR	(IMXRT_FLEXRAM.offset004)
@@ -2432,6 +2432,18 @@ typedef struct {
 #define FLEXRAM_INT_STATUS		(IMXRT_FLEXRAM.offset010)
 #define FLEXRAM_INT_STAT_EN		(IMXRT_FLEXRAM.offset014)
 #define FLEXRAM_INT_SIG_EN		(IMXRT_FLEXRAM.offset018)
+#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON			((uint32_t)0x00000004)
+#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN			((uint32_t)0x00000002)
+#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN			((uint32_t)0x00000001)
+#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS		((uint32_t)0x00000020)
+#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS		((uint32_t)0x00000010)
+#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS		((uint32_t)0x00000008)
+#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN		((uint32_t)0x00000020)
+#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN		((uint32_t)0x00000010)
+#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN		((uint32_t)0x00000008)
+#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN		((uint32_t)0x00000020)
+#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN		((uint32_t)0x00000010)
+#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN		((uint32_t)0x00000008)
 
 // page 1583
 #define IMXRT_FLEXSPI		(*(IMXRT_REGISTER32_t *)0x400B0000)
@@ -2602,10 +2614,9 @@ typedef struct {
 #define FLEXSPI_LUT62			(IMXRT_FLEXSPI.offset2F8)
 #define FLEXSPI_LUT63			(IMXRT_FLEXSPI.offset2FC)
 
-// page 1629
+// page 1595
 #define IMXRT_GPC		(*(IMXRT_REGISTER32_t *)0x400F4000)
 #define GPC_CNTR			(IMXRT_GPC.offset000)
-#define GPC_PGR				(IMXRT_GPC.offset004)
 #define GPC_IMR1			(IMXRT_GPC.offset008)
 #define GPC_IMR2			(IMXRT_GPC.offset00C)
 #define GPC_IMR3			(IMXRT_GPC.offset010)
@@ -2614,6 +2625,33 @@ typedef struct {
 #define GPC_ISR2			(IMXRT_GPC.offset01C)
 #define GPC_ISR3			(IMXRT_GPC.offset020)
 #define GPC_ISR4			(IMXRT_GPC.offset024)
+#define GPC_IMR5			(IMXRT_GPC.offset034)
+#define GPC_ISR5			(IMXRT_GPC.offset038)
+#define GPC_CNTR_PDRAM0_PGE				((uint32_t)0x00400000)
+#define GPC_CNTR_MEGA_PUP_REQ				((uint32_t)0x00000008)
+#define GPC_CNTR_MEGA_PDN_REQ				((uint32_t)0x00000004)
+// page 1602
+#define PGC_MEGA_CTRL			(IMXRT_GPC.offset220)
+#define PGC_MEGA_PUPSCR			(IMXRT_GPC.offset224)
+#define PGC_MEGA_PDNSCR			(IMXRT_GPC.offset228)
+#define PGC_MEGA_SR			(IMXRT_GPC.offset22C)
+#define PGC_CPU_CTRL			(IMXRT_GPC.offset2A0)
+#define PGC_CPU_PUPSCR			(IMXRT_GPC.offset2A4)
+#define PGC_CPU_PDNSCR			(IMXRT_GPC.offset2A8)
+#define PGC_CPU_SR			(IMXRT_GPC.offset2AC)
+#define PGC_MEGA_CTRL_PCR				((uint32_t)0x00000001)
+#define PGC_MEGA_PUPSCR_SW2ISO(n)			((uint32_t)(((n) & 0x3F) << 8))
+#define PGC_MEGA_PUPSCR_SW(n)				((uint32_t)(((n) & 0x3F) << 0))
+#define PGC_MEGA_PDNSCR_ISO2SW(n)			((uint32_t)(((n) & 0x3F) << 8))
+#define PGC_MEGA_PDNSCR_ISO(n)				((uint32_t)(((n) & 0x3F) << 0))
+#define PGC_MEGA_SR_PSR					((uint32_t)0x00000001)
+#define PGC_CPU_CTRL_PCR				((uint32_t)0x00000001)
+#define PGC_CPU_PUPSCR_SW2ISO(n)			((uint32_t)(((n) & 0x3F) << 8))
+#define PGC_CPU_PUPSCR_SW(n)				((uint32_t)(((n) & 0x3F) << 0))
+#define PGC_CPU_PDNSCR_ISO2SW(n)			((uint32_t)(((n) & 0x3F) << 8))
+#define PGC_CPU_PDNSCR_ISO(n)				((uint32_t)(((n) & 0x3F) << 0))
+#define PGC_CPU_SR_PSR					((uint32_t)0x00000001)
+
 
 // page 1658
 #define IMXRT_GPIO1		(*(IMXRT_REGISTER32_t *)0x401B8000)
@@ -3651,7 +3689,7 @@ typedef struct {
 #define LPSPI4_RSR			(IMXRT_LPSPI4.offset070)
 #define LPSPI4_RDR			(IMXRT_LPSPI4.offset074)
 
-// page 2520
+// page 2486
 #define IMXRT_LPUART1		(*(IMXRT_REGISTER32_t *)0x40184000)
 #define LPUART1_VERID			(IMXRT_LPUART1.offset000)
 #define LPUART1_PARAM			(IMXRT_LPUART1.offset004)
@@ -3756,6 +3794,106 @@ typedef struct {
 #define LPUART8_MODIR			(IMXRT_LPUART8.offset024)
 #define LPUART8_FIFO			(IMXRT_LPUART8.offset028)
 #define LPUART8_WATER			(IMXRT_LPUART8.offset02C)
+#define LPUART_VERID_MAJOR(n)				((uint32_t)(((n) & 0xFF) << 24))
+#define LPUART_VERID_MINOR(n)				((uint32_t)(((n) & 0xFF) << 16))
+#define LPUART_VERID_FEATURE(n)				((uint32_t)(((n) & 0xFFFF) << 0))
+#define LPUART_PARAM_RXFIFO(n)				((uint32_t)(((n) & 0xFF) << 8))
+#define LPUART_PARAM_TXFIFO(n)				((uint32_t)(((n) & 0xFF) << 0))
+#define LPUART_GLOBAL_RST				((uint32_t)0x00000002)
+#define LPUART_PINCFG_TRGSEL(n)				((uint32_t)(((n) & 0x03) << 0))
+#define LPUART_BAUD_MAEN1				((uint32_t)0x80000000)
+#define LPUART_BAUD_MAEN2				((uint32_t)0x40000000)
+#define LPUART_BAUD_M10					((uint32_t)0x20000000)
+#define LPUART_BAUD_OSR(n)				((uint32_t)(((n) & 0x1F) << 24))
+#define LPUART_BAUD_TDMAE				((uint32_t)0x00800000)
+#define LPUART_BAUD_RDMAE				((uint32_t)0x00200000)
+#define LPUART_BAUD_MATCFG(n)				((uint32_t)(((n) & 0x03) << 18))
+#define LPUART_BAUD_BOTHEDGE				((uint32_t)0x00020000)
+#define LPUART_BAUD_RESYNCDIS				((uint32_t)0x00010000)
+#define LPUART_BAUD_LBKDIE				((uint32_t)0x00008000)
+#define LPUART_BAUD_RXEDGIE				((uint32_t)0x00004000)
+#define LPUART_BAUD_SBNS				((uint32_t)0x00002000)
+#define LPUART_BAUD_SBR(n)				((uint32_t)(((n) & 0x01FFF) << 0))
+#define LPUART_STAT_LBKDIF				((uint32_t)0x80000000)
+#define LPUART_STAT_RXEDGIF				((uint32_t)0x40000000)
+#define LPUART_STAT_MSBF				((uint32_t)0x20000000)
+#define LPUART_STAT_RXINV				((uint32_t)0x10000000)
+#define LPUART_STAT_RWUID				((uint32_t)0x08000000)
+#define LPUART_STAT_BRK13				((uint32_t)0x04000000)
+#define LPUART_STAT_LBKDE				((uint32_t)0x02000000)
+#define LPUART_STAT_RAF					((uint32_t)0x01000000)
+#define LPUART_STAT_TDRE				((uint32_t)0x00800000)
+#define LPUART_STAT_TC					((uint32_t)0x00400000)
+#define LPUART_STAT_RDRF				((uint32_t)0x00200000)
+#define LPUART_STAT_IDLE				((uint32_t)0x00100000)
+#define LPUART_STAT_OR					((uint32_t)0x00080000)
+#define LPUART_STAT_NF					((uint32_t)0x00040000)
+#define LPUART_STAT_FE					((uint32_t)0x00020000)
+#define LPUART_STAT_PF					((uint32_t)0x00010000)
+#define LPUART_STAT_MA1F				((uint32_t)0x00008000)
+#define LPUART_STAT_MA2F				((uint32_t)0x00004000)
+#define LPUART_CTRL_R8T9				((uint32_t)0x80000000)
+#define LPUART_CTRL_R9T8				((uint32_t)0x40000000)
+#define LPUART_CTRL_TXDIR				((uint32_t)0x20000000)
+#define LPUART_CTRL_TXINV				((uint32_t)0x10000000)
+#define LPUART_CTRL_ORIE				((uint32_t)0x08000000)
+#define LPUART_CTRL_NEIE				((uint32_t)0x04000000)
+#define LPUART_CTRL_NEIE				((uint32_t)0x02000000)
+#define LPUART_CTRL_PEIE				((uint32_t)0x01000000)
+#define LPUART_CTRL_TIE					((uint32_t)0x00800000)
+#define LPUART_CTRL_TCIE				((uint32_t)0x00400000)
+#define LPUART_CTRL_RIE					((uint32_t)0x00200000)
+#define LPUART_CTRL_ILIE				((uint32_t)0x00100000)
+#define LPUART_CTRL_TE					((uint32_t)0x00080000)
+#define LPUART_CTRL_RE					((uint32_t)0x00040000)
+#define LPUART_CTRL_RWU					((uint32_t)0x00020000)
+#define LPUART_CTRL_SBK					((uint32_t)0x00010000)
+#define LPUART_CTRL_MA1IE				((uint32_t)0x00008000)
+#define LPUART_CTRL_MA2IE				((uint32_t)0x00004000)
+#define LPUART_CTRL_M7					((uint32_t)0x00000800)
+#define LPUART_CTRL_IDLECFG(n)				((uint32_t)(((n) & 0x07) << 8))
+#define LPUART_CTRL_LOOPS				((uint32_t)0x00000080)
+#define LPUART_CTRL_DOZEEN				((uint32_t)0x00000040)
+#define LPUART_CTRL_RSRC				((uint32_t)0x00000020)
+#define LPUART_CTRL_M					((uint32_t)0x00000010)
+#define LPUART_CTRL_WAKE				((uint32_t)0x00000008)
+#define LPUART_CTRL_ILT					((uint32_t)0x00000004)
+#define LPUART_CTRL_PE					((uint32_t)0x00000002)
+#define LPUART_CTRL_PT					((uint32_t)0x00000001)
+#define LPUART_DATA_NOISY				((uint32_t)0x00008000)
+#define LPUART_DATA_PARITYE				((uint32_t)0x00004000)
+#define LPUART_DATA_FRETSC				((uint32_t)0x00002000)
+#define LPUART_DATA_RXEMPT				((uint32_t)0x00001000)
+#define LPUART_DATA_IDLINE				((uint32_t)0x00000800)
+#define LPUART_MATCH_MA2(n)				((uint32_t)(((n) & 0x3FF) << 16))
+#define LPUART_MATCH_MA1(n)				((uint32_t)(((n) & 0x3FF) << 0))
+#define LPUART_MODIR_IREN				((uint32_t)0x00040000)
+#define LPUART_MODIR_TNP(n)				((uint32_t)(((n) & 0x03) << 16))
+#define LPUART_MODIR_RTSWATER(n)			((uint32_t)(((n) & 0x03) << 8))
+#define LPUART_MODIR_TXCTSSRC				((uint32_t)0x00000020)
+#define LPUART_MODIR_TXCTSSRC				((uint32_t)0x00000010)
+#define LPUART_MODIR_RXRTSE				((uint32_t)0x00000008)
+#define LPUART_MODIR_TXRTSPOL				((uint32_t)0x00000004)
+#define LPUART_MODIR_TXRTSE				((uint32_t)0x00000002)
+#define LPUART_MODIR_TXCTSE				((uint32_t)0x00000001)
+#define LPUART_FIFO_TXEMPT				((uint32_t)0x00800000)
+#define LPUART_FIFO_RXEMPT				((uint32_t)0x00400000)
+#define LPUART_FIFO_TXOF				((uint32_t)0x00020000)
+#define LPUART_FIFO_RXUF				((uint32_t)0x00010000)
+#define LPUART_FIFO_TXFLUSH				((uint32_t)0x00008000)
+#define LPUART_FIFO_RXFLUSH				((uint32_t)0x00004000)
+#define LPUART_FIFO_RXIDEN(n)				((uint32_t)(((n) & 0x07) << 10))
+#define LPUART_FIFO_TXOFE				((uint32_t)0x00000200)
+#define LPUART_FIFO_RXUFE				((uint32_t)0x00000100)
+#define LPUART_FIFO_TXFE				((uint32_t)0x00000080)
+#define LPUART_FIFO_TXFIFOSIZE(n)			((uint32_t)(((n) & 0x07) << 4))
+#define LPUART_FIFO_RXFE				((uint32_t)0x00000008)
+#define LPUART_FIFO_RXFIFOSIZE(n)			((uint32_t)(((n) & 0x07) << 0))
+#define LPUART_WATER_RXCOUNT(n)				((uint32_t)(((n) & 0x07) << 24))
+#define LPUART_WATER_RXWATER(n)				((uint32_t)(((n) & 0x03) << 16))
+#define LPUART_WATER_TXCOUNT(n)				((uint32_t)(((n) & 0x07) << 8))
+#define LPUART_WATER_TXWATER(n)				((uint32_t)(((n) & 0x03) << 0))
+
 
 // page 2558
 #define IMXRT_OCOTP		(*(IMXRT_REGISTER32_t *)0x401F4000)