#define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz | #define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz | ||||
#define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz | #define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz | ||||
#define ADC_CFG1_8BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz | #define ADC_CFG1_8BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz | ||||
#elif F_BUS == 56000000 | |||||
#elif F_BUS == 56000000 || F_BUS == 54000000 | |||||
#define ADC_CFG1_16BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 7 MHz | #define ADC_CFG1_16BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 7 MHz | ||||
#define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 14 MHz | #define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 14 MHz | ||||
#define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 14 MHz | #define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 14 MHz | ||||
#define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz | #define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz | ||||
#define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz | #define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz | ||||
#else | #else | ||||
#error "F_BUS must be 60, 56, 48, 40, 36, 24, 4 or 2 MHz" | |||||
#error "F_BUS must be 60, 56, 54, 48, 40, 36, 24, 4 or 2 MHz" | |||||
#endif | #endif | ||||
void analog_init(void) | void analog_init(void) |
static inline void delayMicroseconds(uint32_t) __attribute__((always_inline, unused)); | static inline void delayMicroseconds(uint32_t) __attribute__((always_inline, unused)); | ||||
static inline void delayMicroseconds(uint32_t usec) | static inline void delayMicroseconds(uint32_t usec) | ||||
{ | { | ||||
#if F_CPU == 192000000 | |||||
#if F_CPU == 240000000 | |||||
uint32_t n = usec * 80; | |||||
#elif F_CPU == 216000000 | |||||
uint32_t n = usec * 72; | |||||
#elif F_CPU == 192000000 | |||||
uint32_t n = usec * 64; | uint32_t n = usec * 64; | ||||
#elif F_CPU == 180000000 | #elif F_CPU == 180000000 | ||||
uint32_t n = usec * 60; | uint32_t n = usec * 60; |
#endif // end of board-specific definitions | #endif // end of board-specific definitions | ||||
#if (F_CPU == 192000000) | |||||
#if (F_CPU == 240000000) | |||||
#define F_PLL 240000000 | |||||
#define F_BUS 60000000 | |||||
#define F_MEM 30000000 | |||||
#elif (F_CPU == 216000000) | |||||
#define F_PLL 216000000 | |||||
#define F_BUS 54000000 | |||||
#define F_MEM 27000000 | |||||
#elif (F_CPU == 192000000) | |||||
#define F_PLL 192000000 | #define F_PLL 192000000 | ||||
#define F_BUS 48000000 | #define F_BUS 48000000 | ||||
#define F_MEM 27428571 | #define F_MEM 27428571 |
SMC_PMCTRL = SMC_PMCTRL_RUNM(3); // enter HSRUN mode | SMC_PMCTRL = SMC_PMCTRL_RUNM(3); // enter HSRUN mode | ||||
while (SMC_PMSTAT != SMC_PMSTAT_HSRUN) ; // wait for HSRUN | while (SMC_PMSTAT != SMC_PMSTAT_HSRUN) ; // wait for HSRUN | ||||
#endif | #endif | ||||
#if F_CPU == 192000000 | |||||
#if F_CPU == 240000000 | |||||
MCG_C5 = MCG_C5_PRDIV0(0); | |||||
MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(14); | |||||
#elif F_CPU == 216000000 | |||||
MCG_C5 = MCG_C5_PRDIV0(0); | |||||
MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(11); | |||||
#elif F_CPU == 192000000 | |||||
MCG_C5 = MCG_C5_PRDIV0(0); | MCG_C5 = MCG_C5_PRDIV0(0); | ||||
MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(8); | MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(8); | ||||
#elif F_CPU == 180000000 | #elif F_CPU == 180000000 | ||||
#endif | #endif | ||||
#endif | #endif | ||||
// now program the clock dividers | // now program the clock dividers | ||||
#if F_CPU == 192000000 | |||||
// config divisors: 192 MHz core, 48 MHz bus, 27.4 MHz flash, USB = 192 * 4 | |||||
#if F_CPU == 240000000 | |||||
// config divisors: 240 MHz core, 60 MHz bus, 30 MHz flash, USB = 240 / 5 | |||||
// TODO: gradual ramp-up for HSRUN mode | |||||
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(3) | SIM_CLKDIV1_OUTDIV4(7); | |||||
SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(4); | |||||
#elif F_CPU == 216000000 | |||||
// config divisors: 216 MHz core, 54 MHz bus, 27 MHz flash, USB = not feasible | |||||
// TODO: gradual ramp-up for HSRUN mode | |||||
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(3) | SIM_CLKDIV1_OUTDIV4(7); | |||||
SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(8) | SIM_CLKDIV2_USBFRAC; | |||||
#elif F_CPU == 192000000 | |||||
// config divisors: 192 MHz core, 48 MHz bus, 27.4 MHz flash, USB = 192 / 4 | |||||
// TODO: gradual ramp-up for HSRUN mode | // TODO: gradual ramp-up for HSRUN mode | ||||
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(3) | SIM_CLKDIV1_OUTDIV4(6); | SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(3) | SIM_CLKDIV1_OUTDIV4(6); | ||||
SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(3); | SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(3); |
#elif F_TIMER == 56000000 | #elif F_TIMER == 56000000 | ||||
#define DEFAULT_FTM_MOD (57344 - 1) | #define DEFAULT_FTM_MOD (57344 - 1) | ||||
#define DEFAULT_FTM_PRESCALE 1 | #define DEFAULT_FTM_PRESCALE 1 | ||||
#elif F_TIMER == 54000000 | |||||
#define DEFAULT_FTM_MOD (55296 - 1) | |||||
#define DEFAULT_FTM_PRESCALE 1 | |||||
#elif F_TIMER == 48000000 | #elif F_TIMER == 48000000 | ||||
#define DEFAULT_FTM_MOD (49152 - 1) | #define DEFAULT_FTM_MOD (49152 - 1) | ||||
#define DEFAULT_FTM_PRESCALE 1 | #define DEFAULT_FTM_PRESCALE 1 | ||||
} | } | ||||
// TODO: verify these result in correct timeouts... | // TODO: verify these result in correct timeouts... | ||||
#if F_CPU == 192000000 | |||||
#if F_CPU == 240000000 | |||||
#define PULSEIN_LOOPS_PER_USEC 33 | |||||
#elif F_CPU == 216000000 | |||||
#define PULSEIN_LOOPS_PER_USEC 31 | |||||
#elif F_CPU == 192000000 | |||||
#define PULSEIN_LOOPS_PER_USEC 29 | #define PULSEIN_LOOPS_PER_USEC 29 | ||||
#elif F_CPU == 180000000 | #elif F_CPU == 180000000 | ||||
#define PULSEIN_LOOPS_PER_USEC 27 | #define PULSEIN_LOOPS_PER_USEC 27 |
// When the PC isn't listening, how long do we wait before discarding data? | // When the PC isn't listening, how long do we wait before discarding data? | ||||
#define TX_TIMEOUT_MSEC 30 | #define TX_TIMEOUT_MSEC 30 | ||||
#if F_CPU == 192000000 | |||||
#if F_CPU == 240000000 | |||||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1600) | |||||
#elif F_CPU == 216000000 | |||||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1440) | |||||
#elif F_CPU == 192000000 | |||||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1280) | #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1280) | ||||
#elif F_CPU == 180000000 | #elif F_CPU == 180000000 | ||||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1200) | #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1200) |
// When the PC isn't listening, how long do we wait before discarding data? | // When the PC isn't listening, how long do we wait before discarding data? | ||||
#define TX_TIMEOUT_MSEC 50 | #define TX_TIMEOUT_MSEC 50 | ||||
#if F_CPU == 192000000 | |||||
#if F_CPU == 240000000 | |||||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1600) | |||||
#elif F_CPU == 216000000 | |||||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1440) | |||||
#elif F_CPU == 192000000 | |||||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1280) | #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1280) | ||||
#elif F_CPU == 180000000 | #elif F_CPU == 180000000 | ||||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1200) | #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1200) |
// When the PC isn't listening, how long do we wait before discarding data? | // When the PC isn't listening, how long do we wait before discarding data? | ||||
#define TX_TIMEOUT_MSEC 40 | #define TX_TIMEOUT_MSEC 40 | ||||
#if F_CPU == 192000000 | |||||
#if F_CPU == 240000000 | |||||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1600) | |||||
#elif F_CPU == 216000000 | |||||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1440) | |||||
#elif F_CPU == 192000000 | |||||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1280) | #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1280) | ||||
#elif F_CPU == 180000000 | #elif F_CPU == 180000000 | ||||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1200) | #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1200) |
// When the PC isn't listening, how long do we wait before discarding data? | // When the PC isn't listening, how long do we wait before discarding data? | ||||
#define TX_TIMEOUT_MSEC 30 | #define TX_TIMEOUT_MSEC 30 | ||||
#if F_CPU == 192000000 | |||||
#if F_CPU == 240000000 | |||||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1600) | |||||
#elif F_CPU == 216000000 | |||||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1440) | |||||
#elif F_CPU == 192000000 | |||||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1280) | #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1280) | ||||
#elif F_CPU == 180000000 | #elif F_CPU == 180000000 | ||||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1200) | #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1200) |
// software. If it's too long, we stall the user's program when no software is running. | // software. If it's too long, we stall the user's program when no software is running. | ||||
#define TX_TIMEOUT_MSEC 30 | #define TX_TIMEOUT_MSEC 30 | ||||
#if F_CPU == 192000000 | |||||
#if F_CPU == 240000000 | |||||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1600) | |||||
#elif F_CPU == 216000000 | |||||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1440) | |||||
#elif F_CPU == 192000000 | |||||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1280) | #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1280) | ||||
#elif F_CPU == 180000000 | #elif F_CPU == 180000000 | ||||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1200) | #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1200) |
// software. If it's too long, we stall the user's program when no software is running. | // software. If it's too long, we stall the user's program when no software is running. | ||||
#define TX_TIMEOUT_MSEC 70 | #define TX_TIMEOUT_MSEC 70 | ||||
#if F_CPU == 192000000 | |||||
#if F_CPU == 240000000 | |||||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1600) | |||||
#elif F_CPU == 216000000 | |||||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1440) | |||||
#elif F_CPU == 192000000 | |||||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1280) | #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1280) | ||||
#elif F_CPU == 180000000 | #elif F_CPU == 180000000 | ||||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1200) | #define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1200) |