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Merge pull request #23 from duff2013/master

more 2 MHz (VLPR) fixes
teensy4-core
Paul Stoffregen 10 years ago
parent
commit
60f60ff37d
2 changed files with 8 additions and 4 deletions
  1. +2
    -1
      teensy3/core_pins.h
  2. +6
    -3
      teensy3/mk20dx128.c

+ 2
- 1
teensy3/core_pins.h View File

#elif F_CPU == 2000000 #elif F_CPU == 2000000
uint32_t n = usec >> 1; uint32_t n = usec >> 1;
#endif #endif
if (usec == 0) return;
// changed because a delay of 1 micro Sec @ 2MHz will be 0
if (n == 0) return;
__asm__ volatile( __asm__ volatile(
"L_%=_delayMicroseconds:" "\n\t" "L_%=_delayMicroseconds:" "\n\t"
#if F_CPU < 24000000 #if F_CPU < 24000000

+ 6
- 3
teensy3/mk20dx128.c View File

// release I/O pins hold, if we woke up from VLLS mode // release I/O pins hold, if we woke up from VLLS mode
if (PMC_REGSC & PMC_REGSC_ACKISO) PMC_REGSC |= PMC_REGSC_ACKISO; if (PMC_REGSC & PMC_REGSC_ACKISO) PMC_REGSC |= PMC_REGSC_ACKISO;


// since this is a write once register, make it visible to all F_CPU's
// so we can into other sleep modes in the future at any speed
SMC_PMPROT = SMC_PMPROT_AVLP | SMC_PMPROT_ALLS | SMC_PMPROT_AVLLS;
// TODO: do this while the PLL is waiting to lock.... // TODO: do this while the PLL is waiting to lock....
while (dest < &_edata) *dest++ = *src++; while (dest < &_edata) *dest++ = *src++;
dest = &_sbss; dest = &_sbss;
#endif #endif


#if F_CPU <= 2000000 #if F_CPU <= 2000000
// switch to VLPR mode....
SMC_PMPROT = SMC_PMPROT_AVLP | SMC_PMPROT_ALLS | SMC_PMPROT_AVLLS;
SMC_PMCTRL = SMC_PMCTRL_RUNM(2) | SMC_PMCTRL_STOPM(2); // VLPR mode :-)
// since we are not going into "stop mode" i removed it
SMC_PMCTRL = SMC_PMCTRL_RUNM(2); // VLPR mode :-)
#endif #endif


// initialize the SysTick counter // initialize the SysTick counter

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