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Merge pull request #2 from PaulStoffregen/master

resync
teensy4-core
duff2013 il y a 10 ans
Parent
révision
65b4d38779
3 fichiers modifiés avec 12 ajouts et 4 suppressions
  1. +2
    -2
      teensy3/mk20dx128.c
  2. +1
    -1
      teensy3/mk20dx128.h
  3. +9
    -1
      teensy3/usb_midi.c

+ 2
- 2
teensy3/mk20dx128.c Voir le fichier

@@ -438,8 +438,8 @@ void ResetHandler(void)
// now we're in PBE mode

#if F_CPU == 168000000
// config divisors: 168 MHz core, 56 MHz bus, 28 MHz flash
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2) | SIM_CLKDIV1_OUTDIV4(5);
// config divisors: 168 MHz core, 56 MHz bus, 33.6 MHz flash
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2) | SIM_CLKDIV1_OUTDIV4(4);
#elif F_CPU == 144000000
// config divisors: 144 MHz core, 48 MHz bus, 28.8 MHz flash
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2) | SIM_CLKDIV1_OUTDIV4(4);

+ 1
- 1
teensy3/mk20dx128.h Voir le fichier

@@ -44,7 +44,7 @@

#if (F_CPU == 168000000)
#define F_BUS 56000000
#define F_MEM 28000000
#define F_MEM 33600000
#elif (F_CPU == 144000000)
#define F_BUS 48000000
#define F_MEM 28800000

+ 9
- 1
teensy3/usb_midi.c Voir le fichier

@@ -62,8 +62,16 @@ static uint8_t tx_noautoflush=0;
// When the PC isn't listening, how long do we wait before discarding data?
#define TX_TIMEOUT_MSEC 40

#if F_CPU == 96000000
#if F_CPU == 168000000
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1100)
#elif F_CPU == 144000000
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 932)
#elif F_CPU == 120000000
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 764)
#elif F_CPU == 96000000
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 596)
#elif F_CPU == 72000000
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 512)
#elif F_CPU == 48000000
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 428)
#elif F_CPU == 24000000

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