Add support for 2, 4, 8, 16MHz (Duff)

teensy3/SPIFIFO.h

@@ -57,6 +57,24 @@
 #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0))                //(24 / 2) * ((1+0)/2)
 #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(2) | SPI_CTAR_DBR) //(24 / 2) * ((1+1)/6)
 
+#elif F_BUS == 16000000
+#define HAS_SPIFIFO
+#define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | SPI_CTAR_DBR) //(16 / 2) * ((1+1)/8) = 2 MHz
+#define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | SPI_CTAR_DBR) //(16 / 2) * ((1+1)/8) = 2 MHz
+#define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | SPI_CTAR_DBR) //(16 / 2) * ((1+1)/8) = 2 MHz
+#define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | SPI_CTAR_DBR) //(16 / 2) * ((1+1)/8) = 2 MHz
+#define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | SPI_CTAR_DBR) //(16 / 2) * ((1+1)/8) = 2 MHz
+#define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | SPI_CTAR_DBR) //(16 / 2) * ((1+1)/8) = 2 MHz
+
+#elif F_BUS == 8000000
+#define HAS_SPIFIFO
+#define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(8 / 2) * ((1+1)/4) = 2 MHz
+#define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(8 / 2) * ((1+1)/4) = 2 MHz
+#define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(8 / 2) * ((1+1)/4) = 2 MHz
+#define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(8 / 2) * ((1+1)/4) = 2 MHz
+#define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(8 / 2) * ((1+1)/4) = 2 MHz
+#define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(8 / 2) * ((1+1)/4) = 2 MHz
+
 #elif F_BUS == 4000000
 #define HAS_SPIFIFO
 #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 2 MHz

teensy3/analog.c

@@ -71,6 +71,16 @@ static uint8_t analog_reference_internal = 0;
   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(0) // 12 MHz
   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(0) // 12 MHz
   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 24 MHz
+#elif F_BUS == 16000000
+  #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
+  #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
+  #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
+  #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 16 MHz
+#elif F_BUS == 8000000
+  #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
+  #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
+  #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
+  #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
 #elif F_BUS == 4000000
   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz
   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz

teensy3/core_pins.h

@@ -784,6 +784,10 @@ static inline void delayMicroseconds(uint32_t usec)
 	uint32_t n = usec << 4;
 #elif F_CPU == 24000000
 	uint32_t n = usec << 3;
+#elif F_CPU == 16000000
+	uint32_t n = usec << 2;
+#elif F_CPU == 8000000
+	uint32_t n = usec << 1;
 #elif F_CPU == 4000000
 	uint32_t n = usec;
 #elif F_CPU == 2000000
@@ -792,7 +796,7 @@ static inline void delayMicroseconds(uint32_t usec)
 	if (usec == 0) return;
 	__asm__ volatile(
 		"L_%=_delayMicroseconds:"		"\n\t"
-#if F_CPU < 10000000
+#if F_CPU < 24000000
 		"nop"					"\n\t"
 #endif
 		"subs   %0, #1"				"\n\t"

teensy3/mk20dx128.c

@@ -458,15 +458,66 @@ void ResetHandler(void)
 #elif F_CPU == 24000000
 	// config divisors: 24 MHz core, 24 MHz bus, 24 MHz flash
 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(3) |	 SIM_CLKDIV1_OUTDIV4(3);
+#elif F_CPU == 16000000
+	// config divisors: 16 MHz core (FLL), 16 MHz bus, 16 MHz flash
+	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |	 SIM_CLKDIV1_OUTDIV4(0);
+#elif F_CPU == 8000000
+	// config divisors: 8 MHz core (FLL), 8 MHz bus, 8 MHz flash
+	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) |	 SIM_CLKDIV1_OUTDIV4(1);
+#elif F_CPU == 4000000
+	// config divisors: 4 MHz core (FLL), 4 MHz bus, 4 MHz flash
+	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(3) |	 SIM_CLKDIV1_OUTDIV4(15);
+#elif F_CPU == 2000000
+	// config divisors: 2 MHz core (FLL), 2 MHz bus, 2 MHz flash
+	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |	 SIM_CLKDIV1_OUTDIV4(1);
 #else
-#error "Error, F_CPU must be 168, 144, 120, 96, 72, 48, or 24 MHz"
+#error "Error, F_CPU must be 168, 144, 120, 96, 72, 48, 24, 16, 8, 4, or 2 MHz"
 #endif
+
+#if F_CPU == 2000000
+	// select external reference clock as MCG_OUT
+	MCG_C1 |= MCG_C1_CLKS(2);
+	// wait for FLL clock to be used
+	while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2)) ;
+	// now move to FBE mode
+	// make sure the FRDIV is configured to keep the FLL reference within spec.
+	MCG_C1 &= ~0x38; // clear FRDIV field
+	MCG_C1 |= MCG_C1_FRDIV(4); // set FLL ref divider to 512
+	MCG_C6 &= ~MCG_C6_PLLS; // clear PLLS to select the FLL
+	while (MCG_S & MCG_S_PLLST){} // Wait for PLLST status bit to clear to
+	// indicate switch to FLL output
+	// now move to FBI mode
+	MCG_C2 |= MCG_C2_IRCS; // set the IRCS bit to select the fast IRC
+	// set CLKS to 1 to select the internal reference clock
+	// keep FRDIV at existing value to keep FLL ref clock in spec.
+	// set IREFS to 1 to select internal reference clock
+	MCG_C1 = MCG_C1_CLKS(1) | MCG_C1_FRDIV(4) | MCG_C1_IREFS;
+	// wait for internal reference to be selected
+	while (!(MCG_S & MCG_S_IREFST)){}
+	// wait for fast internal reference to be selected
+	while (!(MCG_S & MCG_S_IRCST)){}
+	// wait for clock to switch to IRC
+	while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(1)) ;
+	// now move to BLPI
+	MCG_C2 |= MCG_C2_LP;
+	// now we're in BLPI mode
+#elif F_CPU == 16000000 || F_CPU == 8000000 || F_CPU == 4000000
+	// select external reference clock as MCG_OUT
+	MCG_C1 = MCG_C1_CLKS(2);
+	// wait for external clock to be used
+	while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2)) ;
+	// set the LP bit to enter BLPE
+	MCG_C2 |= MCG_C2_LP;
+	// now we're in BLPE mode
+#else
 	// switch to PLL as clock source, FLL input = 16 MHz / 512
 	MCG_C1 = MCG_C1_CLKS(0) | MCG_C1_FRDIV(4);
 	// wait for PLL clock to be used
 	while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(3)) ;
 	// now we're in PEE mode
 	// configure USB for 48 MHz clock
+#endif
+
 #if F_CPU == 168000000
 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(6) | SIM_CLKDIV2_USBFRAC; // USB = 168 MHz PLL * 2 / 7
 #elif F_CPU == 144000000

teensy3/mk20dx128.h

@@ -63,6 +63,18 @@
 #elif (F_CPU == 24000000)
  #define F_BUS 24000000
  #define F_MEM 24000000
+#elif (F_CPU == 16000000)
+ #define F_BUS 16000000
+ #define F_MEM 16000000
+#elif (F_CPU == 8000000)
+ #define F_BUS 8000000
+ #define F_MEM 8000000
+#elif (F_CPU == 4000000)
+ #define F_BUS 4000000
+ #define F_MEM 4000000
+#elif (F_CPU == 2000000)
+ #define F_BUS 2000000
+ #define F_MEM 2000000
 #endif
 
 

teensy3/pins_teensy.c

@@ -339,6 +339,12 @@ extern void usb_init(void);
 #elif F_BUS == 24000000
 #define DEFAULT_FTM_MOD (49152 - 1)
 #define DEFAULT_FTM_PRESCALE 0
+#elif F_BUS == 16000000
+#define DEFAULT_FTM_MOD (32768 - 1)
+#define DEFAULT_FTM_PRESCALE 0
+#elif F_BUS == 8000000
+#define DEFAULT_FTM_MOD (16384 - 1)
+#define DEFAULT_FTM_PRESCALE 0
 #elif F_BUS == 4000000
 #define DEFAULT_FTM_MOD (8192 - 1)
 #define DEFAULT_FTM_PRESCALE 0
@@ -719,6 +725,10 @@ void delay(uint32_t ms)
 #define PULSEIN_LOOPS_PER_USEC 7
 #elif F_CPU == 24000000
 #define PULSEIN_LOOPS_PER_USEC 4
+#elif F_CPU == 16000000
+#define PULSEIN_LOOPS_PER_USEC 1
+#elif F_CPU == 8000000
+#define PULSEIN_LOOPS_PER_USEC 1
 #elif F_CPU == 4000000
 #define PULSEIN_LOOPS_PER_USEC 1
 #elif F_CPU == 2000000