| while (transmitting) yield(); // wait for buffered data to send | while (transmitting) yield(); // wait for buffered data to send | ||||
| NVIC_DISABLE_IRQ(IRQ_UART1_STATUS); | NVIC_DISABLE_IRQ(IRQ_UART1_STATUS); | ||||
| UART1_C2 = 0; | UART1_C2 = 0; | ||||
| #if defined(KINETISK) | |||||
| switch (rx_pin_num) { | switch (rx_pin_num) { | ||||
| case 9: CORE_PIN9_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break; // PTC3 | case 9: CORE_PIN9_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break; // PTC3 | ||||
| #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.4 or T3.5 | |||||
| #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.5 or T3.6 | |||||
| case 26: CORE_PIN26_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break; // PTE1 | case 26: CORE_PIN26_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break; // PTE1 | ||||
| #endif | #endif | ||||
| } | } | ||||
| switch (tx_pin_num & 127) { | switch (tx_pin_num & 127) { | ||||
| case 10: CORE_PIN10_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break; // PTC4 | case 10: CORE_PIN10_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break; // PTC4 | ||||
| #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.4 or T3.5 | |||||
| #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.5 or T3.6 | |||||
| case 31: CORE_PIN31_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break; // PTE0 | case 31: CORE_PIN31_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break; // PTE0 | ||||
| #endif | #endif | ||||
| } | } | ||||
| #elif defined(KINETISL) | |||||
| CORE_PIN9_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); // PTC3 | |||||
| CORE_PIN10_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); // PTC4 | |||||
| #endif | |||||
| rx_buffer_head = 0; | rx_buffer_head = 0; | ||||
| rx_buffer_tail = 0; | rx_buffer_tail = 0; | ||||
| if (rts_pin) rts_deassert(); | if (rts_pin) rts_deassert(); | ||||
| if ((SIM_SCGC4 & SIM_SCGC4_UART1)) { | if ((SIM_SCGC4 & SIM_SCGC4_UART1)) { | ||||
| switch (tx_pin_num & 127) { | switch (tx_pin_num & 127) { | ||||
| case 10: CORE_PIN10_CONFIG = 0; break; // PTC4 | case 10: CORE_PIN10_CONFIG = 0; break; // PTC4 | ||||
| #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.4 or T3.5 | |||||
| #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.5 or T3.6 | |||||
| case 31: CORE_PIN31_CONFIG = 0; break; // PTE0 | case 31: CORE_PIN31_CONFIG = 0; break; // PTE0 | ||||
| #endif | #endif | ||||
| } | } | ||||
| } | } | ||||
| switch (pin & 127) { | switch (pin & 127) { | ||||
| case 10: CORE_PIN10_CONFIG = cfg | PORT_PCR_MUX(3); break; | case 10: CORE_PIN10_CONFIG = cfg | PORT_PCR_MUX(3); break; | ||||
| #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.4 or T3.5 | |||||
| #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.5 or T3.6 | |||||
| case 31: CORE_PIN31_CONFIG = cfg | PORT_PCR_MUX(3); break; | case 31: CORE_PIN31_CONFIG = cfg | PORT_PCR_MUX(3); break; | ||||
| #endif | #endif | ||||
| } | } | ||||
| if ((SIM_SCGC4 & SIM_SCGC4_UART1)) { | if ((SIM_SCGC4 & SIM_SCGC4_UART1)) { | ||||
| switch (rx_pin_num) { | switch (rx_pin_num) { | ||||
| case 9: CORE_PIN9_CONFIG = 0; break; // PTC3 | case 9: CORE_PIN9_CONFIG = 0; break; // PTC3 | ||||
| #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.4 or T3.5 | |||||
| #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.5 or T3.6 | |||||
| case 26: CORE_PIN26_CONFIG = 0; break; // PTE1 | case 26: CORE_PIN26_CONFIG = 0; break; // PTE1 | ||||
| #endif | #endif | ||||
| } | } | ||||
| switch (pin) { | switch (pin) { | ||||
| case 9: CORE_PIN9_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break; | case 9: CORE_PIN9_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break; | ||||
| #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.4 or T3.5 | |||||
| #if !(defined(__MK64FX512__) || defined(__MK66FX1M0__)) // not on T3.5 or T3.6 | |||||
| case 26: CORE_PIN26_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break; | case 26: CORE_PIN26_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break; | ||||
| #endif | #endif | ||||
| } | } |