| @@ -237,6 +237,9 @@ static void flash_write(void *addr, const void *data, uint32_t len) | |||
| FLEXSPI_LUTCR = FLEXSPI_LUTCR_UNLOCK; | |||
| FLEXSPI_IPCR0 = 0; | |||
| FLEXSPI_LUT60 = LUT0(CMD_SDR, PINS1, 0x06); // 06 = write enable | |||
| FLEXSPI_LUT61 = 0; | |||
| FLEXSPI_LUT62 = 0; | |||
| FLEXSPI_LUT63 = 0; | |||
| FLEXSPI_IPCR1 = FLEXSPI_IPCR1_ISEQID(15); | |||
| FLEXSPI_IPCMD = FLEXSPI_IPCMD_TRG; | |||
| arm_dcache_delete(addr, len); // purge old data from ARM's cache | |||
| @@ -273,6 +276,9 @@ static void flash_erase_sector(void *addr) | |||
| FLEXSPI_LUTKEY = FLEXSPI_LUTKEY_VALUE; | |||
| FLEXSPI_LUTCR = FLEXSPI_LUTCR_UNLOCK; | |||
| FLEXSPI_LUT60 = LUT0(CMD_SDR, PINS1, 0x06); // 06 = write enable | |||
| FLEXSPI_LUT61 = 0; | |||
| FLEXSPI_LUT62 = 0; | |||
| FLEXSPI_LUT63 = 0; | |||
| FLEXSPI_IPCR0 = 0; | |||
| FLEXSPI_IPCR1 = FLEXSPI_IPCR1_ISEQID(15); | |||
| FLEXSPI_IPCMD = FLEXSPI_IPCMD_TRG; | |||
| @@ -280,7 +286,6 @@ static void flash_erase_sector(void *addr) | |||
| while (!(FLEXSPI_INTR & FLEXSPI_INTR_IPCMDDONE)) ; // wait | |||
| FLEXSPI_INTR = FLEXSPI_INTR_IPCMDDONE; | |||
| FLEXSPI_LUT60 = LUT0(CMD_SDR, PINS1, 0x20) | LUT1(ADDR_SDR, PINS1, 24); // 20 = sector erase | |||
| FLEXSPI_LUT61 = 0; | |||
| FLEXSPI_IPCR0 = (uint32_t)addr & 0x001FF000; | |||
| FLEXSPI_IPCR1 = FLEXSPI_IPCR1_ISEQID(15); | |||
| FLEXSPI_IPCMD = FLEXSPI_IPCMD_TRG; | |||