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T4.x CTS pins - T4.1 add memory chip area to Serial ports.

A few of the T4 and now T4.1 Serial ports support a CTS pin.  One was previous fixed, added the others to tables.

Also T4.1 has Some Serial port pins in the area that the optional memory chips could be installed
teensy4-core
Kurt Eckhardt 4 years ago
parent
commit
72ed1825e1
7 changed files with 17 additions and 10 deletions
  1. +6
    -1
      teensy4/HardwareSerial1.cpp
  2. +1
    -1
      teensy4/HardwareSerial2.cpp
  3. +1
    -1
      teensy4/HardwareSerial3.cpp
  4. +1
    -1
      teensy4/HardwareSerial4.cpp
  5. +4
    -2
      teensy4/HardwareSerial5.cpp
  6. +1
    -1
      teensy4/HardwareSerial7.cpp
  7. +3
    -3
      teensy4/HardwareSerial8.cpp

+ 6
- 1
teensy4/HardwareSerial1.cpp View File

const HardwareSerial::hardware_t UART6_Hardware = { const HardwareSerial::hardware_t UART6_Hardware = {
0, IRQ_LPUART6, &IRQHandler_Serial1, &serial_event_check_serial1, 0, IRQ_LPUART6, &IRQHandler_Serial1, &serial_event_check_serial1,
CCM_CCGR3, CCM_CCGR3_LPUART6(CCM_CCGR_ON), CCM_CCGR3, CCM_CCGR3_LPUART6(CCM_CCGR_ON),
#if defined(ARDUINO_TEENSY41)
{{0,2, &IOMUXC_LPUART6_RX_SELECT_INPUT, 1}, {52, 2, &IOMUXC_LPUART6_RX_SELECT_INPUT, 0}},
{{1,2, &IOMUXC_LPUART6_TX_SELECT_INPUT, 0}, {53, 2, nullptr, 0}},
#else
{{0,2, &IOMUXC_LPUART6_RX_SELECT_INPUT, 1}, {0xff, 0xff, nullptr, 0}}, {{0,2, &IOMUXC_LPUART6_RX_SELECT_INPUT, 1}, {0xff, 0xff, nullptr, 0}},
{{1,2, nullptr, 0}, {0xff, 0xff, nullptr, 0}},
{{1,2, &IOMUXC_LPUART6_TX_SELECT_INPUT, 1}, {0xff, 0xff, nullptr, 0}},
#endif
0xff, // No CTS pin 0xff, // No CTS pin
0, // No CTS 0, // No CTS
IRQ_PRIORITY, 38, 24, // IRQ, rts_low_watermark, rts_high_watermark IRQ_PRIORITY, 38, 24, // IRQ, rts_low_watermark, rts_high_watermark

+ 1
- 1
teensy4/HardwareSerial2.cpp View File

{{7,2, nullptr, 0}, {0xff, 0xff, nullptr, 0}}, {{7,2, nullptr, 0}, {0xff, 0xff, nullptr, 0}},
#elif defined(__IMXRT1062__) #elif defined(__IMXRT1062__)
{{7,2, &IOMUXC_LPUART4_RX_SELECT_INPUT, 2}, {0xff, 0xff, nullptr, 0}}, {{7,2, &IOMUXC_LPUART4_RX_SELECT_INPUT, 2}, {0xff, 0xff, nullptr, 0}},
{{8,2, nullptr, 0}, {0xff, 0xff, nullptr, 0}},
{{8,2, &IOMUXC_LPUART4_TX_SELECT_INPUT, 2}, {0xff, 0xff, nullptr, 0}},
#endif #endif
0xff, // No CTS pin 0xff, // No CTS pin
0, // No CTS 0, // No CTS

+ 1
- 1
teensy4/HardwareSerial3.cpp View File

2, IRQ_LPUART2, &IRQHandler_Serial3, &serial_event_check_serial3, 2, IRQ_LPUART2, &IRQHandler_Serial3, &serial_event_check_serial3,
CCM_CCGR0, CCM_CCGR0_LPUART2(CCM_CCGR_ON), CCM_CCGR0, CCM_CCGR0_LPUART2(CCM_CCGR_ON),
{{15,2, &IOMUXC_LPUART2_RX_SELECT_INPUT, 1}, {0xff, 0xff, nullptr, 0}}, {{15,2, &IOMUXC_LPUART2_RX_SELECT_INPUT, 1}, {0xff, 0xff, nullptr, 0}},
{{14,2, nullptr, 0}, {0xff, 0xff, nullptr, 0}},
{{14,2, &IOMUXC_LPUART2_TX_SELECT_INPUT, 1}, {0xff, 0xff, nullptr, 0}},
19, //IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00, // 19 19, //IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00, // 19
2, // page 473 2, // page 473
IRQ_PRIORITY, 38, 24, // IRQ, rts_low_watermark, rts_high_watermark IRQ_PRIORITY, 38, 24, // IRQ, rts_low_watermark, rts_high_watermark

+ 1
- 1
teensy4/HardwareSerial4.cpp View File

3, IRQ_LPUART3, &IRQHandler_Serial4, &serial_event_check_serial4, 3, IRQ_LPUART3, &IRQHandler_Serial4, &serial_event_check_serial4,
CCM_CCGR0, CCM_CCGR0_LPUART3(CCM_CCGR_ON), CCM_CCGR0, CCM_CCGR0_LPUART3(CCM_CCGR_ON),
{{16,2, &IOMUXC_LPUART3_RX_SELECT_INPUT, 0}, {0xff, 0xff, nullptr, 0}}, {{16,2, &IOMUXC_LPUART3_RX_SELECT_INPUT, 0}, {0xff, 0xff, nullptr, 0}},
{{17,2, nullptr, 0}, {0xff, 0xff, nullptr, 0}},
{{17,2, &IOMUXC_LPUART3_TX_SELECT_INPUT, 0}, {0xff, 0xff, nullptr, 0}},
0xff, // No CTS pin 0xff, // No CTS pin
0, // No CTS 0, // No CTS
IRQ_PRIORITY, 38, 24, // IRQ, rts_low_watermark, rts_high_watermark IRQ_PRIORITY, 38, 24, // IRQ, rts_low_watermark, rts_high_watermark

+ 4
- 2
teensy4/HardwareSerial5.cpp View File

#if defined(ARDUINO_TEENSY41) #if defined(ARDUINO_TEENSY41)
{{21,2, &IOMUXC_LPUART8_RX_SELECT_INPUT, 1}, {46, 2, &IOMUXC_LPUART8_RX_SELECT_INPUT, 0}}, {{21,2, &IOMUXC_LPUART8_RX_SELECT_INPUT, 1}, {46, 2, &IOMUXC_LPUART8_RX_SELECT_INPUT, 0}},
{{20,2, &IOMUXC_LPUART8_TX_SELECT_INPUT, 1}, {47, 2, &IOMUXC_LPUART8_TX_SELECT_INPUT, 0}}, {{20,2, &IOMUXC_LPUART8_TX_SELECT_INPUT, 1}, {47, 2, &IOMUXC_LPUART8_TX_SELECT_INPUT, 0}},
43, // CTS pin
2, // CTS
#else #else
{{21,2, &IOMUXC_LPUART8_RX_SELECT_INPUT, 1}, {38, 2, &IOMUXC_LPUART8_RX_SELECT_INPUT, 0}}, {{21,2, &IOMUXC_LPUART8_RX_SELECT_INPUT, 1}, {38, 2, &IOMUXC_LPUART8_RX_SELECT_INPUT, 0}},
{{20,2, &IOMUXC_LPUART8_TX_SELECT_INPUT, 1}, {39, 2, &IOMUXC_LPUART8_TX_SELECT_INPUT, 0}}, {{20,2, &IOMUXC_LPUART8_TX_SELECT_INPUT, 1}, {39, 2, &IOMUXC_LPUART8_TX_SELECT_INPUT, 0}},
35, // CTS pin
2, // CTS
#endif #endif
0xff, // No CTS pin
0, // No CTS
IRQ_PRIORITY, 38, 24, // IRQ, rts_low_watermark, rts_high_watermark IRQ_PRIORITY, 38, 24, // IRQ, rts_low_watermark, rts_high_watermark
}; };
HardwareSerial Serial5(&IMXRT_LPUART8, &UART8_Hardware, tx_buffer5, SERIAL5_TX_BUFFER_SIZE, HardwareSerial Serial5(&IMXRT_LPUART8, &UART8_Hardware, tx_buffer5, SERIAL5_TX_BUFFER_SIZE,

+ 1
- 1
teensy4/HardwareSerial7.cpp View File

6, IRQ_LPUART7, &IRQHandler_Serial7, &serial_event_check_serial7, 6, IRQ_LPUART7, &IRQHandler_Serial7, &serial_event_check_serial7,
CCM_CCGR5, CCM_CCGR5_LPUART7(CCM_CCGR_ON), CCM_CCGR5, CCM_CCGR5_LPUART7(CCM_CCGR_ON),
{{28,2, &IOMUXC_LPUART7_RX_SELECT_INPUT, 1}, {0xff, 0xff, nullptr, 0}}, {{28,2, &IOMUXC_LPUART7_RX_SELECT_INPUT, 1}, {0xff, 0xff, nullptr, 0}},
{{29,2, nullptr, 0}, {0xff, 0xff, nullptr, 0}},
{{29,2, &IOMUXC_LPUART7_TX_SELECT_INPUT, 1}, {0xff, 0xff, nullptr, 0}},
0xff, // No CTS pin 0xff, // No CTS pin
0, // No CTS 0, // No CTS
IRQ_PRIORITY, 38, 24, // IRQ, rts_low_watermark, rts_high_watermark IRQ_PRIORITY, 38, 24, // IRQ, rts_low_watermark, rts_high_watermark

+ 3
- 3
teensy4/HardwareSerial8.cpp View File

static HardwareSerial::hardware_t UART5_Hardware = { static HardwareSerial::hardware_t UART5_Hardware = {
7, IRQ_LPUART5, &IRQHandler_Serial8, &serial_event_check_serial8, 7, IRQ_LPUART5, &IRQHandler_Serial8, &serial_event_check_serial8,
CCM_CCGR3, CCM_CCGR3_LPUART5(CCM_CCGR_ON), CCM_CCGR3, CCM_CCGR3_LPUART5(CCM_CCGR_ON),
{{34,1, &IOMUXC_LPUART5_RX_SELECT_INPUT, 1}, {0xff, 0xff, nullptr, 0}},
{{34,1, &IOMUXC_LPUART5_RX_SELECT_INPUT, 1}, {48, 2, &IOMUXC_LPUART5_RX_SELECT_INPUT, 0}},
{{35,1, &IOMUXC_LPUART5_TX_SELECT_INPUT, 1}, {0xff, 0xff, nullptr, 0}}, {{35,1, &IOMUXC_LPUART5_TX_SELECT_INPUT, 1}, {0xff, 0xff, nullptr, 0}},


0xff, // No CTS pin
0, // No CTS
50, // CTS pin
2, // CTS
IRQ_PRIORITY, 38, 24, // IRQ, rts_low_watermark, rts_high_watermark IRQ_PRIORITY, 38, 24, // IRQ, rts_low_watermark, rts_high_watermark
}; };
HardwareSerial Serial8(&IMXRT_LPUART5, &UART5_Hardware, tx_buffer8, SERIAL8_TX_BUFFER_SIZE, HardwareSerial Serial8(&IMXRT_LPUART5, &UART5_Hardware, tx_buffer8, SERIAL8_TX_BUFFER_SIZE,

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