On Serial 3 this addition is for all 3.x. Before it was ifdefed to only do work on Teensy_LC as there is only one valid TX pin. But we now pass in open drain as an option so this code should allow you to not turn it on/off on Serial3 on all of these boards and on Serial4 and Serial5 on the new boards.teensy4-core
* permit persons to whom the Software is furnished to do so, subject to | * permit persons to whom the Software is furnished to do so, subject to | ||||
* the following conditions: | * the following conditions: | ||||
* | * | ||||
* 1. The above copyright notice and this permission notice shall be | |||||
* 1. The above copyright notice and this permission notice shall be | |||||
* included in all copies or substantial portions of the Software. | * included in all copies or substantial portions of the Software. | ||||
* | * | ||||
* 2. If the Software is incorporated into a build system that allows | |||||
* 2. If the Software is incorporated into a build system that allows | |||||
* selection among a list of target devices, then similar target | * selection among a list of target devices, then similar target | ||||
* devices manufactured by PJRC.COM must be included in the list of | * devices manufactured by PJRC.COM must be included in the list of | ||||
* target devices and selectable in the same manner. | * target devices and selectable in the same manner. | ||||
#endif | #endif | ||||
#if defined(KINETISL) | #if defined(KINETISL) | ||||
static uint8_t rx_pin_num = 7; | static uint8_t rx_pin_num = 7; | ||||
static uint8_t tx_pin_num = 8; | |||||
#endif | #endif | ||||
static uint8_t tx_pin_num = 8; | |||||
// UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS | // UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS | ||||
// UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer | // UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer | ||||
void serial3_set_tx(uint8_t pin, uint8_t opendrain) | void serial3_set_tx(uint8_t pin, uint8_t opendrain) | ||||
{ | { | ||||
#if defined(KINETISL) | |||||
uint32_t cfg; | uint32_t cfg; | ||||
if (opendrain) pin |= 128; | if (opendrain) pin |= 128; | ||||
if ((SIM_SCGC4 & SIM_SCGC4_UART2)) { | if ((SIM_SCGC4 & SIM_SCGC4_UART2)) { | ||||
switch (tx_pin_num & 127) { | switch (tx_pin_num & 127) { | ||||
case 8: CORE_PIN8_CONFIG = 0; break; // PTD3 | case 8: CORE_PIN8_CONFIG = 0; break; // PTD3 | ||||
#if defined(KINETISL) | |||||
case 20: CORE_PIN20_CONFIG = 0; break; // PTD5 | case 20: CORE_PIN20_CONFIG = 0; break; // PTD5 | ||||
#endif | |||||
} | } | ||||
if (opendrain) { | if (opendrain) { | ||||
cfg = PORT_PCR_DSE | PORT_PCR_ODE; | cfg = PORT_PCR_DSE | PORT_PCR_ODE; | ||||
} | } | ||||
switch (pin & 127) { | switch (pin & 127) { | ||||
case 8: CORE_PIN8_CONFIG = cfg | PORT_PCR_MUX(3); break; | case 8: CORE_PIN8_CONFIG = cfg | PORT_PCR_MUX(3); break; | ||||
#if defined(KINETISL) | |||||
case 20: CORE_PIN20_CONFIG = cfg | PORT_PCR_MUX(3); break; | case 20: CORE_PIN20_CONFIG = cfg | PORT_PCR_MUX(3); break; | ||||
#endif | |||||
} | } | ||||
} | } | ||||
tx_pin_num = pin; | tx_pin_num = pin; | ||||
#endif | |||||
} | } | ||||
void serial3_set_rx(uint8_t pin) | void serial3_set_rx(uint8_t pin) | ||||
if (rts_pin) rts_assert(); | if (rts_pin) rts_assert(); | ||||
} | } | ||||
// status interrupt combines | |||||
// status interrupt combines | |||||
// Transmit data below watermark UART_S1_TDRE | // Transmit data below watermark UART_S1_TDRE | ||||
// Transmit complete UART_S1_TC | // Transmit complete UART_S1_TC | ||||
// Idle line UART_S1_IDLE | // Idle line UART_S1_IDLE | ||||
if (head >= RX_BUFFER_SIZE) head = 0; | if (head >= RX_BUFFER_SIZE) head = 0; | ||||
if (head != rx_buffer_tail) { | if (head != rx_buffer_tail) { | ||||
rx_buffer[head] = n; | rx_buffer[head] = n; | ||||
rx_buffer_head = head; | |||||
rx_buffer_head = head; | |||||
} | } | ||||
if (rts_pin) { | if (rts_pin) { | ||||
int avail; | int avail; |
* permit persons to whom the Software is furnished to do so, subject to | * permit persons to whom the Software is furnished to do so, subject to | ||||
* the following conditions: | * the following conditions: | ||||
* | * | ||||
* 1. The above copyright notice and this permission notice shall be | |||||
* 1. The above copyright notice and this permission notice shall be | |||||
* included in all copies or substantial portions of the Software. | * included in all copies or substantial portions of the Software. | ||||
* | * | ||||
* 2. If the Software is incorporated into a build system that allows | |||||
* 2. If the Software is incorporated into a build system that allows | |||||
* selection among a list of target devices, then similar target | * selection among a list of target devices, then similar target | ||||
* devices manufactured by PJRC.COM must be included in the list of | * devices manufactured by PJRC.COM must be included in the list of | ||||
* target devices and selectable in the same manner. | * target devices and selectable in the same manner. | ||||
static volatile uint8_t rx_buffer_tail = 0; | static volatile uint8_t rx_buffer_tail = 0; | ||||
#endif | #endif | ||||
static uint8_t tx_pin_num = 32; | |||||
// UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS | // UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS | ||||
// UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer | // UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer | ||||
void serial4_set_tx(uint8_t pin, uint8_t opendrain) | void serial4_set_tx(uint8_t pin, uint8_t opendrain) | ||||
{ | { | ||||
uint32_t cfg; | |||||
if (opendrain) pin |= 128; | |||||
if (pin == tx_pin_num) return; | |||||
if ((SIM_SCGC4 & SIM_SCGC4_UART2)) { | |||||
switch (tx_pin_num & 127) { | |||||
case 32: CORE_PIN8_CONFIG = 0; break; // PTD3 | |||||
} | |||||
if (opendrain) { | |||||
cfg = PORT_PCR_DSE | PORT_PCR_ODE; | |||||
} else { | |||||
cfg = PORT_PCR_DSE | PORT_PCR_SRE; | |||||
} | |||||
switch (pin & 127) { | |||||
case 32: CORE_PIN8_CONFIG = cfg | PORT_PCR_MUX(3); break; | |||||
} | |||||
} | |||||
tx_pin_num = pin; | |||||
} | } | ||||
void serial4_set_rx(uint8_t pin) | void serial4_set_rx(uint8_t pin) | ||||
if (rts_pin) rts_assert(); | if (rts_pin) rts_assert(); | ||||
} | } | ||||
// status interrupt combines | |||||
// status interrupt combines | |||||
// Transmit data below watermark UART_S1_TDRE | // Transmit data below watermark UART_S1_TDRE | ||||
// Transmit complete UART_S1_TC | // Transmit complete UART_S1_TC | ||||
// Idle line UART_S1_IDLE | // Idle line UART_S1_IDLE | ||||
if (head >= RX_BUFFER_SIZE) head = 0; | if (head >= RX_BUFFER_SIZE) head = 0; | ||||
if (head != rx_buffer_tail) { | if (head != rx_buffer_tail) { | ||||
rx_buffer[head] = n; | rx_buffer[head] = n; | ||||
rx_buffer_head = head; | |||||
rx_buffer_head = head; | |||||
} | } | ||||
if (rts_pin) { | if (rts_pin) { | ||||
int avail; | int avail; |
* permit persons to whom the Software is furnished to do so, subject to | * permit persons to whom the Software is furnished to do so, subject to | ||||
* the following conditions: | * the following conditions: | ||||
* | * | ||||
* 1. The above copyright notice and this permission notice shall be | |||||
* 1. The above copyright notice and this permission notice shall be | |||||
* included in all copies or substantial portions of the Software. | * included in all copies or substantial portions of the Software. | ||||
* | * | ||||
* 2. If the Software is incorporated into a build system that allows | |||||
* 2. If the Software is incorporated into a build system that allows | |||||
* selection among a list of target devices, then similar target | * selection among a list of target devices, then similar target | ||||
* devices manufactured by PJRC.COM must be included in the list of | * devices manufactured by PJRC.COM must be included in the list of | ||||
* target devices and selectable in the same manner. | * target devices and selectable in the same manner. | ||||
static volatile uint8_t rx_buffer_tail = 0; | static volatile uint8_t rx_buffer_tail = 0; | ||||
#endif | #endif | ||||
static uint8_t tx_pin_num = 34; | |||||
// UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS | // UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS | ||||
// UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer | // UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer | ||||
void serial5_set_tx(uint8_t pin, uint8_t opendrain) | void serial5_set_tx(uint8_t pin, uint8_t opendrain) | ||||
{ | { | ||||
uint32_t cfg; | |||||
if (opendrain) pin |= 128; | |||||
if (pin == tx_pin_num) return; | |||||
if ((SIM_SCGC4 & SIM_SCGC4_UART2)) { | |||||
switch (tx_pin_num & 127) { | |||||
case 34: CORE_PIN8_CONFIG = 0; break; // PTD3 | |||||
} | |||||
if (opendrain) { | |||||
cfg = PORT_PCR_DSE | PORT_PCR_ODE; | |||||
} else { | |||||
cfg = PORT_PCR_DSE | PORT_PCR_SRE; | |||||
} | |||||
switch (pin & 127) { | |||||
case 34: CORE_PIN8_CONFIG = cfg | PORT_PCR_MUX(3); break; | |||||
} | |||||
} | |||||
tx_pin_num = pin; | |||||
} | } | ||||
void serial5_set_rx(uint8_t pin) | void serial5_set_rx(uint8_t pin) | ||||
if (rts_pin) rts_assert(); | if (rts_pin) rts_assert(); | ||||
} | } | ||||
// status interrupt combines | |||||
// status interrupt combines | |||||
// Transmit data below watermark UART_S1_TDRE | // Transmit data below watermark UART_S1_TDRE | ||||
// Transmit complete UART_S1_TC | // Transmit complete UART_S1_TC | ||||
// Idle line UART_S1_IDLE | // Idle line UART_S1_IDLE | ||||
if (head >= RX_BUFFER_SIZE) head = 0; | if (head >= RX_BUFFER_SIZE) head = 0; | ||||
if (head != rx_buffer_tail) { | if (head != rx_buffer_tail) { | ||||
rx_buffer[head] = n; | rx_buffer[head] = n; | ||||
rx_buffer_head = head; | |||||
rx_buffer_head = head; | |||||
} | } | ||||
if (rts_pin) { | if (rts_pin) { | ||||
int avail; | int avail; |