PaulStoffregen
6 years ago
1 changed files with 77 additions and 0 deletions
+ 77
- 0
teensy4/imxrt.h
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| #define IOMUXC_XBAR1_IN25_SELECT_INPUT (IMXRT_IOMUXC_b.offset250) | #define IOMUXC_XBAR1_IN25_SELECT_INPUT (IMXRT_IOMUXC_b.offset250) | ||||
| #define IOMUXC_XBAR1_IN19_SELECT_INPUT (IMXRT_IOMUXC_b.offset254) | #define IOMUXC_XBAR1_IN19_SELECT_INPUT (IMXRT_IOMUXC_b.offset254) | ||||
| #define IOMUXC_XBAR1_IN21_SELECT_INPUT (IMXRT_IOMUXC_b.offset258) | #define IOMUXC_XBAR1_IN21_SELECT_INPUT (IMXRT_IOMUXC_b.offset258) | ||||
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_00 (IMXRT_IOMUXC_b.offset25C) | |||||
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_01 (IMXRT_IOMUXC_b.offset260) | |||||
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_02 (IMXRT_IOMUXC_b.offset264) | |||||
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_03 (IMXRT_IOMUXC_b.offset268) | |||||
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_04 (IMXRT_IOMUXC_b.offset26C) | |||||
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_05 (IMXRT_IOMUXC_b.offset270) | |||||
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_06 (IMXRT_IOMUXC_b.offset274) | |||||
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_07 (IMXRT_IOMUXC_b.offset278) | |||||
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_08 (IMXRT_IOMUXC_b.offset27C) | |||||
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_09 (IMXRT_IOMUXC_b.offset280) | |||||
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_10 (IMXRT_IOMUXC_b.offset284) | |||||
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_11 (IMXRT_IOMUXC_b.offset288) | |||||
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_12 (IMXRT_IOMUXC_b.offset28C) | |||||
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_13 (IMXRT_IOMUXC_b.offset290) | |||||
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_00 (IMXRT_IOMUXC_b.offset294) | |||||
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_01 (IMXRT_IOMUXC_b.offset298) | |||||
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_02 (IMXRT_IOMUXC_b.offset29C) | |||||
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_03 (IMXRT_IOMUXC_b.offset2A0) | |||||
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_04 (IMXRT_IOMUXC_b.offset2A4) | |||||
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_05 (IMXRT_IOMUXC_b.offset2A8) | |||||
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_06 (IMXRT_IOMUXC_b.offset2AC) | |||||
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_07 (IMXRT_IOMUXC_b.offset2B0) | |||||
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_00 (IMXRT_IOMUXC_b.offset2B4) | |||||
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_01 (IMXRT_IOMUXC_b.offset2B8) | |||||
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_02 (IMXRT_IOMUXC_b.offset2BC) | |||||
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_03 (IMXRT_IOMUXC_b.offset2C0) | |||||
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_04 (IMXRT_IOMUXC_b.offset2C4) | |||||
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_05 (IMXRT_IOMUXC_b.offset2C8) | |||||
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_06 (IMXRT_IOMUXC_b.offset2CC) | |||||
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_07 (IMXRT_IOMUXC_b.offset2D0) | |||||
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_08 (IMXRT_IOMUXC_b.offset2D4) | |||||
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_09 (IMXRT_IOMUXC_b.offset2D8) | |||||
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_10 (IMXRT_IOMUXC_b.offset2DC) | |||||
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_11 (IMXRT_IOMUXC_b.offset2E0) | |||||
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_12 (IMXRT_IOMUXC_b.offset2E4) | |||||
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_13 (IMXRT_IOMUXC_b.offset2E8) | |||||
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_00 (IMXRT_IOMUXC_b.offset2EC) | |||||
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_01 (IMXRT_IOMUXC_b.offset2F0) | |||||
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_02 (IMXRT_IOMUXC_b.offset2F4) | |||||
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_03 (IMXRT_IOMUXC_b.offset2F8) | |||||
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_04 (IMXRT_IOMUXC_b.offset2FC) | |||||
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_05 (IMXRT_IOMUXC_b.offset300) | |||||
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_06 (IMXRT_IOMUXC_b.offset304) | |||||
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_07 (IMXRT_IOMUXC_b.offset308) | |||||
| #define IOMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT (IMXRT_IOMUXC_b.offset30C) | |||||
| #define IOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT (IMXRT_IOMUXC_b.offset310) | |||||
| #define IOMUXC_ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_0 (IMXRT_IOMUXC_b.offset314) | |||||
| #define IOMUXC_ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_1 (IMXRT_IOMUXC_b.offset318) | |||||
| #define IOMUXC_ENET2_IPP_IND_MAC0_RXEN_SELECT_INPUT (IMXRT_IOMUXC_b.offset31C) | |||||
| #define IOMUXC_ENET2_IPP_IND_MAC0_RXERR_SELECT_INPUT (IMXRT_IOMUXC_b.offset320) | |||||
| #define IOMUXC_ENET2_IPP_IND_MAC0_TIMER_SELECT_INPUT_0 (IMXRT_IOMUXC_b.offset324) | |||||
| #define IOMUXC_ENET2_IPP_IND_MAC0_TXCLK_SELECT_INPUT (IMXRT_IOMUXC_b.offset328) | |||||
| #define IOMUXC_FLEXSPI2_IPP_IND_DQS_FA_SELECT_INPUT (IMXRT_IOMUXC_b.offset32C) | |||||
| #define IOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT0_SELECT_INPUT (IMXRT_IOMUXC_b.offset330) | |||||
| #define IOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT1_SELECT_INPUT (IMXRT_IOMUXC_b.offset334) | |||||
| #define IOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT2_SELECT_INPUT (IMXRT_IOMUXC_b.offset338) | |||||
| #define IOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT3_SELECT_INPUT (IMXRT_IOMUXC_b.offset33C) | |||||
| #define IOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT0_SELECT_INPUT (IMXRT_IOMUXC_b.offset340) | |||||
| #define IOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT1_SELECT_INPUT (IMXRT_IOMUXC_b.offset344) | |||||
| #define IOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT2_SELECT_INPUT (IMXRT_IOMUXC_b.offset348) | |||||
| #define IOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT3_SELECT_INPUT (IMXRT_IOMUXC_b.offset34C) | |||||
| #define IOMUXC_FLEXSPI2_IPP_IND_SCK_FA_SELECT_INPUT (IMXRT_IOMUXC_b.offset350) | |||||
| #define IOMUXC_FLEXSPI2_IPP_IND_SCK_FB_SELECT_INPUT (IMXRT_IOMUXC_b.offset354) | |||||
| #define IOMUXC_GPT1_IPP_IND_CAPIN1_SELECT_INPUT (IMXRT_IOMUXC_b.offset358) | |||||
| #define IOMUXC_GPT1_IPP_IND_CAPIN2_SELECT_INPUT (IMXRT_IOMUXC_b.offset35C) | |||||
| #define IOMUXC_GPT1_IPP_IND_CLKIN_SELECT_INPUT (IMXRT_IOMUXC_b.offset360) | |||||
| #define IOMUXC_GPT2_IPP_IND_CAPIN1_SELECT_INPUT (IMXRT_IOMUXC_b.offset364) | |||||
| #define IOMUXC_GPT2_IPP_IND_CAPIN2_SELECT_INPUT (IMXRT_IOMUXC_b.offset368) | |||||
| #define IOMUXC_GPT2_IPP_IND_CLKIN_SELECT_INPUT (IMXRT_IOMUXC_b.offset36C) | |||||
| #define IOMUXC_SAI3_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 (IMXRT_IOMUXC_b.offset370) | |||||
| #define IOMUXC_SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT (IMXRT_IOMUXC_b.offset374) | |||||
| #define IOMUXC_SAI3_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 (IMXRT_IOMUXC_b.offset378) | |||||
| #define IOMUXC_SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT (IMXRT_IOMUXC_b.offset37C) | |||||
| #define IOMUXC_SAI3_IPP_IND_SAI_TXBCLK_SELECT_INPUT (IMXRT_IOMUXC_b.offset380) | |||||
| #define IOMUXC_SAI3_IPP_IND_SAI_TXSYNC_SELECT_INPUT (IMXRT_IOMUXC_b.offset384) | |||||
| #define IOMUXC_SEMC_I_IPP_IND_DQS4_SELECT_INPUT (IMXRT_IOMUXC_b.offset388) | |||||
| #define IOMUXC_CANFD_IPP_IND_CANRX_SELECT_INPUT (IMXRT_IOMUXC_b.offset38C) | |||||
| #define IOMUXC_PAD_SRE ((uint32_t)(1<<0)) | #define IOMUXC_PAD_SRE ((uint32_t)(1<<0)) | ||||
| #define IOMUXC_PAD_DSE(n) ((uint32_t)(((n) & 0x07) << 3)) | #define IOMUXC_PAD_DSE(n) ((uint32_t)(((n) & 0x07) << 3)) | ||||
| #define IOMUXC_PAD_SPEED(n) ((uint32_t)(((n) & 0x03) << 6)) | #define IOMUXC_PAD_SPEED(n) ((uint32_t)(((n) & 0x03) << 6)) |
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