@@ -3,29 +3,94 @@ | |||
#include "avr_emulation.h" | |||
#if F_BUS == 60000000 | |||
#define HAS_SPIFIFO | |||
#define SPI_CLOCK_24MHz (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(60 / 3) * ((1+1)/2) = 20 MHz | |||
#define SPI_CLOCK_16MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0)) //(60 / 2) * ((1+0)/2) = 15 MHz | |||
#define SPI_CLOCK_12MHz (SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(60 / 5) * ((1+1)/2) | |||
#define SPI_CLOCK_8MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1)) //(60 / 2) * ((1+0)/4) = 7.5 MHz | |||
#define SPI_CLOCK_6MHz (SPI_CTAR_PBR(2) | SPI_CTAR_BR(0)) //(60 / 5) * ((1+0)/2) | |||
#define SPI_CLOCK_4MHz (SPI_CTAR_PBR(2) | SPI_CTAR_BR(2) | SPI_CTAR_DBR) //(60 / 5) * ((1+1)/6) | |||
#if F_BUS == 48000000 | |||
#elif F_BUS == 56000000 | |||
#define HAS_SPIFIFO | |||
#define SPI_CLOCK_24MHz (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(56 / 3) * ((1+1)/2) = 18.67 | |||
#define SPI_CLOCK_16MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0)) //(56 / 2) * ((1+0)/2) = 14 | |||
#define SPI_CLOCK_12MHz (SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(56 / 5) * ((1+1)/2) = 11.2 | |||
#define SPI_CLOCK_8MHz (SPI_CTAR_PBR(3) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(56 / 7) * ((1+1)/2) | |||
#define SPI_CLOCK_6MHz (SPI_CTAR_PBR(2) | SPI_CTAR_BR(0)) //(56 / 5) * ((1+0)/2) | |||
#define SPI_CLOCK_4MHz (SPI_CTAR_PBR(3) | SPI_CTAR_BR(0)) //(56 / 7) * ((1+0)/2) | |||
#elif F_BUS == 48000000 | |||
#define HAS_SPIFIFO | |||
#define SPI_CLOCK_24MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(48 / 2) * ((1+1)/2) | |||
#define SPI_CLOCK_16MHz (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(48 / 3) * ((1+1)/2) 33% duty cycle | |||
#define SPI_CLOCK_12MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0)) //(48 / 2) * ((1+0)/2) | |||
#define SPI_CLOCK_8MHz (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0)) //(48 / 3) * ((1+0)/2) | |||
#define SPI_CLOCK_6MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1)) //(48 / 2) * ((1+0)/4) | |||
#define SPI_CLOCK_4MHz (SPI_CTAR_PBR(1) | SPI_CTAR_BR(1)) //(48 / 3) * ((1+0)/4) | |||
#define SPI_CLOCK_16MHz (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(48 / 3) * ((1+1)/2) | |||
#define SPI_CLOCK_12MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0)) //(48 / 2) * ((1+0)/2) | |||
#define SPI_CLOCK_8MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(2) | SPI_CTAR_DBR) //(48 / 2) * ((1+1)/6) | |||
#define SPI_CLOCK_6MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1)) //(48 / 2) * ((1+0)/4) | |||
#define SPI_CLOCK_4MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(2)) //(48 / 2) * ((1+0)/6) | |||
#elif F_BUS == 24000000 | |||
#elif F_BUS == 40000000 | |||
#define HAS_SPIFIFO | |||
#define SPI_CLOCK_24MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(40 / 2) * ((1+1)/2) = 20 | |||
#define SPI_CLOCK_16MHz (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(40 / 3) * ((1+1)/2) = 13.33 | |||
#define SPI_CLOCK_12MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0)) //(40 / 2) * ((1+0)/2) = 10 | |||
#define SPI_CLOCK_8MHz (SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(40 / 5) * ((1+1)/2) | |||
#define SPI_CLOCK_6MHz (SPI_CTAR_PBR(3) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(40 / 7) * ((1+1)/2) = 5.71 | |||
#define SPI_CLOCK_4MHz (SPI_CTAR_PBR(2) | SPI_CTAR_BR(1)) //(40 / 5) * ((1+0)/2) | |||
#elif F_BUS == 36000000 | |||
#define HAS_SPIFIFO | |||
#define SPI_CLOCK_24MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(36 / 2) * ((1+1)/2) = 18 | |||
#define SPI_CLOCK_16MHz (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(36 / 3) * ((1+1)/2) = 12 | |||
#define SPI_CLOCK_12MHz (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(36 / 3) * ((1+1)/2) = 12 | |||
#define SPI_CLOCK_8MHz (SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(36 / 5) * ((1+1)/2) = 7.2 | |||
#define SPI_CLOCK_6MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(2) | SPI_CTAR_DBR) //(36 / 2) * ((1+1)/6) | |||
#define SPI_CLOCK_4MHz (SPI_CTAR_PBR(1) | SPI_CTAR_BR(2) | SPI_CTAR_DBR) //(36 / 3) * ((1+1)/6) | |||
#elif F_BUS == 24000000 | |||
#define HAS_SPIFIFO | |||
#define SPI_CLOCK_24MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(24 / 2) * ((1+1)/2) 12 MHz | |||
#define SPI_CLOCK_16MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(24 / 2) * ((1+1)/2) 12 MHz | |||
#define SPI_CLOCK_12MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(24 / 2) * ((1+1)/2) | |||
#define SPI_CLOCK_8MHz (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(24 / 3) * ((1+1)/2) 33% duty cycle | |||
#define SPI_CLOCK_6MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0)) //(24 / 2) * ((1+0)/2) | |||
#define SPI_CLOCK_4MHz (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0)) //(24 / 3) * ((1+0)/2) | |||
#define SPI_CLOCK_8MHz (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(24 / 3) * ((1+1)/2) | |||
#define SPI_CLOCK_6MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0)) //(24 / 2) * ((1+0)/2) | |||
#define SPI_CLOCK_4MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(2) | SPI_CTAR_DBR) //(24 / 2) * ((1+1)/6) | |||
#elif F_BUS == 4000000 | |||
#define HAS_SPIFIFO | |||
#define SPI_CLOCK_24MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 2 MHz | |||
#define SPI_CLOCK_16MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 2 MHz | |||
#define SPI_CLOCK_12MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 2 MHz | |||
#define SPI_CLOCK_8MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 2 MHz | |||
#define SPI_CLOCK_6MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 2 MHz | |||
#define SPI_CLOCK_4MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 2 MHz | |||
#elif F_BUS == 2000000 | |||
#define HAS_SPIFIFO | |||
#define SPI_CLOCK_24MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 1 MHz | |||
#define SPI_CLOCK_16MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 1 MHz | |||
#define SPI_CLOCK_12MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 1 MHz | |||
#define SPI_CLOCK_8MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 1 MHz | |||
#define SPI_CLOCK_6MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 1 MHz | |||
#define SPI_CLOCK_4MHz (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 1 MHz | |||
#endif | |||
/* | |||
#! /usr/bin/perl | |||
$clock = 60; | |||
for $i (2, 3, 5, 7) { | |||
for $j (0, 1) { | |||
for $k (2, 4, 6, 8, 16, 32) { | |||
$out = $clock / $i * (1 + $j) / $k; | |||
printf "%0.2f : ", $out; | |||
print "$clock / $i * (1 + $j) / $k = $out\n"; | |||
} | |||
} | |||
} | |||
*/ | |||
// sck = F_BUS / PBR * ((1+DBR)/BR) | |||
// PBR = 2, 3, 5, 7 | |||
// DBR = 0, 1 -- zero preferred |
@@ -41,16 +41,48 @@ static uint8_t analog_reference_internal = 0; | |||
// datasheet says ADC clock should be 2 to 12 MHz for 16 bit mode | |||
// datasheet says ADC clock should be 1 to 18 MHz for 8-12 bit mode | |||
#if F_BUS == 48000000 | |||
#define ADC_CFG1_6MHZ ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) | |||
#define ADC_CFG1_12MHZ ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) | |||
#define ADC_CFG1_24MHZ ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) | |||
#if F_BUS == 60000000 | |||
#define ADC_CFG1_16BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 7.5 MHz | |||
#define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz | |||
#define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz | |||
#define ADC_CFG1_8BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz | |||
#elif F_BUS == 56000000 | |||
#define ADC_CFG1_16BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 7 MHz | |||
#define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 14 MHz | |||
#define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 14 MHz | |||
#define ADC_CFG1_8BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 14 MHz | |||
#elif F_BUS == 48000000 | |||
#define ADC_CFG1_16BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 12 MHz | |||
#define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 12 MHz | |||
#define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 12 MHz | |||
#define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 24 MHz | |||
#elif F_BUS == 40000000 | |||
#define ADC_CFG1_16BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 10 MHz | |||
#define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 10 MHz | |||
#define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 10 MHz | |||
#define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 20 MHz | |||
#elif F_BUS == 36000000 | |||
#define ADC_CFG1_16BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 9 MHz | |||
#define ADC_CFG1_12BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 18 MHz | |||
#define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 18 MHz | |||
#define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 18 MHz | |||
#elif F_BUS == 24000000 | |||
#define ADC_CFG1_6MHZ ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(0) | |||
#define ADC_CFG1_12MHZ ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(0) | |||
#define ADC_CFG1_24MHZ ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) | |||
#define ADC_CFG1_16BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(0) // 12 MHz | |||
#define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(0) // 12 MHz | |||
#define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(0) // 12 MHz | |||
#define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 24 MHz | |||
#elif F_BUS == 4000000 | |||
#define ADC_CFG1_16BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz | |||
#define ADC_CFG1_12BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz | |||
#define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz | |||
#define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz | |||
#elif F_BUS == 2000000 | |||
#define ADC_CFG1_16BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz | |||
#define ADC_CFG1_12BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz | |||
#define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz | |||
#define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz | |||
#else | |||
#error | |||
#error "F_BUS must be 60, 56, 48, 40, 36, 24, 4 or 2 MHz" | |||
#endif | |||
void analog_init(void) | |||
@@ -61,31 +93,31 @@ void analog_init(void) | |||
VREF_SC = 0xE1; // enable 1.2 volt ref | |||
if (analog_config_bits == 8) { | |||
ADC0_CFG1 = ADC_CFG1_24MHZ + ADC_CFG1_MODE(0); | |||
ADC0_CFG1 = ADC_CFG1_8BIT + ADC_CFG1_MODE(0); | |||
ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3); | |||
#if defined(__MK20DX256__) | |||
ADC1_CFG1 = ADC_CFG1_24MHZ + ADC_CFG1_MODE(0); | |||
ADC1_CFG1 = ADC_CFG1_8BIT + ADC_CFG1_MODE(0); | |||
ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3); | |||
#endif | |||
} else if (analog_config_bits == 10) { | |||
ADC0_CFG1 = ADC_CFG1_12MHZ + ADC_CFG1_MODE(2) + ADC_CFG1_ADLSMP; | |||
ADC0_CFG1 = ADC_CFG1_10BIT + ADC_CFG1_MODE(2) + ADC_CFG1_ADLSMP; | |||
ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3); | |||
#if defined(__MK20DX256__) | |||
ADC1_CFG1 = ADC_CFG1_12MHZ + ADC_CFG1_MODE(2) + ADC_CFG1_ADLSMP; | |||
ADC1_CFG1 = ADC_CFG1_10BIT + ADC_CFG1_MODE(2) + ADC_CFG1_ADLSMP; | |||
ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3); | |||
#endif | |||
} else if (analog_config_bits == 12) { | |||
ADC0_CFG1 = ADC_CFG1_12MHZ + ADC_CFG1_MODE(1) + ADC_CFG1_ADLSMP; | |||
ADC0_CFG1 = ADC_CFG1_12BIT + ADC_CFG1_MODE(1) + ADC_CFG1_ADLSMP; | |||
ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2); | |||
#if defined(__MK20DX256__) | |||
ADC1_CFG1 = ADC_CFG1_12MHZ + ADC_CFG1_MODE(1) + ADC_CFG1_ADLSMP; | |||
ADC1_CFG1 = ADC_CFG1_12BIT + ADC_CFG1_MODE(1) + ADC_CFG1_ADLSMP; | |||
ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2); | |||
#endif | |||
} else { | |||
ADC0_CFG1 = ADC_CFG1_12MHZ + ADC_CFG1_MODE(3) + ADC_CFG1_ADLSMP; | |||
ADC0_CFG1 = ADC_CFG1_16BIT + ADC_CFG1_MODE(3) + ADC_CFG1_ADLSMP; | |||
ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2); | |||
#if defined(__MK20DX256__) | |||
ADC1_CFG1 = ADC_CFG1_12MHZ + ADC_CFG1_MODE(3) + ADC_CFG1_ADLSMP; | |||
ADC1_CFG1 = ADC_CFG1_16BIT + ADC_CFG1_MODE(3) + ADC_CFG1_ADLSMP; | |||
ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2); | |||
#endif | |||
} |
@@ -770,18 +770,29 @@ uint32_t micros(void); | |||
static inline void delayMicroseconds(uint32_t) __attribute__((always_inline, unused)); | |||
static inline void delayMicroseconds(uint32_t usec) | |||
{ | |||
#if F_CPU == 144000000 | |||
#if F_CPU == 168000000 | |||
uint32_t n = usec * 56; | |||
#elif F_CPU == 144000000 | |||
uint32_t n = usec * 48; | |||
#elif F_CPU == 120000000 | |||
uint32_t n = usec * 40; | |||
#elif F_CPU == 96000000 | |||
uint32_t n = usec << 5; | |||
#elif F_CPU == 48000000 | |||
uint32_t n = usec << 4; | |||
#elif F_CPU == 24000000 | |||
uint32_t n = usec << 3; | |||
#elif F_CPU == 4000000 | |||
uint32_t n = usec; | |||
#elif F_CPU == 2000000 | |||
uint32_t n = usec >> 1; | |||
#endif | |||
if (usec == 0) return; | |||
asm volatile( | |||
"L_%=_delayMicroseconds:" "\n\t" | |||
#if F_CPU < 10000000 | |||
"nop" "\n\t" | |||
#endif | |||
"subs %0, #1" "\n\t" | |||
"bne L_%=_delayMicroseconds" "\n" | |||
: "+r" (n) : |
@@ -320,12 +320,31 @@ extern void usb_init(void); | |||
// create a default PWM at the same 488.28 Hz as Arduino Uno | |||
#if F_BUS == 48000000 | |||
#if F_BUS == 60000000 | |||
#define DEFAULT_FTM_MOD (61440 - 1) | |||
#define DEFAULT_FTM_PRESCALE 1 | |||
#elif F_BUS == 56000000 | |||
#define DEFAULT_FTM_MOD (57344 - 1) | |||
#define DEFAULT_FTM_PRESCALE 1 | |||
#elif F_BUS == 48000000 | |||
#define DEFAULT_FTM_MOD (49152 - 1) | |||
#define DEFAULT_FTM_PRESCALE 1 | |||
#elif F_BUS == 40000000 | |||
#define DEFAULT_FTM_MOD (40960 - 1) | |||
#define DEFAULT_FTM_PRESCALE 1 | |||
#elif F_BUS == 36000000 | |||
#define DEFAULT_FTM_MOD (36864 - 1) | |||
#define DEFAULT_FTM_PRESCALE 1 | |||
#elif F_BUS == 24000000 | |||
#define DEFAULT_FTM_MOD (49152 - 1) | |||
#define DEFAULT_FTM_PRESCALE 0 | |||
#elif F_BUS == 4000000 | |||
#define DEFAULT_FTM_MOD (8192 - 1) | |||
#define DEFAULT_FTM_PRESCALE 0 | |||
#elif F_BUS == 2000000 | |||
#define DEFAULT_FTM_MOD (4096 - 1) | |||
#define DEFAULT_FTM_PRESCALE 0 | |||
#endif | |||
//void init_pins(void) | |||
@@ -685,14 +704,25 @@ void delay(uint32_t ms) | |||
} | |||
} | |||
#if F_CPU == 144000000 | |||
#define PULSEIN_LOOPS_PER_USEC 21 | |||
// TODO: verify these result in correct timeouts... | |||
#if F_CPU == 168000000 | |||
#define PULSEIN_LOOPS_PER_USEC 25 | |||
#elif F_CPU == 144000000 | |||
#define PULSEIN_LOOPS_PER_USEC 21 | |||
#elif F_CPU == 120000000 | |||
#define PULSEIN_LOOPS_PER_USEC 18 | |||
#elif F_CPU == 96000000 | |||
#define PULSEIN_LOOPS_PER_USEC 14 | |||
#elif F_CPU == 72000000 | |||
#define PULSEIN_LOOPS_PER_USEC 10 | |||
#elif F_CPU == 48000000 | |||
#define PULSEIN_LOOPS_PER_USEC 7 | |||
#elif F_CPU == 24000000 | |||
#define PULSEIN_LOOPS_PER_USEC 4 | |||
#elif F_CPU == 4000000 | |||
#define PULSEIN_LOOPS_PER_USEC 1 | |||
#elif F_CPU == 2000000 | |||
#define PULSEIN_LOOPS_PER_USEC 1 | |||
#endif | |||
@@ -48,8 +48,16 @@ static uint8_t transmit_previous_timeout=0; | |||
// When the PC isn't listening, how long do we wait before discarding data? | |||
#define TX_TIMEOUT_MSEC 30 | |||
#if F_CPU == 96000000 | |||
#if F_CPU == 168000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1100) | |||
#elif F_CPU == 144000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 932) | |||
#elif F_CPU == 120000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 764) | |||
#elif F_CPU == 96000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 596) | |||
#elif F_CPU == 72000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 512) | |||
#elif F_CPU == 48000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 428) | |||
#elif F_CPU == 24000000 | |||
@@ -58,7 +66,6 @@ static uint8_t transmit_previous_timeout=0; | |||
int usb_joystick_send(void) | |||
{ | |||
uint32_t wait_count=0; |
@@ -449,8 +449,16 @@ static uint8_t transmit_previous_timeout=0; | |||
// When the PC isn't listening, how long do we wait before discarding data? | |||
#define TX_TIMEOUT_MSEC 50 | |||
#if F_CPU == 96000000 | |||
#if F_CPU == 168000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1100) | |||
#elif F_CPU == 144000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 932) | |||
#elif F_CPU == 120000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 764) | |||
#elif F_CPU == 96000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 596) | |||
#elif F_CPU == 72000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 512) | |||
#elif F_CPU == 48000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 428) | |||
#elif F_CPU == 24000000 |
@@ -114,8 +114,16 @@ static uint8_t transmit_previous_timeout=0; | |||
// When the PC isn't listening, how long do we wait before discarding data? | |||
#define TX_TIMEOUT_MSEC 30 | |||
#if F_CPU == 96000000 | |||
#if F_CPU == 168000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1100) | |||
#elif F_CPU == 144000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 932) | |||
#elif F_CPU == 120000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 764) | |||
#elif F_CPU == 96000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 596) | |||
#elif F_CPU == 72000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 512) | |||
#elif F_CPU == 48000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 428) | |||
#elif F_CPU == 24000000 |
@@ -138,16 +138,23 @@ void usb_seremu_flush_input(void) | |||
// software. If it's too long, we stall the user's program when no software is running. | |||
#define TX_TIMEOUT_MSEC 30 | |||
#if F_CPU == 144000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 932) | |||
#if F_CPU == 168000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1100) | |||
#elif F_CPU == 144000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 932) | |||
#elif F_CPU == 120000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 764) | |||
#elif F_CPU == 96000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 596) | |||
#elif F_CPU == 72000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 512) | |||
#elif F_CPU == 48000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 428) | |||
#elif F_CPU == 24000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 262) | |||
#endif | |||
// When we've suffered the transmit timeout, don't wait again until the computer | |||
// begins accepting data. If no software is running to receive, we'll just discard | |||
// data as rapidly as Serial.print() can generate it, until there's something to |
@@ -147,10 +147,16 @@ void usb_serial_flush_input(void) | |||
// software. If it's too long, we stall the user's program when no software is running. | |||
#define TX_TIMEOUT_MSEC 70 | |||
#if F_CPU == 144000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 932) | |||
#if F_CPU == 168000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 1100) | |||
#elif F_CPU == 144000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 932) | |||
#elif F_CPU == 120000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 764) | |||
#elif F_CPU == 96000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 596) | |||
#elif F_CPU == 72000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 512) | |||
#elif F_CPU == 48000000 | |||
#define TX_TIMEOUT (TX_TIMEOUT_MSEC * 428) | |||
#elif F_CPU == 24000000 |