Add register definitions for Teensy 3.1

teensy3/mk20dx128.h

@@ -302,7 +302,7 @@ extern "C" {
 #define SIM_SCGC6_DMAMUX		(uint32_t)0x00000002		// DMA Mux Clock Gate Control
 #define SIM_SCGC6_FTFL			(uint32_t)0x00000001		// Flash Memory Clock Gate Control
 #define SIM_SCGC7		*(volatile uint32_t *)0x40048040 // System Clock Gating Control Register 7
-#define SIM_SCGC7_DMA			(uint32_t)0x00000020		// DMA Clock Gate Control
+#define SIM_SCGC7_DMA			(uint32_t)0x00000002		// DMA Clock Gate Control
 #define SIM_CLKDIV1		*(volatile uint32_t *)0x40048044 // System Clock Divider Register 1
 #define SIM_CLKDIV1_OUTDIV1(n)		(uint32_t)(((n) & 0x0F) << 28)	// divide value for the core/system clock
 #define SIM_CLKDIV1_OUTDIV2(n)		(uint32_t)(((n) & 0x0F) << 24)	// divide value for the peripheral clock
@@ -380,7 +380,49 @@ extern "C" {
 // Chapter 17: Miscellaneous Control Module (MCM)
 #define MCM_PLASC		*(volatile uint16_t *)0xE0080008 // Crossbar Switch (AXBS) Slave Configuration
 #define MCM_PLAMC		*(volatile uint16_t *)0xE008000A // Crossbar Switch (AXBS) Master Configuration
-#define MCM_PLACR		*(volatile uint32_t *)0xE008000C // Crossbar Switch (AXBS) Control Register
+#define MCM_PLACR		*(volatile uint32_t *)0xE008000C // Crossbar Switch (AXBS) Control Register (MK20DX128)
+#define MCM_PLACR_ARG			(uint32_t)0x00000200		// Arbitration select, 0=fixed, 1=round-robin
+#define MCM_CR			*(volatile uint32_t *)0xE008000C // RAM arbitration control register (MK20DX256)
+#define MCM_CR_SRAMLWP			(uint32_t)0x40000000		// SRAM_L write protect
+#define MCM_CR_SRAMLAP(n)		(uint32_t)(((n) & 0x03) << 28)	// SRAM_L priority, 0=RR, 1=favor DMA, 2=CPU, 3=DMA
+#define MCM_CR_SRAMUWP			(uint32_t)0x04000000		// SRAM_U write protect
+#define MCM_CR_SRAMUAP(n)		(uint32_t)(((n) & 0x03) << 24)	// SRAM_U priority, 0=RR, 1=favor DMA, 2=CPU, 3=DMA
+
+// Crossbar Switch (AXBS) - only programmable on MK20DX256
+#define AXBS_PRS0		*(volatile uint32_t *)0x40004000 // Priority Registers Slave 0
+#define AXBS_CRS0		*(volatile uint32_t *)0x40004010 // Control Register 0
+#define AXBS_PRS1		*(volatile uint32_t *)0x40004100 // Priority Registers Slave 1
+#define AXBS_CRS1		*(volatile uint32_t *)0x40004110 // Control Register 1
+#define AXBS_PRS2		*(volatile uint32_t *)0x40004200 // Priority Registers Slave 2
+#define AXBS_CRS2		*(volatile uint32_t *)0x40004210 // Control Register 2
+#define AXBS_PRS3		*(volatile uint32_t *)0x40004300 // Priority Registers Slave 3
+#define AXBS_CRS3		*(volatile uint32_t *)0x40004310 // Control Register 3
+#define AXBS_PRS4		*(volatile uint32_t *)0x40004400 // Priority Registers Slave 4
+#define AXBS_CRS4		*(volatile uint32_t *)0x40004410 // Control Register 4
+#define AXBS_PRS5		*(volatile uint32_t *)0x40004500 // Priority Registers Slave 5
+#define AXBS_CRS5		*(volatile uint32_t *)0x40004510 // Control Register 5
+#define AXBS_PRS6		*(volatile uint32_t *)0x40004600 // Priority Registers Slave 6
+#define AXBS_CRS6		*(volatile uint32_t *)0x40004610 // Control Register 6
+#define AXBS_PRS7		*(volatile uint32_t *)0x40004700 // Priority Registers Slave 7
+#define AXBS_CRS7		*(volatile uint32_t *)0x40004710 // Control Register 7
+#define AXBS_MGPCR0		*(volatile uint32_t *)0x40004800 // Master 0 General Purpose Control Register
+#define AXBS_MGPCR1		*(volatile uint32_t *)0x40004900 // Master 1 General Purpose Control Register
+#define AXBS_MGPCR2		*(volatile uint32_t *)0x40004A00 // Master 2 General Purpose Control Register
+#define AXBS_MGPCR3		*(volatile uint32_t *)0x40004B00 // Master 3 General Purpose Control Register
+#define AXBS_MGPCR4		*(volatile uint32_t *)0x40004C00 // Master 4 General Purpose Control Register
+#define AXBS_MGPCR5		*(volatile uint32_t *)0x40004D00 // Master 5 General Purpose Control Register
+#define AXBS_MGPCR6		*(volatile uint32_t *)0x40004E00 // Master 6 General Purpose Control Register
+#define AXBS_MGPCR7		*(volatile uint32_t *)0x40004F00 // Master 7 General Purpose Control Register
+#define AXBS_CRS_READONLY		(uint32_t)0x80000000
+#define AXBS_CRS_HALTLOWPRIORITY	(uint32_t)0x40000000
+#define AXBS_CRS_ARB_FIXED		(uint32_t)0x00000000
+#define AXBS_CRS_ARB_ROUNDROBIN		(uint32_t)0x00010000
+#define AXBS_CRS_PARK_FIXED		(uint32_t)0x00000000
+#define AXBS_CRS_PARK_PREVIOUS		(uint32_t)0x00000010
+#define AXBS_CRS_PARK_NONE		(uint32_t)0x00000020
+#define AXBS_CRS_PARK(n)		(uint32_t)(((n) & 7) << 0)
+
+
 
 // Chapter 20: Direct Memory Access Multiplexer (DMAMUX)
 #define DMAMUX0_CHCFG0		*(volatile uint8_t  *)0x40021000 // Channel Configuration register