#define NVIC_ISER0 (*(volatile uint32_t *)0xE000E100) | #define NVIC_ISER0 (*(volatile uint32_t *)0xE000E100) | ||||
#define NVIC_ISER1 (*(volatile uint32_t *)0xE000E104) | #define NVIC_ISER1 (*(volatile uint32_t *)0xE000E104) | ||||
#define NVIC_ISER2 (*(volatile uint32_t *)0xE000E108) | |||||
#define NVIC_ISER3 (*(volatile uint32_t *)0xE000E10C) | |||||
#define NVIC_ICER0 (*(volatile uint32_t *)0xE000E180) | #define NVIC_ICER0 (*(volatile uint32_t *)0xE000E180) | ||||
#define NVIC_ICER1 (*(volatile uint32_t *)0xE000E184) | #define NVIC_ICER1 (*(volatile uint32_t *)0xE000E184) | ||||
#define NVIC_ICER2 (*(volatile uint32_t *)0xE000E188) | |||||
#define NVIC_ICER3 (*(volatile uint32_t *)0xE000E18C) | |||||
// 0 = highest priority | // 0 = highest priority | ||||
// Cortex-M4: 0,16,32,48,64,80,96,112,128,144,160,176,192,208,224,240 | // Cortex-M4: 0,16,32,48,64,80,96,112,128,144,160,176,192,208,224,240 |