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#define SCB_ID_CLIDR (*(const uint32_t *)0xE000ED78) // Cache Level ID |
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#define SCB_ID_CLIDR (*(const uint32_t *)0xE000ED78) // Cache Level ID |
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#define SCB_ID_CTR (*(const uint32_t *)0xE000ED7C) // Cache Type |
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#define SCB_ID_CTR (*(const uint32_t *)0xE000ED7C) // Cache Type |
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#define SCB_ID_CCSIDR (*(const uint32_t *)0xE000ED80) // Cache Size ID |
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#define SCB_ID_CCSIDR (*(const uint32_t *)0xE000ED80) // Cache Size ID |
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#define SCB_ID_CSSELR (*(const uint32_t *)0xE000ED84) // Cache Size Selection |
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#define SCB_ID_CSSELR (*(volatile uint32_t *)0xE000ED84) // Cache Size Selection |
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#define SCB_CPACR (*(volatile uint32_t *)0xE000ED88) // Coprocessor Access Control |
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#define SCB_CPACR (*(volatile uint32_t *)0xE000ED88) // Coprocessor Access Control |
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#define SCB_FPCCR (*(volatile uint32_t *)0xE000EF34) // FP Context Control |
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#define SCB_FPCCR (*(volatile uint32_t *)0xE000EF34) // FP Context Control |
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#define SCB_FPCAR (*(volatile uint32_t *)0xE000EF38) // FP Context Address |
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#define SCB_FPCAR (*(volatile uint32_t *)0xE000EF38) // FP Context Address |