Update digital & PWM for IMXRT1062 pins

teensy4/core_pins.h

@@ -47,6 +47,399 @@
 #define FALLING			2
 #define RISING			3
 
+
+#if defined(__IMXRT1062__)
+
+#define CORE_NUM_TOTAL_PINS	34
+#define CORE_NUM_DIGITAL	34
+#define CORE_NUM_INTERRUPT	34
+#define CORE_NUM_ANALOG		14
+#define CORE_NUM_PWM		27
+
+#define CORE_PIN0_BIT		3
+#define CORE_PIN1_BIT		2
+#define CORE_PIN2_BIT		4
+#define CORE_PIN3_BIT		5
+#define CORE_PIN4_BIT		6
+#define CORE_PIN5_BIT		8
+#define CORE_PIN6_BIT		10
+#define CORE_PIN7_BIT		17
+#define CORE_PIN8_BIT		16
+#define CORE_PIN9_BIT		11
+#define CORE_PIN10_BIT		0
+#define CORE_PIN11_BIT		2
+#define CORE_PIN12_BIT		1
+#define CORE_PIN13_BIT		3
+#define CORE_PIN14_BIT		18
+#define CORE_PIN15_BIT		19
+#define CORE_PIN16_BIT		23
+#define CORE_PIN17_BIT		22
+#define CORE_PIN18_BIT		17
+#define CORE_PIN19_BIT		16
+#define CORE_PIN20_BIT		26
+#define CORE_PIN21_BIT		27
+#define CORE_PIN22_BIT		24
+#define CORE_PIN23_BIT		25
+#define CORE_PIN24_BIT		12
+#define CORE_PIN25_BIT		13
+#define CORE_PIN26_BIT		30
+#define CORE_PIN27_BIT		31
+#define CORE_PIN28_BIT		18
+#define CORE_PIN29_BIT		31
+#define CORE_PIN30_BIT		24
+#define CORE_PIN31_BIT		23
+#define CORE_PIN32_BIT		12
+#define CORE_PIN33_BIT		7
+
+#define CORE_PIN0_BITMASK	(1<<(CORE_PIN0_BIT))
+#define CORE_PIN1_BITMASK	(1<<(CORE_PIN1_BIT))
+#define CORE_PIN2_BITMASK	(1<<(CORE_PIN2_BIT))
+#define CORE_PIN3_BITMASK	(1<<(CORE_PIN3_BIT))
+#define CORE_PIN4_BITMASK	(1<<(CORE_PIN4_BIT))
+#define CORE_PIN5_BITMASK	(1<<(CORE_PIN5_BIT))
+#define CORE_PIN6_BITMASK	(1<<(CORE_PIN6_BIT))
+#define CORE_PIN7_BITMASK	(1<<(CORE_PIN7_BIT))
+#define CORE_PIN8_BITMASK	(1<<(CORE_PIN8_BIT))
+#define CORE_PIN9_BITMASK	(1<<(CORE_PIN9_BIT))
+#define CORE_PIN10_BITMASK	(1<<(CORE_PIN10_BIT))
+#define CORE_PIN11_BITMASK	(1<<(CORE_PIN11_BIT))
+#define CORE_PIN12_BITMASK	(1<<(CORE_PIN12_BIT))
+#define CORE_PIN13_BITMASK	(1<<(CORE_PIN13_BIT))
+#define CORE_PIN14_BITMASK	(1<<(CORE_PIN14_BIT))
+#define CORE_PIN15_BITMASK	(1<<(CORE_PIN15_BIT))
+#define CORE_PIN16_BITMASK	(1<<(CORE_PIN16_BIT))
+#define CORE_PIN17_BITMASK	(1<<(CORE_PIN17_BIT))
+#define CORE_PIN18_BITMASK	(1<<(CORE_PIN18_BIT))
+#define CORE_PIN19_BITMASK	(1<<(CORE_PIN19_BIT))
+#define CORE_PIN20_BITMASK	(1<<(CORE_PIN20_BIT))
+#define CORE_PIN21_BITMASK	(1<<(CORE_PIN21_BIT))
+#define CORE_PIN22_BITMASK	(1<<(CORE_PIN22_BIT))
+#define CORE_PIN23_BITMASK	(1<<(CORE_PIN23_BIT))
+#define CORE_PIN24_BITMASK	(1<<(CORE_PIN24_BIT))
+#define CORE_PIN25_BITMASK	(1<<(CORE_PIN25_BIT))
+#define CORE_PIN26_BITMASK	(1<<(CORE_PIN26_BIT))
+#define CORE_PIN27_BITMASK	(1<<(CORE_PIN27_BIT))
+#define CORE_PIN28_BITMASK	(1<<(CORE_PIN28_BIT))
+#define CORE_PIN29_BITMASK	(1<<(CORE_PIN29_BIT))
+#define CORE_PIN30_BITMASK	(1<<(CORE_PIN30_BIT))
+#define CORE_PIN31_BITMASK	(1<<(CORE_PIN31_BIT))
+#define CORE_PIN32_BITMASK	(1<<(CORE_PIN32_BIT))
+#define CORE_PIN33_BITMASK	(1<<(CORE_PIN33_BIT))
+
+#define CORE_PIN0_PORTREG	GPIO1_DR
+#define CORE_PIN1_PORTREG	GPIO1_DR
+#define CORE_PIN2_PORTREG	GPIO4_DR
+#define CORE_PIN3_PORTREG	GPIO4_DR
+#define CORE_PIN4_PORTREG	GPIO4_DR
+#define CORE_PIN5_PORTREG	GPIO4_DR
+#define CORE_PIN6_PORTREG	GPIO2_DR
+#define CORE_PIN7_PORTREG	GPIO2_DR
+#define CORE_PIN8_PORTREG	GPIO2_DR
+#define CORE_PIN9_PORTREG	GPIO2_DR
+#define CORE_PIN10_PORTREG	GPIO2_DR
+#define CORE_PIN11_PORTREG	GPIO2_DR
+#define CORE_PIN12_PORTREG	GPIO2_DR
+#define CORE_PIN13_PORTREG	GPIO2_DR
+#define CORE_PIN14_PORTREG	GPIO1_DR
+#define CORE_PIN15_PORTREG	GPIO1_DR
+#define CORE_PIN16_PORTREG	GPIO1_DR
+#define CORE_PIN17_PORTREG	GPIO1_DR
+#define CORE_PIN18_PORTREG	GPIO1_DR
+#define CORE_PIN19_PORTREG	GPIO1_DR
+#define CORE_PIN20_PORTREG	GPIO1_DR
+#define CORE_PIN21_PORTREG	GPIO1_DR
+#define CORE_PIN22_PORTREG	GPIO1_DR
+#define CORE_PIN23_PORTREG	GPIO1_DR
+#define CORE_PIN24_PORTREG	GPIO1_DR
+#define CORE_PIN25_PORTREG	GPIO1_DR
+#define CORE_PIN26_PORTREG	GPIO1_DR
+#define CORE_PIN27_PORTREG	GPIO1_DR
+#define CORE_PIN28_PORTREG	GPIO3_DR
+#define CORE_PIN29_PORTREG	GPIO4_DR
+#define CORE_PIN30_PORTREG	GPIO4_DR
+#define CORE_PIN31_PORTREG	GPIO4_DR
+#define CORE_PIN32_PORTREG	GPIO2_DR
+#define CORE_PIN33_PORTREG	GPIO4_DR
+
+#define CORE_PIN0_PORTSET	GPIO1_DR_SET
+#define CORE_PIN1_PORTSET	GPIO1_DR_SET
+#define CORE_PIN2_PORTSET	GPIO4_DR_SET
+#define CORE_PIN3_PORTSET	GPIO4_DR_SET
+#define CORE_PIN4_PORTSET	GPIO4_DR_SET
+#define CORE_PIN5_PORTSET	GPIO4_DR_SET
+#define CORE_PIN6_PORTSET	GPIO2_DR_SET
+#define CORE_PIN7_PORTSET	GPIO2_DR_SET
+#define CORE_PIN8_PORTSET	GPIO2_DR_SET
+#define CORE_PIN9_PORTSET	GPIO2_DR_SET
+#define CORE_PIN10_PORTSET	GPIO2_DR_SET
+#define CORE_PIN11_PORTSET	GPIO2_DR_SET
+#define CORE_PIN12_PORTSET	GPIO2_DR_SET
+#define CORE_PIN13_PORTSET	GPIO2_DR_SET
+#define CORE_PIN14_PORTSET	GPIO1_DR_SET
+#define CORE_PIN15_PORTSET	GPIO1_DR_SET
+#define CORE_PIN16_PORTSET	GPIO1_DR_SET
+#define CORE_PIN17_PORTSET	GPIO1_DR_SET
+#define CORE_PIN18_PORTSET	GPIO1_DR_SET
+#define CORE_PIN19_PORTSET	GPIO1_DR_SET
+#define CORE_PIN20_PORTSET	GPIO1_DR_SET
+#define CORE_PIN21_PORTSET	GPIO1_DR_SET
+#define CORE_PIN22_PORTSET	GPIO1_DR_SET
+#define CORE_PIN23_PORTSET	GPIO1_DR_SET
+#define CORE_PIN24_PORTSET	GPIO1_DR_SET
+#define CORE_PIN25_PORTSET	GPIO1_DR_SET
+#define CORE_PIN26_PORTSET	GPIO1_DR_SET
+#define CORE_PIN27_PORTSET	GPIO1_DR_SET
+#define CORE_PIN28_PORTSET	GPIO3_DR_SET
+#define CORE_PIN29_PORTSET	GPIO4_DR_SET
+#define CORE_PIN30_PORTSET	GPIO4_DR_SET
+#define CORE_PIN31_PORTSET	GPIO4_DR_SET
+#define CORE_PIN32_PORTSET	GPIO2_DR_SET
+#define CORE_PIN33_PORTSET	GPIO4_DR_SET
+
+#define CORE_PIN0_PORTCLEAR	GPIO1_DR_CLEAR
+#define CORE_PIN1_PORTCLEAR	GPIO1_DR_CLEAR
+#define CORE_PIN2_PORTCLEAR	GPIO4_DR_CLEAR
+#define CORE_PIN3_PORTCLEAR	GPIO4_DR_CLEAR
+#define CORE_PIN4_PORTCLEAR	GPIO4_DR_CLEAR
+#define CORE_PIN5_PORTCLEAR	GPIO4_DR_CLEAR
+#define CORE_PIN6_PORTCLEAR	GPIO2_DR_CLEAR
+#define CORE_PIN7_PORTCLEAR	GPIO2_DR_CLEAR
+#define CORE_PIN8_PORTCLEAR	GPIO2_DR_CLEAR
+#define CORE_PIN9_PORTCLEAR	GPIO2_DR_CLEAR
+#define CORE_PIN10_PORTCLEAR	GPIO2_DR_CLEAR
+#define CORE_PIN11_PORTCLEAR	GPIO2_DR_CLEAR
+#define CORE_PIN12_PORTCLEAR	GPIO2_DR_CLEAR
+#define CORE_PIN13_PORTCLEAR	GPIO2_DR_CLEAR
+#define CORE_PIN14_PORTCLEAR	GPIO1_DR_CLEAR
+#define CORE_PIN15_PORTCLEAR	GPIO1_DR_CLEAR
+#define CORE_PIN16_PORTCLEAR	GPIO1_DR_CLEAR
+#define CORE_PIN17_PORTCLEAR	GPIO1_DR_CLEAR
+#define CORE_PIN18_PORTCLEAR	GPIO1_DR_CLEAR
+#define CORE_PIN19_PORTCLEAR	GPIO1_DR_CLEAR
+#define CORE_PIN20_PORTCLEAR	GPIO1_DR_CLEAR
+#define CORE_PIN21_PORTCLEAR	GPIO1_DR_CLEAR
+#define CORE_PIN22_PORTCLEAR	GPIO1_DR_CLEAR
+#define CORE_PIN23_PORTCLEAR	GPIO1_DR_CLEAR
+#define CORE_PIN24_PORTCLEAR	GPIO1_DR_CLEAR
+#define CORE_PIN25_PORTCLEAR	GPIO1_DR_CLEAR
+#define CORE_PIN26_PORTCLEAR	GPIO1_DR_CLEAR
+#define CORE_PIN27_PORTCLEAR	GPIO1_DR_CLEAR
+#define CORE_PIN28_PORTCLEAR	GPIO3_DR_CLEAR
+#define CORE_PIN29_PORTCLEAR	GPIO4_DR_CLEAR
+#define CORE_PIN30_PORTCLEAR	GPIO4_DR_CLEAR
+#define CORE_PIN31_PORTCLEAR	GPIO4_DR_CLEAR
+#define CORE_PIN32_PORTCLEAR	GPIO2_DR_CLEAR
+#define CORE_PIN33_PORTCLEAR	GPIO4_DR_CLEAR
+
+#define CORE_PIN0_DDRREG	GPIO1_GDIR
+#define CORE_PIN1_DDRREG	GPIO1_GDIR
+#define CORE_PIN2_DDRREG	GPIO4_GDIR
+#define CORE_PIN3_DDRREG	GPIO4_GDIR
+#define CORE_PIN4_DDRREG	GPIO4_GDIR
+#define CORE_PIN5_DDRREG	GPIO4_GDIR
+#define CORE_PIN6_DDRREG	GPIO2_GDIR
+#define CORE_PIN7_DDRREG	GPIO2_GDIR
+#define CORE_PIN8_DDRREG	GPIO2_GDIR
+#define CORE_PIN9_DDRREG	GPIO2_GDIR
+#define CORE_PIN10_DDRREG	GPIO2_GDIR
+#define CORE_PIN11_DDRREG	GPIO2_GDIR
+#define CORE_PIN12_DDRREG	GPIO2_GDIR
+#define CORE_PIN13_DDRREG	GPIO2_GDIR
+#define CORE_PIN14_DDRREG	GPIO1_GDIR
+#define CORE_PIN15_DDRREG	GPIO1_GDIR
+#define CORE_PIN16_DDRREG	GPIO1_GDIR
+#define CORE_PIN17_DDRREG	GPIO1_GDIR
+#define CORE_PIN18_DDRREG	GPIO1_GDIR
+#define CORE_PIN19_DDRREG	GPIO1_GDIR
+#define CORE_PIN20_DDRREG	GPIO1_GDIR
+#define CORE_PIN21_DDRREG	GPIO1_GDIR
+#define CORE_PIN22_DDRREG	GPIO1_GDIR
+#define CORE_PIN23_DDRREG	GPIO1_GDIR
+#define CORE_PIN24_DDRREG	GPIO1_GDIR
+#define CORE_PIN25_DDRREG	GPIO1_GDIR
+#define CORE_PIN26_DDRREG	GPIO1_GDIR
+#define CORE_PIN27_DDRREG	GPIO1_GDIR
+#define CORE_PIN28_DDRREG	GPIO3_GDIR
+#define CORE_PIN29_DDRREG	GPIO4_GDIR
+#define CORE_PIN30_DDRREG	GPIO4_GDIR
+#define CORE_PIN31_DDRREG	GPIO4_GDIR
+#define CORE_PIN32_DDRREG	GPIO2_GDIR
+#define CORE_PIN33_DDRREG	GPIO4_GDIR
+
+#define CORE_PIN0_PINREG	GPIO1_PSR
+#define CORE_PIN1_PINREG	GPIO1_PSR
+#define CORE_PIN2_PINREG	GPIO4_PSR
+#define CORE_PIN3_PINREG	GPIO4_PSR
+#define CORE_PIN4_PINREG	GPIO4_PSR
+#define CORE_PIN5_PINREG	GPIO4_PSR
+#define CORE_PIN6_PINREG	GPIO2_PSR
+#define CORE_PIN7_PINREG	GPIO2_PSR
+#define CORE_PIN8_PINREG	GPIO2_PSR
+#define CORE_PIN9_PINREG	GPIO2_PSR
+#define CORE_PIN10_PINREG	GPIO2_PSR
+#define CORE_PIN11_PINREG	GPIO2_PSR
+#define CORE_PIN12_PINREG	GPIO2_PSR
+#define CORE_PIN13_PINREG	GPIO2_PSR
+#define CORE_PIN14_PINREG	GPIO1_PSR
+#define CORE_PIN15_PINREG	GPIO1_PSR
+#define CORE_PIN16_PINREG	GPIO1_PSR
+#define CORE_PIN17_PINREG	GPIO1_PSR
+#define CORE_PIN18_PINREG	GPIO1_PSR
+#define CORE_PIN19_PINREG	GPIO1_PSR
+#define CORE_PIN20_PINREG	GPIO1_PSR
+#define CORE_PIN21_PINREG	GPIO1_PSR
+#define CORE_PIN22_PINREG	GPIO1_PSR
+#define CORE_PIN23_PINREG	GPIO1_PSR
+#define CORE_PIN24_PINREG	GPIO1_PSR
+#define CORE_PIN25_PINREG	GPIO1_PSR
+#define CORE_PIN26_PINREG	GPIO1_PSR
+#define CORE_PIN27_PINREG	GPIO1_PSR
+#define CORE_PIN28_PINREG	GPIO3_PSR
+#define CORE_PIN29_PINREG	GPIO4_PSR
+#define CORE_PIN30_PINREG	GPIO4_PSR
+#define CORE_PIN31_PINREG	GPIO4_PSR
+#define CORE_PIN32_PINREG	GPIO2_PSR
+#define CORE_PIN33_PINREG	GPIO4_PSR
+
+// mux config registers control which peripheral uses the pin
+#define CORE_PIN0_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03
+#define CORE_PIN1_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02
+#define CORE_PIN2_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04
+#define CORE_PIN3_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05
+#define CORE_PIN4_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06
+#define CORE_PIN5_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08
+#define CORE_PIN6_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10
+#define CORE_PIN7_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01
+#define CORE_PIN8_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00
+#define CORE_PIN9_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11
+#define CORE_PIN10_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00
+#define CORE_PIN11_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02
+#define CORE_PIN12_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01
+#define CORE_PIN13_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03
+#define CORE_PIN14_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02
+#define CORE_PIN15_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03
+#define CORE_PIN16_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07
+#define CORE_PIN17_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06
+#define CORE_PIN18_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01
+#define CORE_PIN19_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00
+#define CORE_PIN20_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10
+#define CORE_PIN21_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11
+#define CORE_PIN22_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08
+#define CORE_PIN23_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09
+#define CORE_PIN24_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12
+#define CORE_PIN25_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13
+#define CORE_PIN26_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14
+#define CORE_PIN27_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15
+#define CORE_PIN28_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32
+#define CORE_PIN29_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31
+#define CORE_PIN30_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24
+#define CORE_PIN31_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23
+#define CORE_PIN32_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12
+#define CORE_PIN33_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07
+
+// pad config registers control pullup/pulldown/keeper, drive strength, etc
+#define CORE_PIN0_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03
+#define CORE_PIN1_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02
+#define CORE_PIN2_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04
+#define CORE_PIN3_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05
+#define CORE_PIN4_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06
+#define CORE_PIN5_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08
+#define CORE_PIN6_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10
+#define CORE_PIN7_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01
+#define CORE_PIN8_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00
+#define CORE_PIN9_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11
+#define CORE_PIN10_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00
+#define CORE_PIN11_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02
+#define CORE_PIN12_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01
+#define CORE_PIN13_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03
+#define CORE_PIN14_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02
+#define CORE_PIN15_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03
+#define CORE_PIN16_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07
+#define CORE_PIN17_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06
+#define CORE_PIN18_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01
+#define CORE_PIN19_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00
+#define CORE_PIN20_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10
+#define CORE_PIN21_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11
+#define CORE_PIN22_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08
+#define CORE_PIN23_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09
+#define CORE_PIN24_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12
+#define CORE_PIN25_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13
+#define CORE_PIN26_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14
+#define CORE_PIN27_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15
+#define CORE_PIN28_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32
+#define CORE_PIN29_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31
+#define CORE_PIN30_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24
+#define CORE_PIN31_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23
+#define CORE_PIN32_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12
+#define CORE_PIN33_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07
+
+#define CORE_LED0_PIN		13
+
+#define CORE_ADC0_PIN		14
+#define CORE_ADC1_PIN		15
+#define CORE_ADC2_PIN		16
+#define CORE_ADC3_PIN		17
+#define CORE_ADC4_PIN		18
+#define CORE_ADC5_PIN		19
+#define CORE_ADC6_PIN		20
+#define CORE_ADC7_PIN		21
+#define CORE_ADC8_PIN		22
+#define CORE_ADC9_PIN		23
+
+#define CORE_RXD0_PIN		0
+#define CORE_TXD0_PIN		1
+#define CORE_RXD1_PIN		6
+#define CORE_TXD1_PIN		7
+#define CORE_RXD2_PIN		15
+#define CORE_TXD2_PIN		14
+#define CORE_RXD3_PIN		16
+#define CORE_TXD3_PIN		17
+#define CORE_RXD4_PIN		21
+#define CORE_TXD4_PIN		20
+#define CORE_RXD5_PIN		25
+#define CORE_TXD5_PIN		24
+#define CORE_RXD6_PIN		28
+#define CORE_TXD6_PIN		29
+
+#define CORE_INT0_PIN		0
+#define CORE_INT1_PIN		1
+#define CORE_INT2_PIN		2
+#define CORE_INT3_PIN		3
+#define CORE_INT4_PIN		4
+#define CORE_INT5_PIN		5
+#define CORE_INT6_PIN		6
+#define CORE_INT7_PIN		7
+#define CORE_INT8_PIN		8
+#define CORE_INT9_PIN		9
+#define CORE_INT10_PIN		10
+#define CORE_INT11_PIN		11
+#define CORE_INT12_PIN		12
+#define CORE_INT13_PIN		13
+#define CORE_INT14_PIN		14
+#define CORE_INT15_PIN		15
+#define CORE_INT16_PIN		16
+#define CORE_INT17_PIN		17
+#define CORE_INT18_PIN		18
+#define CORE_INT19_PIN		19
+#define CORE_INT20_PIN		20
+#define CORE_INT21_PIN		21
+#define CORE_INT22_PIN		22
+#define CORE_INT23_PIN		23
+#define CORE_INT24_PIN		24
+#define CORE_INT25_PIN		25
+#define CORE_INT26_PIN		26
+#define CORE_INT27_PIN		27
+#define CORE_INT28_PIN		28
+#define CORE_INT29_PIN		29
+#define CORE_INT30_PIN		30
+#define CORE_INT31_PIN		31
+#define CORE_INT32_PIN		32
+#define CORE_INT33_PIN		33
+#define CORE_INT_EVERY_PIN	1
+
+
+#elif defined(__IMXRT1052__)
+
 #define CORE_NUM_TOTAL_PINS	34
 #define CORE_NUM_DIGITAL	34
 #define CORE_NUM_INTERRUPT	34
@@ -436,6 +829,7 @@
 #define CORE_INT33_PIN		33
 #define CORE_INT_EVERY_PIN	1
 
+#endif // __IMXRT1052__
 
 #ifdef __cplusplus
 extern "C" {

teensy4/pwm.c

@@ -14,6 +14,47 @@ uint8_t analog_write_res = 8;
 
 #define M(a, b) ((((a) - 1) << 4) | (b))
 
+#if defined(__IMXRT1062__)
+
+const struct pwm_pin_info_struct pwm_pin_info[] = {
+	{1, M(1, 1), 0, 4},  // FlexPWM1_1_X   0  // AD_B0_03
+	{1, M(1, 0), 0, 4},  // FlexPWM1_0_X   1  // AD_B0_02
+	{1, M(4, 2), 1, 1},  // FlexPWM4_2_A   2  // EMC_04
+	{1, M(4, 2), 2, 1},  // FlexPWM4_2_B   3  // EMC_05
+	{1, M(2, 0), 1, 1},  // FlexPWM2_0_A   4  // EMC_06
+	{1, M(2, 1), 1, 1},  // FlexPWM2_1_A   5  // EMC_08
+	{1, M(2, 2), 1, 2},  // FlexPWM2_2_A   6  // B0_10
+	{1, M(1, 3), 2, 6},  // FlexPWM1_3_B   7  // B1_01
+	{1, M(1, 3), 1, 6},  // FlexPWM1_3_A   8  // B1_00
+	{1, M(2, 2), 2, 2},  // FlexPWM2_2_B   9  // B0_11
+	{2, M(1, 0), 0, 1},  // QuadTimer1_0  10  // B0_00
+	{2, M(1, 2), 0, 1},  // QuadTimer1_2  11  // B0_02
+	{2, M(1, 1), 0, 1},  // QuadTimer1_1  12  // B0_01
+	{2, M(2, 0), 0, 1},  // QuadTimer2_0  13  // B0_03
+	{2, M(3, 2), 0, 1},  // QuadTimer3_2  14  // AD_B1_02
+	{2, M(3, 3), 0, 1},  // QuadTimer3_3  15  // AD_B1_03
+	{0, M(1, 0), 0, 0},
+	{0, M(1, 0), 0, 0},
+	{2, M(3, 1), 0, 1},  // QuadTimer3_1  18  // AD_B1_01
+	{2, M(3, 0), 0, 1},  // QuadTimer3_0  19  // AD_B1_00
+	{0, M(1, 0), 0, 0},
+	{0, M(1, 0), 0, 0},
+	{1, M(4, 0), 1, 1},  // FlexPWM4_0_A  22  // AD_B1_08
+	{1, M(4, 1), 1, 1},  // FlexPWM4_1_A  23  // AD_B1_09
+	{1, M(1, 2), 0, 4},  // FlexPWM1_2_X  24  // AD_B0_12
+	{1, M(1, 3), 0, 4},  // FlexPWM1_3_X  25  // AD_B0_13
+	{0, M(1, 0), 0, 0},
+	{0, M(1, 0), 0, 0},
+	{1, M(3, 1), 2, 1},  // FlexPWM3_1_B  28  // EMC_32
+	{1, M(3, 1), 1, 1},  // FlexPWM3_1_A  29  // EMC_31
+	{0, M(1, 0), 0, 0},
+	{0, M(1, 0), 0, 0},
+	{0, M(1, 0), 0, 0},
+	{1, M(2, 0), 2, 1},  // FlexPWM2_0_B  33  // EMC_07
+};
+
+#elif defined(__IMXRT1052__)
+
 const struct pwm_pin_info_struct pwm_pin_info[] = {
 	{1, M(1, 1), 0, 4},  // FlexPWM1_1_X   0  // AD_B0_03
 	{1, M(1, 0), 0, 4},  // FlexPWM1_0_X   1  // AD_B0_02
@@ -51,6 +92,8 @@ const struct pwm_pin_info_struct pwm_pin_info[] = {
 	{1, M(2, 1), 1, 1},  // FlexPWM2_1_A  33  // EMC_08
 };
 
+#endif // __IMXRT1052__
+
 void flexpwmWrite(IMXRT_FLEXPWM_t *p, unsigned int submodule, uint8_t channel, uint16_t val)
 {
 	uint16_t mask = 1 << submodule;