Defs for Teensy 4.1 (work in progress)

teensy4/Makefile

 OPTIONS = -DF_CPU=600000000 -DUSB_SERIAL -DLAYOUT_US_ENGLISH -DUSING_MAKEFILE
 
 # options needed by many Arduino libraries to configure for Teensy 4.0
-OPTIONS += -D__$(MCU)__ -DARDUINO=10810 -DTEENSYDUINO=149
+OPTIONS += -D__$(MCU)__ -DARDUINO=10810 -DTEENSYDUINO=149 -DARDUINO_TEENSY40
 
 # for Cortex M7 with single & double precision FPU
 CPUOPTIONS = -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb

teensy4/core_pins.h

 #define RISING			3
 
 
-#if defined(__IMXRT1062__)
+#if defined(__IMXRT1062__) && defined(ARDUINO_TEENSY40)
 
 #define CORE_NUM_TOTAL_PINS	40
 #define CORE_NUM_DIGITAL	40
 #define CORE_INT39_PIN		39
 #define CORE_INT_EVERY_PIN	1
 
+
+
+
+
+#elif defined(__IMXRT1062__) && defined(ARDUINO_TEENSY41)
+
+#define CORE_NUM_TOTAL_PINS	48
+#define CORE_NUM_DIGITAL	48
+#define CORE_NUM_INTERRUPT	48
+#define CORE_NUM_ANALOG		18
+#define CORE_NUM_PWM		29
+
+#define CORE_PIN0_BIT		3
+#define CORE_PIN1_BIT		2
+#define CORE_PIN2_BIT		4
+#define CORE_PIN3_BIT		5
+#define CORE_PIN4_BIT		6
+#define CORE_PIN5_BIT		8
+#define CORE_PIN6_BIT		10
+#define CORE_PIN7_BIT		17
+#define CORE_PIN8_BIT		16
+#define CORE_PIN9_BIT		11
+#define CORE_PIN10_BIT		0
+#define CORE_PIN11_BIT		2
+#define CORE_PIN12_BIT		1
+#define CORE_PIN13_BIT		3
+#define CORE_PIN14_BIT		18
+#define CORE_PIN15_BIT		19
+#define CORE_PIN16_BIT		23
+#define CORE_PIN17_BIT		22
+#define CORE_PIN18_BIT		17
+#define CORE_PIN19_BIT		16
+#define CORE_PIN20_BIT		26
+#define CORE_PIN21_BIT		27
+#define CORE_PIN22_BIT		24
+#define CORE_PIN23_BIT		25
+#define CORE_PIN24_BIT		12
+#define CORE_PIN25_BIT		13
+#define CORE_PIN26_BIT		30
+#define CORE_PIN27_BIT		31
+#define CORE_PIN28_BIT		18
+#define CORE_PIN29_BIT		31
+#define CORE_PIN30_BIT		23
+#define CORE_PIN31_BIT		22
+#define CORE_PIN32_BIT		12
+#define CORE_PIN33_BIT		7
+#define CORE_PIN34_BIT		29
+#define CORE_PIN35_BIT		28
+#define CORE_PIN36_BIT		18
+#define CORE_PIN37_BIT		19
+#define CORE_PIN38_BIT		28
+#define CORE_PIN39_BIT		29
+#define CORE_PIN40_BIT		20
+#define CORE_PIN41_BIT		21
+#define CORE_PIN42_BIT		15
+#define CORE_PIN43_BIT		14
+#define CORE_PIN44_BIT		13
+#define CORE_PIN45_BIT		12
+#define CORE_PIN46_BIT		17
+#define CORE_PIN47_BIT		16
+
+#define CORE_PIN0_BITMASK	(1<<(CORE_PIN0_BIT))
+#define CORE_PIN1_BITMASK	(1<<(CORE_PIN1_BIT))
+#define CORE_PIN2_BITMASK	(1<<(CORE_PIN2_BIT))
+#define CORE_PIN3_BITMASK	(1<<(CORE_PIN3_BIT))
+#define CORE_PIN4_BITMASK	(1<<(CORE_PIN4_BIT))
+#define CORE_PIN5_BITMASK	(1<<(CORE_PIN5_BIT))
+#define CORE_PIN6_BITMASK	(1<<(CORE_PIN6_BIT))
+#define CORE_PIN7_BITMASK	(1<<(CORE_PIN7_BIT))
+#define CORE_PIN8_BITMASK	(1<<(CORE_PIN8_BIT))
+#define CORE_PIN9_BITMASK	(1<<(CORE_PIN9_BIT))
+#define CORE_PIN10_BITMASK	(1<<(CORE_PIN10_BIT))
+#define CORE_PIN11_BITMASK	(1<<(CORE_PIN11_BIT))
+#define CORE_PIN12_BITMASK	(1<<(CORE_PIN12_BIT))
+#define CORE_PIN13_BITMASK	(1<<(CORE_PIN13_BIT))
+#define CORE_PIN14_BITMASK	(1<<(CORE_PIN14_BIT))
+#define CORE_PIN15_BITMASK	(1<<(CORE_PIN15_BIT))
+#define CORE_PIN16_BITMASK	(1<<(CORE_PIN16_BIT))
+#define CORE_PIN17_BITMASK	(1<<(CORE_PIN17_BIT))
+#define CORE_PIN18_BITMASK	(1<<(CORE_PIN18_BIT))
+#define CORE_PIN19_BITMASK	(1<<(CORE_PIN19_BIT))
+#define CORE_PIN20_BITMASK	(1<<(CORE_PIN20_BIT))
+#define CORE_PIN21_BITMASK	(1<<(CORE_PIN21_BIT))
+#define CORE_PIN22_BITMASK	(1<<(CORE_PIN22_BIT))
+#define CORE_PIN23_BITMASK	(1<<(CORE_PIN23_BIT))
+#define CORE_PIN24_BITMASK	(1<<(CORE_PIN24_BIT))
+#define CORE_PIN25_BITMASK	(1<<(CORE_PIN25_BIT))
+#define CORE_PIN26_BITMASK	(1<<(CORE_PIN26_BIT))
+#define CORE_PIN27_BITMASK	(1<<(CORE_PIN27_BIT))
+#define CORE_PIN28_BITMASK	(1<<(CORE_PIN28_BIT))
+#define CORE_PIN29_BITMASK	(1<<(CORE_PIN29_BIT))
+#define CORE_PIN30_BITMASK	(1<<(CORE_PIN30_BIT))
+#define CORE_PIN31_BITMASK	(1<<(CORE_PIN31_BIT))
+#define CORE_PIN32_BITMASK	(1<<(CORE_PIN32_BIT))
+#define CORE_PIN33_BITMASK	(1<<(CORE_PIN33_BIT))
+#define CORE_PIN34_BITMASK	(1<<(CORE_PIN34_BIT))
+#define CORE_PIN35_BITMASK	(1<<(CORE_PIN35_BIT))
+#define CORE_PIN36_BITMASK	(1<<(CORE_PIN36_BIT))
+#define CORE_PIN37_BITMASK	(1<<(CORE_PIN37_BIT))
+#define CORE_PIN38_BITMASK	(1<<(CORE_PIN38_BIT))
+#define CORE_PIN39_BITMASK	(1<<(CORE_PIN39_BIT))
+#define CORE_PIN40_BITMASK	(1<<(CORE_PIN40_BIT))
+#define CORE_PIN41_BITMASK	(1<<(CORE_PIN41_BIT))
+#define CORE_PIN42_BITMASK	(1<<(CORE_PIN42_BIT))
+#define CORE_PIN43_BITMASK	(1<<(CORE_PIN43_BIT))
+#define CORE_PIN44_BITMASK	(1<<(CORE_PIN44_BIT))
+#define CORE_PIN45_BITMASK	(1<<(CORE_PIN45_BIT))
+#define CORE_PIN46_BITMASK	(1<<(CORE_PIN46_BIT))
+#define CORE_PIN47_BITMASK	(1<<(CORE_PIN47_BIT))
+
+// Fast GPIO
+#define CORE_PIN0_PORTREG	GPIO6_DR
+#define CORE_PIN1_PORTREG	GPIO6_DR
+#define CORE_PIN2_PORTREG	GPIO9_DR
+#define CORE_PIN3_PORTREG	GPIO9_DR
+#define CORE_PIN4_PORTREG	GPIO9_DR
+#define CORE_PIN5_PORTREG	GPIO9_DR
+#define CORE_PIN6_PORTREG	GPIO7_DR
+#define CORE_PIN7_PORTREG	GPIO7_DR
+#define CORE_PIN8_PORTREG	GPIO7_DR
+#define CORE_PIN9_PORTREG	GPIO7_DR
+#define CORE_PIN10_PORTREG	GPIO7_DR
+#define CORE_PIN11_PORTREG	GPIO7_DR
+#define CORE_PIN12_PORTREG	GPIO7_DR
+#define CORE_PIN13_PORTREG	GPIO7_DR
+#define CORE_PIN14_PORTREG	GPIO6_DR
+#define CORE_PIN15_PORTREG	GPIO6_DR
+#define CORE_PIN16_PORTREG	GPIO6_DR
+#define CORE_PIN17_PORTREG	GPIO6_DR
+#define CORE_PIN18_PORTREG	GPIO6_DR
+#define CORE_PIN19_PORTREG	GPIO6_DR
+#define CORE_PIN20_PORTREG	GPIO6_DR
+#define CORE_PIN21_PORTREG	GPIO6_DR
+#define CORE_PIN22_PORTREG	GPIO6_DR
+#define CORE_PIN23_PORTREG	GPIO6_DR
+#define CORE_PIN24_PORTREG	GPIO6_DR
+#define CORE_PIN25_PORTREG	GPIO6_DR
+#define CORE_PIN26_PORTREG	GPIO6_DR
+#define CORE_PIN27_PORTREG	GPIO6_DR
+#define CORE_PIN28_PORTREG	GPIO8_DR
+#define CORE_PIN29_PORTREG	GPIO9_DR
+#define CORE_PIN30_PORTREG	GPIO8_DR
+#define CORE_PIN31_PORTREG	GPIO8_DR
+#define CORE_PIN32_PORTREG	GPIO7_DR
+#define CORE_PIN33_PORTREG	GPIO9_DR
+#define CORE_PIN34_PORTREG	GPIO7_DR
+#define CORE_PIN35_PORTREG	GPIO7_DR
+#define CORE_PIN36_PORTREG	GPIO7_DR
+#define CORE_PIN37_PORTREG	GPIO7_DR
+#define CORE_PIN38_PORTREG	GPIO6_DR
+#define CORE_PIN39_PORTREG	GPIO6_DR
+#define CORE_PIN40_PORTREG	GPIO6_DR
+#define CORE_PIN41_PORTREG	GPIO6_DR
+#define CORE_PIN42_PORTREG	GPIO8_DR
+#define CORE_PIN43_PORTREG	GPIO8_DR
+#define CORE_PIN44_PORTREG	GPIO8_DR
+#define CORE_PIN45_PORTREG	GPIO8_DR
+#define CORE_PIN46_PORTREG	GPIO8_DR
+#define CORE_PIN47_PORTREG	GPIO8_DR
+
+#define CORE_PIN0_PORTSET	GPIO6_DR_SET
+#define CORE_PIN1_PORTSET	GPIO6_DR_SET
+#define CORE_PIN2_PORTSET	GPIO9_DR_SET
+#define CORE_PIN3_PORTSET	GPIO9_DR_SET
+#define CORE_PIN4_PORTSET	GPIO9_DR_SET
+#define CORE_PIN5_PORTSET	GPIO9_DR_SET
+#define CORE_PIN6_PORTSET	GPIO7_DR_SET
+#define CORE_PIN7_PORTSET	GPIO7_DR_SET
+#define CORE_PIN8_PORTSET	GPIO7_DR_SET
+#define CORE_PIN9_PORTSET	GPIO7_DR_SET
+#define CORE_PIN10_PORTSET	GPIO7_DR_SET
+#define CORE_PIN11_PORTSET	GPIO7_DR_SET
+#define CORE_PIN12_PORTSET	GPIO7_DR_SET
+#define CORE_PIN13_PORTSET	GPIO7_DR_SET
+#define CORE_PIN14_PORTSET	GPIO6_DR_SET
+#define CORE_PIN15_PORTSET	GPIO6_DR_SET
+#define CORE_PIN16_PORTSET	GPIO6_DR_SET
+#define CORE_PIN17_PORTSET	GPIO6_DR_SET
+#define CORE_PIN18_PORTSET	GPIO6_DR_SET
+#define CORE_PIN19_PORTSET	GPIO6_DR_SET
+#define CORE_PIN20_PORTSET	GPIO6_DR_SET
+#define CORE_PIN21_PORTSET	GPIO6_DR_SET
+#define CORE_PIN22_PORTSET	GPIO6_DR_SET
+#define CORE_PIN23_PORTSET	GPIO6_DR_SET
+#define CORE_PIN24_PORTSET	GPIO6_DR_SET
+#define CORE_PIN25_PORTSET	GPIO6_DR_SET
+#define CORE_PIN26_PORTSET	GPIO6_DR_SET
+#define CORE_PIN27_PORTSET	GPIO6_DR_SET
+#define CORE_PIN28_PORTSET	GPIO8_DR_SET
+#define CORE_PIN29_PORTSET	GPIO9_DR_SET
+#define CORE_PIN30_PORTSET	GPIO8_DR_SET
+#define CORE_PIN31_PORTSET	GPIO8_DR_SET
+#define CORE_PIN32_PORTSET	GPIO7_DR_SET
+#define CORE_PIN33_PORTSET	GPIO9_DR_SET
+#define CORE_PIN34_PORTSET	GPIO7_DR_SET
+#define CORE_PIN35_PORTSET	GPIO7_DR_SET
+#define CORE_PIN36_PORTSET	GPIO7_DR_SET
+#define CORE_PIN37_PORTSET	GPIO7_DR_SET
+#define CORE_PIN38_PORTSET	GPIO6_DR_SET
+#define CORE_PIN39_PORTSET	GPIO6_DR_SET
+#define CORE_PIN40_PORTSET	GPIO6_DR_SET
+#define CORE_PIN41_PORTSET	GPIO6_DR_SET
+#define CORE_PIN42_PORTSET	GPIO8_DR_SET
+#define CORE_PIN43_PORTSET	GPIO8_DR_SET
+#define CORE_PIN44_PORTSET	GPIO8_DR_SET
+#define CORE_PIN45_PORTSET	GPIO8_DR_SET
+#define CORE_PIN46_PORTSET	GPIO8_DR_SET
+#define CORE_PIN47_PORTSET	GPIO8_DR_SET
+
+#define CORE_PIN0_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN1_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN2_PORTCLEAR	GPIO9_DR_CLEAR
+#define CORE_PIN3_PORTCLEAR	GPIO9_DR_CLEAR
+#define CORE_PIN4_PORTCLEAR	GPIO9_DR_CLEAR
+#define CORE_PIN5_PORTCLEAR	GPIO9_DR_CLEAR
+#define CORE_PIN6_PORTCLEAR	GPIO7_DR_CLEAR
+#define CORE_PIN7_PORTCLEAR	GPIO7_DR_CLEAR
+#define CORE_PIN8_PORTCLEAR	GPIO7_DR_CLEAR
+#define CORE_PIN9_PORTCLEAR	GPIO7_DR_CLEAR
+#define CORE_PIN10_PORTCLEAR	GPIO7_DR_CLEAR
+#define CORE_PIN11_PORTCLEAR	GPIO7_DR_CLEAR
+#define CORE_PIN12_PORTCLEAR	GPIO7_DR_CLEAR
+#define CORE_PIN13_PORTCLEAR	GPIO7_DR_CLEAR
+#define CORE_PIN14_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN15_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN16_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN17_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN18_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN19_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN20_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN21_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN22_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN23_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN24_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN25_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN26_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN27_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN28_PORTCLEAR	GPIO8_DR_CLEAR
+#define CORE_PIN29_PORTCLEAR	GPIO9_DR_CLEAR
+#define CORE_PIN30_PORTCLEAR	GPIO8_DR_CLEAR
+#define CORE_PIN31_PORTCLEAR	GPIO8_DR_CLEAR
+#define CORE_PIN32_PORTCLEAR	GPIO7_DR_CLEAR
+#define CORE_PIN33_PORTCLEAR	GPIO9_DR_CLEAR
+#define CORE_PIN34_PORTCLEAR	GPIO7_DR_CLEAR
+#define CORE_PIN35_PORTCLEAR	GPIO7_DR_CLEAR
+#define CORE_PIN36_PORTCLEAR	GPIO7_DR_CLEAR
+#define CORE_PIN37_PORTCLEAR	GPIO7_DR_CLEAR
+#define CORE_PIN38_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN39_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN40_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN41_PORTCLEAR	GPIO6_DR_CLEAR
+#define CORE_PIN42_PORTCLEAR	GPIO8_DR_CLEAR
+#define CORE_PIN43_PORTCLEAR	GPIO8_DR_CLEAR
+#define CORE_PIN44_PORTCLEAR	GPIO8_DR_CLEAR
+#define CORE_PIN45_PORTCLEAR	GPIO8_DR_CLEAR
+#define CORE_PIN46_PORTCLEAR	GPIO8_DR_CLEAR
+#define CORE_PIN47_PORTCLEAR	GPIO8_DR_CLEAR
+
+#define CORE_PIN0_DDRREG	GPIO6_GDIR
+#define CORE_PIN1_DDRREG	GPIO6_GDIR
+#define CORE_PIN2_DDRREG	GPIO9_GDIR
+#define CORE_PIN3_DDRREG	GPIO9_GDIR
+#define CORE_PIN4_DDRREG	GPIO9_GDIR
+#define CORE_PIN5_DDRREG	GPIO9_GDIR
+#define CORE_PIN6_DDRREG	GPIO7_GDIR
+#define CORE_PIN7_DDRREG	GPIO7_GDIR
+#define CORE_PIN8_DDRREG	GPIO7_GDIR
+#define CORE_PIN9_DDRREG	GPIO7_GDIR
+#define CORE_PIN10_DDRREG	GPIO7_GDIR
+#define CORE_PIN11_DDRREG	GPIO7_GDIR
+#define CORE_PIN12_DDRREG	GPIO7_GDIR
+#define CORE_PIN13_DDRREG	GPIO7_GDIR
+#define CORE_PIN14_DDRREG	GPIO6_GDIR
+#define CORE_PIN15_DDRREG	GPIO6_GDIR
+#define CORE_PIN16_DDRREG	GPIO6_GDIR
+#define CORE_PIN17_DDRREG	GPIO6_GDIR
+#define CORE_PIN18_DDRREG	GPIO6_GDIR
+#define CORE_PIN19_DDRREG	GPIO6_GDIR
+#define CORE_PIN20_DDRREG	GPIO6_GDIR
+#define CORE_PIN21_DDRREG	GPIO6_GDIR
+#define CORE_PIN22_DDRREG	GPIO6_GDIR
+#define CORE_PIN23_DDRREG	GPIO6_GDIR
+#define CORE_PIN24_DDRREG	GPIO6_GDIR
+#define CORE_PIN25_DDRREG	GPIO6_GDIR
+#define CORE_PIN26_DDRREG	GPIO6_GDIR
+#define CORE_PIN27_DDRREG	GPIO6_GDIR
+#define CORE_PIN28_DDRREG	GPIO8_GDIR
+#define CORE_PIN29_DDRREG	GPIO9_GDIR
+#define CORE_PIN30_DDRREG	GPIO8_GDIR
+#define CORE_PIN31_DDRREG	GPIO8_GDIR
+#define CORE_PIN32_DDRREG	GPIO7_GDIR
+#define CORE_PIN33_DDRREG	GPIO9_GDIR
+#define CORE_PIN34_DDRREG	GPIO7_GDIR
+#define CORE_PIN35_DDRREG	GPIO7_GDIR
+#define CORE_PIN36_DDRREG	GPIO7_GDIR
+#define CORE_PIN37_DDRREG	GPIO7_GDIR
+#define CORE_PIN38_DDRREG	GPIO6_GDIR
+#define CORE_PIN39_DDRREG	GPIO6_GDIR
+#define CORE_PIN40_DDRREG	GPIO6_GDIR
+#define CORE_PIN41_DDRREG	GPIO6_GDIR
+#define CORE_PIN42_DDRREG	GPIO8_GDIR
+#define CORE_PIN43_DDRREG	GPIO8_GDIR
+#define CORE_PIN44_DDRREG	GPIO8_GDIR
+#define CORE_PIN45_DDRREG	GPIO8_GDIR
+#define CORE_PIN46_DDRREG	GPIO8_GDIR
+#define CORE_PIN47_DDRREG	GPIO8_GDIR
+
+#define CORE_PIN0_PINREG	GPIO6_PSR
+#define CORE_PIN1_PINREG	GPIO6_PSR
+#define CORE_PIN2_PINREG	GPIO9_PSR
+#define CORE_PIN3_PINREG	GPIO9_PSR
+#define CORE_PIN4_PINREG	GPIO9_PSR
+#define CORE_PIN5_PINREG	GPIO9_PSR
+#define CORE_PIN6_PINREG	GPIO7_PSR
+#define CORE_PIN7_PINREG	GPIO7_PSR
+#define CORE_PIN8_PINREG	GPIO7_PSR
+#define CORE_PIN9_PINREG	GPIO7_PSR
+#define CORE_PIN10_PINREG	GPIO7_PSR
+#define CORE_PIN11_PINREG	GPIO7_PSR
+#define CORE_PIN12_PINREG	GPIO7_PSR
+#define CORE_PIN13_PINREG	GPIO7_PSR
+#define CORE_PIN14_PINREG	GPIO6_PSR
+#define CORE_PIN15_PINREG	GPIO6_PSR
+#define CORE_PIN16_PINREG	GPIO6_PSR
+#define CORE_PIN17_PINREG	GPIO6_PSR
+#define CORE_PIN18_PINREG	GPIO6_PSR
+#define CORE_PIN19_PINREG	GPIO6_PSR
+#define CORE_PIN20_PINREG	GPIO6_PSR
+#define CORE_PIN21_PINREG	GPIO6_PSR
+#define CORE_PIN22_PINREG	GPIO6_PSR
+#define CORE_PIN23_PINREG	GPIO6_PSR
+#define CORE_PIN24_PINREG	GPIO6_PSR
+#define CORE_PIN25_PINREG	GPIO6_PSR
+#define CORE_PIN26_PINREG	GPIO6_PSR
+#define CORE_PIN27_PINREG	GPIO6_PSR
+#define CORE_PIN28_PINREG	GPIO8_PSR
+#define CORE_PIN29_PINREG	GPIO9_PSR
+#define CORE_PIN30_PINREG	GPIO8_PSR
+#define CORE_PIN31_PINREG	GPIO8_PSR
+#define CORE_PIN32_PINREG	GPIO7_PSR
+#define CORE_PIN33_PINREG	GPIO9_PSR
+#define CORE_PIN34_PINREG	GPIO7_PSR
+#define CORE_PIN35_PINREG	GPIO7_PSR
+#define CORE_PIN36_PINREG	GPIO7_PSR
+#define CORE_PIN37_PINREG	GPIO7_PSR
+#define CORE_PIN38_PINREG	GPIO6_PSR
+#define CORE_PIN39_PINREG	GPIO6_PSR
+#define CORE_PIN40_PINREG	GPIO6_PSR
+#define CORE_PIN41_PINREG	GPIO6_PSR
+#define CORE_PIN42_PINREG	GPIO8_PSR
+#define CORE_PIN43_PINREG	GPIO8_PSR
+#define CORE_PIN44_PINREG	GPIO8_PSR
+#define CORE_PIN45_PINREG	GPIO8_PSR
+#define CORE_PIN46_PINREG	GPIO8_PSR
+#define CORE_PIN47_PINREG	GPIO8_PSR
+
+
+
+// mux config registers control which peripheral uses the pin
+#define CORE_PIN0_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03
+#define CORE_PIN1_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02
+#define CORE_PIN2_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04
+#define CORE_PIN3_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05
+#define CORE_PIN4_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06
+#define CORE_PIN5_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08
+#define CORE_PIN6_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10
+#define CORE_PIN7_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01
+#define CORE_PIN8_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00
+#define CORE_PIN9_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11
+#define CORE_PIN10_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00
+#define CORE_PIN11_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02
+#define CORE_PIN12_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01
+#define CORE_PIN13_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03
+#define CORE_PIN14_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02
+#define CORE_PIN15_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03
+#define CORE_PIN16_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07
+#define CORE_PIN17_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06
+#define CORE_PIN18_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01
+#define CORE_PIN19_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00
+#define CORE_PIN20_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10
+#define CORE_PIN21_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11
+#define CORE_PIN22_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08
+#define CORE_PIN23_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09
+#define CORE_PIN24_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12
+#define CORE_PIN25_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13
+#define CORE_PIN26_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14
+#define CORE_PIN27_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15
+#define CORE_PIN28_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32
+#define CORE_PIN29_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31
+#define CORE_PIN30_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37
+#define CORE_PIN31_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36
+#define CORE_PIN32_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12
+#define CORE_PIN33_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07
+#define CORE_PIN34_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13
+#define CORE_PIN35_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12
+#define CORE_PIN36_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02
+#define CORE_PIN37_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03
+#define CORE_PIN38_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12
+#define CORE_PIN39_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13
+#define CORE_PIN40_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04
+#define CORE_PIN41_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05
+#define CORE_PIN42_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03
+#define CORE_PIN43_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02
+#define CORE_PIN44_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01
+#define CORE_PIN45_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00
+#define CORE_PIN46_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05
+#define CORE_PIN47_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04
+
+// pad config registers control pullup/pulldown/keeper, drive strength, etc
+#define CORE_PIN0_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03
+#define CORE_PIN1_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02
+#define CORE_PIN2_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04
+#define CORE_PIN3_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05
+#define CORE_PIN4_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06
+#define CORE_PIN5_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08
+#define CORE_PIN6_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10
+#define CORE_PIN7_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01
+#define CORE_PIN8_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00
+#define CORE_PIN9_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11
+#define CORE_PIN10_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00
+#define CORE_PIN11_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02
+#define CORE_PIN12_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01
+#define CORE_PIN13_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03
+#define CORE_PIN14_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02
+#define CORE_PIN15_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03
+#define CORE_PIN16_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07
+#define CORE_PIN17_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06
+#define CORE_PIN18_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01
+#define CORE_PIN19_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00
+#define CORE_PIN20_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10
+#define CORE_PIN21_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11
+#define CORE_PIN22_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08
+#define CORE_PIN23_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09
+#define CORE_PIN24_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12
+#define CORE_PIN25_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13
+#define CORE_PIN26_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14
+#define CORE_PIN27_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15
+#define CORE_PIN28_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32
+#define CORE_PIN29_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31
+#define CORE_PIN30_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37
+#define CORE_PIN31_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36
+#define CORE_PIN32_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12
+#define CORE_PIN33_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07
+#define CORE_PIN34_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13
+#define CORE_PIN35_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12
+#define CORE_PIN36_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02
+#define CORE_PIN37_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03
+#define CORE_PIN38_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12
+#define CORE_PIN39_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13
+#define CORE_PIN40_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04
+#define CORE_PIN41_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05
+#define CORE_PIN42_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03
+#define CORE_PIN43_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02
+#define CORE_PIN44_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01
+#define CORE_PIN45_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00
+#define CORE_PIN46_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05
+#define CORE_PIN47_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04
+
+#define CORE_LED0_PIN		13
+
+#define CORE_ADC0_PIN		14
+#define CORE_ADC1_PIN		15
+#define CORE_ADC2_PIN		16
+#define CORE_ADC3_PIN		17
+#define CORE_ADC4_PIN		18
+#define CORE_ADC5_PIN		19
+#define CORE_ADC6_PIN		20
+#define CORE_ADC7_PIN		21
+#define CORE_ADC8_PIN		22
+#define CORE_ADC9_PIN		23
+
+#define CORE_RXD0_PIN		0
+#define CORE_TXD0_PIN		1
+#define CORE_RXD1_PIN		7
+#define CORE_TXD1_PIN		8
+#define CORE_RXD2_PIN		15
+#define CORE_TXD2_PIN		14
+#define CORE_RXD3_PIN		16
+#define CORE_TXD3_PIN		17
+#define CORE_RXD4_PIN		21
+#define CORE_TXD4_PIN		20
+#define CORE_RXD5_PIN		25
+#define CORE_TXD5_PIN		24
+#define CORE_RXD6_PIN		28
+#define CORE_TXD6_PIN		29
+#define CORE_RXD7_PIN		34
+#define CORE_TXD7_PIN		35
+
+#define CORE_INT0_PIN		0
+#define CORE_INT1_PIN		1
+#define CORE_INT2_PIN		2
+#define CORE_INT3_PIN		3
+#define CORE_INT4_PIN		4
+#define CORE_INT5_PIN		5
+#define CORE_INT6_PIN		6
+#define CORE_INT7_PIN		7
+#define CORE_INT8_PIN		8
+#define CORE_INT9_PIN		9
+#define CORE_INT10_PIN		10
+#define CORE_INT11_PIN		11
+#define CORE_INT12_PIN		12
+#define CORE_INT13_PIN		13
+#define CORE_INT14_PIN		14
+#define CORE_INT15_PIN		15
+#define CORE_INT16_PIN		16
+#define CORE_INT17_PIN		17
+#define CORE_INT18_PIN		18
+#define CORE_INT19_PIN		19
+#define CORE_INT20_PIN		20
+#define CORE_INT21_PIN		21
+#define CORE_INT22_PIN		22
+#define CORE_INT23_PIN		23
+#define CORE_INT24_PIN		24
+#define CORE_INT25_PIN		25
+#define CORE_INT26_PIN		26
+#define CORE_INT27_PIN		27
+#define CORE_INT28_PIN		28
+#define CORE_INT29_PIN		29
+#define CORE_INT30_PIN		30
+#define CORE_INT31_PIN		31
+#define CORE_INT32_PIN		32
+#define CORE_INT33_PIN		33
+#define CORE_INT34_PIN		34
+#define CORE_INT35_PIN		35
+#define CORE_INT36_PIN		36
+#define CORE_INT37_PIN		37
+#define CORE_INT38_PIN		38
+#define CORE_INT39_PIN		39
+#define CORE_INT40_PIN		40
+#define CORE_INT41_PIN		41
+#define CORE_INT42_PIN		42
+#define CORE_INT43_PIN		43
+#define CORE_INT44_PIN		44
+#define CORE_INT45_PIN		45
+#define CORE_INT46_PIN		46
+#define CORE_INT47_PIN		47
+#define CORE_INT_EVERY_PIN	1
+
+
+
+
+
+
+
 #endif // __IMXRT1062__
 
 #ifdef __cplusplus

teensy4/digital.c

 	{&CORE_PIN31_PORTREG, &CORE_PIN31_CONFIG, &CORE_PIN31_PADCONFIG, CORE_PIN31_BITMASK},
 	{&CORE_PIN32_PORTREG, &CORE_PIN32_CONFIG, &CORE_PIN32_PADCONFIG, CORE_PIN32_BITMASK},
 	{&CORE_PIN33_PORTREG, &CORE_PIN33_CONFIG, &CORE_PIN33_PADCONFIG, CORE_PIN33_BITMASK},
-#if defined(__IMXRT1062__)
 	{&CORE_PIN34_PORTREG, &CORE_PIN34_CONFIG, &CORE_PIN34_PADCONFIG, CORE_PIN34_BITMASK},
 	{&CORE_PIN35_PORTREG, &CORE_PIN35_CONFIG, &CORE_PIN35_PADCONFIG, CORE_PIN35_BITMASK},
 	{&CORE_PIN36_PORTREG, &CORE_PIN36_CONFIG, &CORE_PIN36_PADCONFIG, CORE_PIN36_BITMASK},
 	{&CORE_PIN37_PORTREG, &CORE_PIN37_CONFIG, &CORE_PIN37_PADCONFIG, CORE_PIN37_BITMASK},
 	{&CORE_PIN38_PORTREG, &CORE_PIN38_CONFIG, &CORE_PIN38_PADCONFIG, CORE_PIN38_BITMASK},
 	{&CORE_PIN39_PORTREG, &CORE_PIN39_CONFIG, &CORE_PIN39_PADCONFIG, CORE_PIN39_BITMASK},
+#if defined(ARDUINO_TEENSY41)
+	{&CORE_PIN40_PORTREG, &CORE_PIN40_CONFIG, &CORE_PIN40_PADCONFIG, CORE_PIN40_BITMASK},
+	{&CORE_PIN41_PORTREG, &CORE_PIN41_CONFIG, &CORE_PIN41_PADCONFIG, CORE_PIN41_BITMASK},
+	{&CORE_PIN42_PORTREG, &CORE_PIN42_CONFIG, &CORE_PIN42_PADCONFIG, CORE_PIN42_BITMASK},
+	{&CORE_PIN43_PORTREG, &CORE_PIN43_CONFIG, &CORE_PIN43_PADCONFIG, CORE_PIN43_BITMASK},
+	{&CORE_PIN44_PORTREG, &CORE_PIN44_CONFIG, &CORE_PIN44_PADCONFIG, CORE_PIN44_BITMASK},
+	{&CORE_PIN45_PORTREG, &CORE_PIN45_CONFIG, &CORE_PIN45_PADCONFIG, CORE_PIN45_BITMASK},
+	{&CORE_PIN46_PORTREG, &CORE_PIN46_CONFIG, &CORE_PIN46_PADCONFIG, CORE_PIN46_BITMASK},
+	{&CORE_PIN47_PORTREG, &CORE_PIN47_CONFIG, &CORE_PIN47_PADCONFIG, CORE_PIN47_BITMASK},
 #endif
-	};
+};
 
 void digitalWrite(uint8_t pin, uint8_t val)
 {

teensy4/imxrt1062_t41.ld

+MEMORY
+{
+	ITCM (rwx):  ORIGIN = 0x00000000, LENGTH = 512K
+	DTCM (rwx):  ORIGIN = 0x20000000, LENGTH = 512K
+	RAM (rwx):   ORIGIN = 0x20200000, LENGTH = 512K
+	FLASH (rwx): ORIGIN = 0x60000000, LENGTH = 1984K
+}
+
+ENTRY(ImageVectorTable)
+
+SECTIONS
+{
+	.text.progmem : {
+		KEEP(*(.flashconfig))
+		FILL(0xFF)
+		. = ORIGIN(FLASH) + 0x1000;
+		KEEP(*(.ivt))
+		KEEP(*(.bootdata))
+		KEEP(*(.vectors))
+		KEEP(*(.startup))
+		*(.flashmem*)
+		*(.progmem*)
+                . = ALIGN(4);
+                KEEP(*(.init))
+                __preinit_array_start = .;
+                KEEP (*(.preinit_array))
+                __preinit_array_end = .;
+                __init_array_start = .;
+                KEEP (*(.init_array))
+                __init_array_end = .;
+		. = ALIGN(16);
+	} > FLASH
+
+	.text.itcm : {
+		. = . + 32; /* MPU to trap NULL pointer deref */
+		*(.fastrun)
+		*(.text*)
+		. = ALIGN(16);
+	} > ITCM  AT> FLASH
+
+	.text.itcm.padding (NOLOAD) : {
+		. = ALIGN(32768);
+	} > ITCM
+
+	.data : {
+		*(.rodata*)
+		*(.data*)
+		. = ALIGN(16);
+	} > DTCM  AT> FLASH
+
+	.bss ALIGN(4) : {
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(32);
+		. = . + 32; /* MPU to trap stack overflow */
+	} > DTCM
+
+	.bss.dma (NOLOAD) : {
+		*(.dmabuffers)
+		. = ALIGN(16);
+	} > RAM
+
+	_stext = ADDR(.text.itcm);
+	_etext = ADDR(.text.itcm) + SIZEOF(.text.itcm);
+	_stextload = LOADADDR(.text.itcm);
+
+	_sdata = ADDR(.data);
+	_edata = ADDR(.data) + SIZEOF(.data);
+	_sdataload = LOADADDR(.data);
+
+	_sbss = ADDR(.bss);
+	_ebss = ADDR(.bss) + SIZEOF(.bss);
+
+	_heap_start = ADDR(.bss.dma) + SIZEOF(.bss.dma);
+	_heap_end = ORIGIN(RAM) + LENGTH(RAM);
+
+	_itcm_block_count = (SIZEOF(.text.itcm) + 0x7FFF) >> 15;
+	_flexram_bank_config = 0xAAAAAAAA | ((1 << (_itcm_block_count * 2)) - 1);
+	_estack = ORIGIN(DTCM) + ((16 - _itcm_block_count) << 15);
+
+	_flashimagelen = SIZEOF(.text.progmem) + SIZEOF(.text.itcm) + SIZEOF(.data);
+	_teensy_model_identifier = 0x25;
+
+	.debug_info     0 : { *(.debug_info) }
+	.debug_abbrev   0 : { *(.debug_abbrev) }
+	.debug_line     0 : { *(.debug_line) }
+	.debug_frame    0 : { *(.debug_frame) }
+	.debug_str      0 : { *(.debug_str) }
+	.debug_loc      0 : { *(.debug_loc) }
+
+}

teensy4/usb_desc.c

   // For USB types that don't explicitly define BCD_DEVICE,
   // use the minor version number to help teensy_ports
   // identify which Teensy model is used.
-  #if defined(__IMXRT1062__)
+  #if defined(__IMXRT1062__) && defined(ARDUINO_TEENSY40)
         0x79, 0x02, // Teensy 4.0
+  #elif defined(__IMXRT1062__) && defined(ARDUINO_TEENSY41)
+        0x80, 0x02, // Teensy 4.1
   #else
         0x00, 0x02,
   #endif