Merge pull request #450 from FrankBoesing/patch-2

MPU: Trap not allowed accesses

teensy4/startup.c

 #define MEM_CACHE_WBWA	SCB_MPU_RASR_TEX(1) | SCB_MPU_RASR_C | SCB_MPU_RASR_B
 #define MEM_NOCACHE	SCB_MPU_RASR_TEX(1)
 #define DEV_NOCACHE	SCB_MPU_RASR_TEX(2)
+#define SIZE_32B	(SCB_MPU_RASR_SIZE(4) | SCB_MPU_RASR_ENABLE)
+#define SIZE_64B	(SCB_MPU_RASR_SIZE(5) | SCB_MPU_RASR_ENABLE)
+#define SIZE_128B	(SCB_MPU_RASR_SIZE(6) | SCB_MPU_RASR_ENABLE)
+#define SIZE_256B	(SCB_MPU_RASR_SIZE(7) | SCB_MPU_RASR_ENABLE)
+#define SIZE_512B	(SCB_MPU_RASR_SIZE(8) | SCB_MPU_RASR_ENABLE)
+#define SIZE_1K		(SCB_MPU_RASR_SIZE(9) | SCB_MPU_RASR_ENABLE)
+#define SIZE_2K		(SCB_MPU_RASR_SIZE(10) | SCB_MPU_RASR_ENABLE)
+#define SIZE_4K		(SCB_MPU_RASR_SIZE(11) | SCB_MPU_RASR_ENABLE)
+#define SIZE_8K		(SCB_MPU_RASR_SIZE(12) | SCB_MPU_RASR_ENABLE)
+#define SIZE_16K	(SCB_MPU_RASR_SIZE(13) | SCB_MPU_RASR_ENABLE)
+#define SIZE_32K	(SCB_MPU_RASR_SIZE(14) | SCB_MPU_RASR_ENABLE)
+#define SIZE_64K	(SCB_MPU_RASR_SIZE(15) | SCB_MPU_RASR_ENABLE)
 #define SIZE_128K	(SCB_MPU_RASR_SIZE(16) | SCB_MPU_RASR_ENABLE)
 #define SIZE_256K	(SCB_MPU_RASR_SIZE(17) | SCB_MPU_RASR_ENABLE)
 #define SIZE_512K	(SCB_MPU_RASR_SIZE(18) | SCB_MPU_RASR_ENABLE)
 #define SIZE_16M	(SCB_MPU_RASR_SIZE(23) | SCB_MPU_RASR_ENABLE)
 #define SIZE_32M	(SCB_MPU_RASR_SIZE(24) | SCB_MPU_RASR_ENABLE)
 #define SIZE_64M	(SCB_MPU_RASR_SIZE(25) | SCB_MPU_RASR_ENABLE)
-#define SIZE_256M	(SCB_MPU_RASR_SIZE(26) | SCB_MPU_RASR_ENABLE)
+#define SIZE_128M	(SCB_MPU_RASR_SIZE(26) | SCB_MPU_RASR_ENABLE)
+#define SIZE_256M	(SCB_MPU_RASR_SIZE(27) | SCB_MPU_RASR_ENABLE)
+#define SIZE_512M	(SCB_MPU_RASR_SIZE(28) | SCB_MPU_RASR_ENABLE)
+#define SIZE_1G		(SCB_MPU_RASR_SIZE(29) | SCB_MPU_RASR_ENABLE)
+#define SIZE_2G		(SCB_MPU_RASR_SIZE(30) | SCB_MPU_RASR_ENABLE)
+#define SIZE_4G		(SCB_MPU_RASR_SIZE(31) | SCB_MPU_RASR_ENABLE)
 #define REGION(n)	(SCB_MPU_RBAR_REGION(n) | SCB_MPU_RBAR_VALID)
 
 FLASHMEM void configure_cache(void)
 
 	SCB_MPU_CTRL = 0; // turn off MPU
 
-	SCB_MPU_RBAR = 0x00000000 | REGION(0); // ITCM
+	uint32_t i = 0;
+	SCB_MPU_RBAR = 0x00000000 | REGION(i++); //https://developer.arm.com/docs/146793866/10/why-does-the-cortex-m7-initiate-axim-read-accesses-to-memory-addresses-that-do-not-fall-under-a-defined-mpu-region
+	SCB_MPU_RASR = SCB_MPU_RASR_TEX(0) | NOACCESS | NOEXEC | SIZE_4G;
+	
+	SCB_MPU_RBAR = 0x00000000 | REGION(i++); // ITCM
 	SCB_MPU_RASR = MEM_NOCACHE | READWRITE | SIZE_512K;
+	
+	SCB_MPU_RBAR = 0x00000000 | REGION(i++); // trap NULL pointer deref
+	SCB_MPU_RASR =  DEV_NOCACHE | NOACCESS | SIZE_32B;
 
-	SCB_MPU_RBAR = 0x00200000 | REGION(1); // Boot ROM
+	SCB_MPU_RBAR = 0x00200000 | REGION(i++); // Boot ROM
 	SCB_MPU_RASR = MEM_CACHE_WT | READONLY | SIZE_128K;
 
-	SCB_MPU_RBAR = 0x20000000 | REGION(2); // DTCM
+	SCB_MPU_RBAR = 0x20000000 | REGION(i++); // DTCM
 	SCB_MPU_RASR = MEM_NOCACHE | READWRITE | NOEXEC | SIZE_512K;
+	
+	SCB_MPU_RBAR = ((uint32_t)&_ebss) | REGION(i++); // trap stack overflow
+	SCB_MPU_RASR = SCB_MPU_RASR_TEX(0) | NOACCESS | NOEXEC | SIZE_32B;
 
-	SCB_MPU_RBAR = 0x20200000 | REGION(3); // RAM (AXI bus)
+	SCB_MPU_RBAR = 0x20200000 | REGION(i++); // RAM (AXI bus)
 	SCB_MPU_RASR = MEM_CACHE_WBWA | READWRITE | NOEXEC | SIZE_1M;
 
-	SCB_MPU_RBAR = 0x40000000 | REGION(4); // Peripherals
+	SCB_MPU_RBAR = 0x40000000 | REGION(i++); // Peripherals
 	SCB_MPU_RASR = DEV_NOCACHE | READWRITE | NOEXEC | SIZE_64M;
 
-	SCB_MPU_RBAR = 0x60000000 | REGION(5); // QSPI Flash
+	SCB_MPU_RBAR = 0x60000000 | REGION(i++); // QSPI Flash
 	SCB_MPU_RASR = MEM_CACHE_WBWA | READONLY | SIZE_16M;
 
-	SCB_MPU_RBAR = 0x70000000 | REGION(6); // FlexSPI2
+	SCB_MPU_RBAR = 0x70000000 | REGION(i++); // FlexSPI2
 	SCB_MPU_RASR = MEM_CACHE_WBWA | READONLY | SIZE_256M;
 
-	SCB_MPU_RBAR = 0x70000000 | REGION(7); // FlexSPI2
+	SCB_MPU_RBAR = 0x70000000 | REGION(i++); // FlexSPI2
 	SCB_MPU_RASR = MEM_CACHE_WBWA | READWRITE | SIZE_16M;
 
-	// TODO: 32 byte sub-region at 0x00000000 with NOACCESS, to trap NULL pointer deref
 	// TODO: protect access to power supply config
-	// TODO: 32 byte sub-region at end of .bss section with NOACCESS, to trap stack overflow
 
 	SCB_MPU_CTRL = SCB_MPU_CTRL_ENABLE;
 
 	SCB_CCR |= (SCB_CCR_IC | SCB_CCR_DC);
 }
 
-
 FLASHMEM void usb_pll_start()
 {
 	while (1) {