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#define CMP_MUXCR_PSTM (uint8_t)0x40 // Pass Through Mode Enable |
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#define CMP_MUXCR_PSTM (uint8_t)0x40 // Pass Through Mode Enable |
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#define CMP_MUXCR_PSEL(n) (uint8_t)(((n) & 0x07) << 3) // Plus Input Mux Control |
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#define CMP_MUXCR_PSEL(n) (uint8_t)(((n) & 0x07) << 3) // Plus Input Mux Control |
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#define CMP_MUXCR_MSEL(n) (uint8_t)(((n) & 0x07) << 0) // Minus Input Mux Control |
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#define CMP_MUXCR_MSEL(n) (uint8_t)(((n) & 0x07) << 0) // Minus Input Mux Control |
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#if defined(KINETISK) |
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#define CMP1_CR0 (*(volatile uint8_t *)0x40073008) // CMP Control Register 0 |
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#define CMP1_CR0 (*(volatile uint8_t *)0x40073008) // CMP Control Register 0 |
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#define CMP1_CR1 (*(volatile uint8_t *)0x40073009) // CMP Control Register 1 |
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#define CMP1_CR1 (*(volatile uint8_t *)0x40073009) // CMP Control Register 1 |
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#define CMP1_FPR (*(volatile uint8_t *)0x4007300A) // CMP Filter Period Register |
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#define CMP1_FPR (*(volatile uint8_t *)0x4007300A) // CMP Filter Period Register |
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#define CMP3_SCR (*(volatile uint8_t *)0x4007301B) // CMP Status and Control Register |
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#define CMP3_SCR (*(volatile uint8_t *)0x4007301B) // CMP Status and Control Register |
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#define CMP3_DACCR (*(volatile uint8_t *)0x4007301C) // DAC Control Register |
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#define CMP3_DACCR (*(volatile uint8_t *)0x4007301C) // DAC Control Register |
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#define CMP3_MUXCR (*(volatile uint8_t *)0x4007301D) // MUX Control Register |
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#define CMP3_MUXCR (*(volatile uint8_t *)0x4007301D) // MUX Control Register |
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#endif |
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// Analog Voltage Reference (VREFV1) |
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// Analog Voltage Reference (VREFV1) |
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#define VREF_TRM (*(volatile uint8_t *)0x40074000) // VREF Trim Register |
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#define VREF_TRM (*(volatile uint8_t *)0x40074000) // VREF Trim Register |