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@@ -31,6 +31,9 @@ |
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#include "kinetis.h" |
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#include <avr/eeprom.h> |
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//#include "HardwareSerial.h" |
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#if F_CPU > 120000000 && defined(__MK66FX1M0__) |
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#include "core_pins.h" // delayMicroseconds() |
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#endif |
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#if defined(__MK20DX128__) || defined(__MK20DX256__) |
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@@ -183,18 +186,68 @@ static void flexram_wait(void) |
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} |
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} |
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#if F_CPU > 120000000 && defined(__MK66FX1M0__) |
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static volatile uint16_t c_intrestore = 0; |
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void c_enable_irq( void ); |
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void c_disable_irq( void ); |
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static __inline__ uint32_t __get_primask(void) \ |
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{ uint32_t primask = 0; \ |
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__asm__ volatile ("MRS %[result], PRIMASK\n\t":[result]"=r"(primask)::); \ |
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return primask; } // returns 0 if interrupts enabled, 1 if disabled |
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void c_enable_irq( void ){ |
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if ( c_intrestore ) { |
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c_intrestore =0; |
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__enable_irq( ); |
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} |
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} |
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void c_disable_irq( void ){ |
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if ( !__get_primask() ) { // Returns 0 if they are enabled, or non-zero if disabled |
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__disable_irq( ); |
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c_intrestore = 1; |
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} |
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} |
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static volatile uint8_t restore_hsrun = 0; |
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static void hsrun_off(void) |
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{ |
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if (SMC_PMSTAT == SMC_PMSTAT_HSRUN) { |
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c_disable_irq( ); // Turn off interrupts for the DURATION !!!! |
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SMC_PMCTRL = SMC_PMCTRL_RUNM(0); // exit HSRUN mode |
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while (SMC_PMSTAT == SMC_PMSTAT_HSRUN) delayMicroseconds(2); // wait for !HSRUN |
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delayMicroseconds(100); |
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restore_hsrun = 1; |
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} |
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} |
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static void hsrun_on(void) |
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{ |
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if (restore_hsrun) { |
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SMC_PMCTRL = SMC_PMCTRL_RUNM(3); // enter HSRUN mode |
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while (SMC_PMSTAT != SMC_PMSTAT_HSRUN) delayMicroseconds(2);; // wait for HSRUN |
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restore_hsrun = 0; |
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c_enable_irq( ); // Restore interrupts only when HSRUN restored } |
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} |
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} |
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#else |
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#define hsrun_off() |
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#define hsrun_on() |
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#endif |
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void eeprom_write_byte(uint8_t *addr, uint8_t value) |
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{ |
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uint32_t offset = (uint32_t)addr; |
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if (offset >= EEPROM_SIZE) return; |
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if (!(FTFL_FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize(); |
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hsrun_off(); |
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if (FlexRAM[offset] != value) { |
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uint8_t stat = FTFL_FSTAT & 0x70; |
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if (stat) FTFL_FSTAT = stat; |
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FlexRAM[offset] = value; |
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flexram_wait(); |
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} |
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hsrun_on(); |
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} |
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void eeprom_write_word(uint16_t *addr, uint16_t value) |
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@@ -203,6 +256,7 @@ void eeprom_write_word(uint16_t *addr, uint16_t value) |
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if (offset >= EEPROM_SIZE-1) return; |
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if (!(FTFL_FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize(); |
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hsrun_off(); |
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#ifdef HANDLE_UNALIGNED_WRITES |
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if ((offset & 1) == 0) { |
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#endif |
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@@ -228,6 +282,7 @@ void eeprom_write_word(uint16_t *addr, uint16_t value) |
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} |
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} |
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#endif |
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hsrun_on(); |
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} |
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void eeprom_write_dword(uint32_t *addr, uint32_t value) |
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@@ -236,6 +291,7 @@ void eeprom_write_dword(uint32_t *addr, uint32_t value) |
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if (offset >= EEPROM_SIZE-3) return; |
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if (!(FTFL_FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize(); |
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hsrun_off(); |
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#ifdef HANDLE_UNALIGNED_WRITES |
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switch (offset & 3) { |
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case 0: |
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@@ -246,6 +302,7 @@ void eeprom_write_dword(uint32_t *addr, uint32_t value) |
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*(uint32_t *)(&FlexRAM[offset]) = value; |
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flexram_wait(); |
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} |
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hsrun_on(); |
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return; |
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#ifdef HANDLE_UNALIGNED_WRITES |
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case 2: |
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@@ -261,6 +318,7 @@ void eeprom_write_dword(uint32_t *addr, uint32_t value) |
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*(uint16_t *)(&FlexRAM[offset + 2]) = value >> 16; |
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flexram_wait(); |
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} |
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hsrun_on(); |
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return; |
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default: |
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if (FlexRAM[offset] != value) { |
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@@ -283,6 +341,7 @@ void eeprom_write_dword(uint32_t *addr, uint32_t value) |
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} |
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} |
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#endif |
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hsrun_on(); |
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} |
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void eeprom_write_block(const void *buf, void *addr, uint32_t len) |
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@@ -292,6 +351,7 @@ void eeprom_write_block(const void *buf, void *addr, uint32_t len) |
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if (offset >= EEPROM_SIZE) return; |
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if (!(FTFL_FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize(); |
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hsrun_off(); |
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if (len >= EEPROM_SIZE) len = EEPROM_SIZE; |
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if (offset + len >= EEPROM_SIZE) len = EEPROM_SIZE - offset; |
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while (len > 0) { |
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@@ -337,6 +397,7 @@ void eeprom_write_block(const void *buf, void *addr, uint32_t len) |
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len--; |
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} |
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} |
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hsrun_on(); |
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} |
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/* |