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#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE ((uint32_t)(1<<8)) |
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#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE ((uint32_t)(1<<8)) |
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#define ADC_ETC_CTRL_TRIG_ENABLE(n) ((uint32_t)(((n) & 0xff) << 0)) |
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#define ADC_ETC_CTRL_TRIG_ENABLE(n) ((uint32_t)(((n) & 0xff) << 0)) |
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#define ADC_ETC_DONE0_1_IRQ_TRIG_DONE1(n) ((uint32_t)(1<<(16 + ((n) &0x7))) |
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#define ADC_ETC_DONE0_1_IRQ_TRIG_DONE1(n) ((uint32_t)(1<<(16 + ((n) &0x7)))) |
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#define ADC_ETC_DONE0_1_IRQ_TRIG_DONE0(n) ((uint32_t)(1<<((n) &0x7))) |
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#define ADC_ETC_DONE0_1_IRQ_TRIG_DONE0(n) ((uint32_t)(1<<((n) &0x7))) |
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG_ERR(n) ((uint32_t)(1<<(16 + ((n) &0x7))) |
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG_ERR(n) ((uint32_t)(1<<(16 + ((n) &0x7)))) |
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG_DONE2(n) ((uint32_t)(1<<((n) &0x7))) |
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#define ADC_ETC_DONE2_ERR_IRQ_TRIG_DONE2(n) ((uint32_t)(1<<((n) &0x7))) |
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#define ADC_ETC_DMA_CTRL_TRIQ_REQ(n) ((uint32_t)(1<<(16 + ((n) &0x7))) |
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#define ADC_ETC_DMA_CTRL_TRIQ_REQ(n) ((uint32_t)(1<<(16 + ((n) &0x7)))) |
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#define ADC_ETC_DMA_CTRL_TRIQ_ENABLE(n) ((uint32_t)(1<<((n) &0x7))) |
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#define ADC_ETC_DMA_CTRL_TRIQ_ENABLE(n) ((uint32_t)(1<<((n) &0x7))) |
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// For each TRIG elements in array |
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// For each TRIG elements in array |
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#define ADC_ETC_TRIG_CHAIN_HWTS0(n) ((uint32_t)(((n) & 0xff) << 4)) |
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#define ADC_ETC_TRIG_CHAIN_HWTS0(n) ((uint32_t)(((n) & 0xff) << 4)) |
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#define ADC_ETC_TRIG_CHAIN_CSEL0(n) ((uint32_t)(((n) & 0x0f) << 0)) |
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#define ADC_ETC_TRIG_CHAIN_CSEL0(n) ((uint32_t)(((n) & 0x0f) << 0)) |
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#define ADC_ETC_TRIG_RESULT_DATA1(n) ((uint32_t)(((n) & 0xff) << 16)) |
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#define ADC_ETC_TRIG_RESULT_DATA0(n) ((uint32_t)(((n) & 0xff) << 0)) |
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#define ADC_ETC_TRIG_RESULT_DATA1(n) ((uint32_t)(((n) & 0xfff) << 16)) |
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#define ADC_ETC_TRIG_RESULT_DATA0(n) ((uint32_t)(((n) & 0xfff) << 0)) |
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// 16.7: page 640 |
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// 16.7: page 640 |
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#define IMXRT_AIPSTZ1 (*(IMXRT_REGISTER32_t *)0x4007C000) |
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#define IMXRT_AIPSTZ1 (*(IMXRT_REGISTER32_t *)0x4007C000) |