Browse Source

check SIM_SCGC1_UART4 in serial5_set_tx

teensy4-core
thewknd 7 years ago
parent
commit
a3b53f21a0
1 changed files with 2 additions and 2 deletions
  1. +2
    -2
      teensy3/serial5.c

+ 2
- 2
teensy3/serial5.c View File

static volatile uint8_t rx_buffer_tail = 0; static volatile uint8_t rx_buffer_tail = 0;
#endif #endif


static uint8_t tx_pin_num = 34;
static uint8_t tx_pin_num = 33;


// UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS // UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS
// UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer // UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer


if (opendrain) pin |= 128; if (opendrain) pin |= 128;
if (pin == tx_pin_num) return; if (pin == tx_pin_num) return;
if ((SIM_SCGC4 & SIM_SCGC4_UART2)) {
if ((SIM_SCGC1 & SIM_SCGC1_UART4)) {
switch (tx_pin_num & 127) { switch (tx_pin_num & 127) {
case 33: CORE_PIN33_CONFIG = 0; break; // PTE24 case 33: CORE_PIN33_CONFIG = 0; break; // PTE24
} }

Loading…
Cancel
Save