Defs for MK66FX1M0

teensy3/WProgram.h

@@ -60,7 +60,7 @@ long map(long, long, long, long, long);
 
 
 // Fast memcpy
-#if defined(__MK20DX128__) || defined(__MK20DX256__)
+#if defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK66FX1M0__)
 #ifdef __cplusplus
 extern "C" {
 extern void *memcpy (void *dst, const void *src, size_t count);

teensy3/analog.c

@@ -516,7 +516,20 @@ void analogWriteDAC0(int val)
 }
 
 
-
+#if defined(__MK66FX1M0__)
+void analogWriteDAC1(int val)
+{
+	SIM_SCGC2 |= SIM_SCGC2_DAC1;
+	if (analog_reference_internal) {
+		DAC1_C0 = DAC_C0_DACEN;  // 1.2V ref is DACREF_1
+	} else {
+		DAC1_C0 = DAC_C0_DACEN | DAC_C0_DACRFS; // 3.3V VDDA is DACREF_2
+	}
+	if (val < 0) val = 0;  // TODO: saturate instruction?
+	else if (val > 4095) val = 4095;
+	*(int16_t *)&(DAC1_DAT0L) = val;
+}
+#endif
 
 
 

teensy3/avr_emulation.h

@@ -1479,14 +1479,23 @@ extern SREGemulation SREG;
 		// 84062840
 		// 322111 
 		// 17395173
+#if defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK66FX1M0__)
+
 #if defined(__MK20DX128__) || defined(__MK20DX256__)
 #define EIMSK_pA 0x01000018 // pins 3, 4, 24
 #define EIMSK_pB 0x020F0003 // pins 0, 1, 16-19, 25
 #define EIMSK_pC 0x78C0BE00 // pins 9-13, 15, 22, 23, 27-30
 #define EIMSK_pD 0x003041E4 // pins 2, 5-8, 14, 20, 21
 #define EIMSK_pE 0x84000000 // pins 26, 31
+#elif defined(__MK66FX1M0__)
+#define EIMSK_pA 0x1E000018 // pins 3, 4, 25-28
+#define EIMSK_pB 0xE00F0003 // pins 0, 1, 16-19, 29-31
+#define EIMSK_pC 0x00C0BE00 // pins 9-13, 15, 22, 23
+#define EIMSK_pD 0x003041E4 // pins 2, 5-8, 14, 20, 21
+#define EIMSK_pE 0x01000000 // pins 24
+#endif
 
-class EIMSKemulation  // used by Adafruit_nRF8001
+class EIMSKemulation  // used by Adafruit_nRF8001 (only supports INT for pins 0 to 31)
 {
 public:
 	operator int () const __attribute__((always_inline)) {

teensy3/core_pins.h

@@ -99,7 +99,7 @@
 #define CORE_NUM_INTERRUPT      34
 #define CORE_NUM_ANALOG         14
 #define CORE_NUM_PWM            10
-#elif defined(__MK20DX256__) || defined(__MK66FX1M0__)
+#elif defined(__MK20DX256__)
 #define CORE_NUM_TOTAL_PINS     34
 #define CORE_NUM_DIGITAL        34
 #define CORE_NUM_INTERRUPT      34
@@ -111,9 +111,15 @@
 #define CORE_NUM_INTERRUPT      24  // really only 18, but 6 "holes"
 #define CORE_NUM_ANALOG         13
 #define CORE_NUM_PWM            10
+#elif defined(__MK66FX1M0__)
+#define CORE_NUM_TOTAL_PINS     40
+#define CORE_NUM_DIGITAL        40
+#define CORE_NUM_INTERRUPT      40
+#define CORE_NUM_ANALOG         23
+#define CORE_NUM_PWM            20
 #endif
 
-#if defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK66FX1M0__)
+#if defined(__MK20DX128__) || defined(__MK20DX256__)
 
 #define CORE_PIN0_BIT		16
 #define CORE_PIN1_BIT		17
@@ -721,6 +727,411 @@
 #define CORE_INT23_PIN		23
 
 
+#elif defined(__MK66FX1M0__)
+
+#define CORE_PIN0_BIT		16
+#define CORE_PIN1_BIT		17
+#define CORE_PIN2_BIT		0
+#define CORE_PIN3_BIT		12
+#define CORE_PIN4_BIT		13
+#define CORE_PIN5_BIT		7
+#define CORE_PIN6_BIT		4
+#define CORE_PIN7_BIT		2
+#define CORE_PIN8_BIT		3
+#define CORE_PIN9_BIT		3
+#define CORE_PIN10_BIT		4
+#define CORE_PIN11_BIT		6
+#define CORE_PIN12_BIT		7
+#define CORE_PIN13_BIT		5
+#define CORE_PIN14_BIT		1
+#define CORE_PIN15_BIT		0
+#define CORE_PIN16_BIT		0
+#define CORE_PIN17_BIT		1
+#define CORE_PIN18_BIT		3
+#define CORE_PIN19_BIT		2
+#define CORE_PIN20_BIT		5
+#define CORE_PIN21_BIT		6
+#define CORE_PIN22_BIT		1
+#define CORE_PIN23_BIT		2
+#define CORE_PIN24_BIT		26
+#define CORE_PIN25_BIT		5
+#define CORE_PIN26_BIT		14
+#define CORE_PIN27_BIT		15
+#define CORE_PIN28_BIT		16
+#define CORE_PIN29_BIT		18
+#define CORE_PIN30_BIT		19
+#define CORE_PIN31_BIT		10
+#define CORE_PIN32_BIT		11
+#define CORE_PIN33_BIT		24
+#define CORE_PIN34_BIT		25
+#define CORE_PIN35_BIT		8
+#define CORE_PIN36_BIT		9
+#define CORE_PIN37_BIT		10
+#define CORE_PIN38_BIT		11
+#define CORE_PIN39_BIT		17
+
+#define CORE_PIN0_BITMASK	(1<<(CORE_PIN0_BIT))
+#define CORE_PIN1_BITMASK	(1<<(CORE_PIN1_BIT))
+#define CORE_PIN2_BITMASK	(1<<(CORE_PIN2_BIT))
+#define CORE_PIN3_BITMASK	(1<<(CORE_PIN3_BIT))
+#define CORE_PIN4_BITMASK	(1<<(CORE_PIN4_BIT))
+#define CORE_PIN5_BITMASK	(1<<(CORE_PIN5_BIT))
+#define CORE_PIN6_BITMASK	(1<<(CORE_PIN6_BIT))
+#define CORE_PIN7_BITMASK	(1<<(CORE_PIN7_BIT))
+#define CORE_PIN8_BITMASK	(1<<(CORE_PIN8_BIT))
+#define CORE_PIN9_BITMASK	(1<<(CORE_PIN9_BIT))
+#define CORE_PIN10_BITMASK	(1<<(CORE_PIN10_BIT))
+#define CORE_PIN11_BITMASK	(1<<(CORE_PIN11_BIT))
+#define CORE_PIN12_BITMASK	(1<<(CORE_PIN12_BIT))
+#define CORE_PIN13_BITMASK	(1<<(CORE_PIN13_BIT))
+#define CORE_PIN14_BITMASK	(1<<(CORE_PIN14_BIT))
+#define CORE_PIN15_BITMASK	(1<<(CORE_PIN15_BIT))
+#define CORE_PIN16_BITMASK	(1<<(CORE_PIN16_BIT))
+#define CORE_PIN17_BITMASK	(1<<(CORE_PIN17_BIT))
+#define CORE_PIN18_BITMASK	(1<<(CORE_PIN18_BIT))
+#define CORE_PIN19_BITMASK	(1<<(CORE_PIN19_BIT))
+#define CORE_PIN20_BITMASK	(1<<(CORE_PIN20_BIT))
+#define CORE_PIN21_BITMASK	(1<<(CORE_PIN21_BIT))
+#define CORE_PIN22_BITMASK	(1<<(CORE_PIN22_BIT))
+#define CORE_PIN23_BITMASK	(1<<(CORE_PIN23_BIT))
+#define CORE_PIN24_BITMASK	(1<<(CORE_PIN24_BIT))
+#define CORE_PIN25_BITMASK	(1<<(CORE_PIN25_BIT))
+#define CORE_PIN26_BITMASK	(1<<(CORE_PIN26_BIT))
+#define CORE_PIN27_BITMASK	(1<<(CORE_PIN27_BIT))
+#define CORE_PIN28_BITMASK	(1<<(CORE_PIN28_BIT))
+#define CORE_PIN29_BITMASK	(1<<(CORE_PIN29_BIT))
+#define CORE_PIN30_BITMASK	(1<<(CORE_PIN30_BIT))
+#define CORE_PIN31_BITMASK	(1<<(CORE_PIN31_BIT))
+#define CORE_PIN32_BITMASK	(1<<(CORE_PIN32_BIT))
+#define CORE_PIN33_BITMASK	(1<<(CORE_PIN33_BIT))
+#define CORE_PIN34_BITMASK	(1<<(CORE_PIN34_BIT))
+#define CORE_PIN35_BITMASK	(1<<(CORE_PIN35_BIT))
+#define CORE_PIN36_BITMASK	(1<<(CORE_PIN36_BIT))
+#define CORE_PIN37_BITMASK	(1<<(CORE_PIN37_BIT))
+#define CORE_PIN38_BITMASK	(1<<(CORE_PIN38_BIT))
+#define CORE_PIN39_BITMASK	(1<<(CORE_PIN39_BIT))
+
+#define CORE_PIN0_PORTREG	GPIOB_PDOR
+#define CORE_PIN1_PORTREG	GPIOB_PDOR
+#define CORE_PIN2_PORTREG	GPIOD_PDOR
+#define CORE_PIN3_PORTREG	GPIOA_PDOR
+#define CORE_PIN4_PORTREG	GPIOA_PDOR
+#define CORE_PIN5_PORTREG	GPIOD_PDOR
+#define CORE_PIN6_PORTREG	GPIOD_PDOR
+#define CORE_PIN7_PORTREG	GPIOD_PDOR
+#define CORE_PIN8_PORTREG	GPIOD_PDOR
+#define CORE_PIN9_PORTREG	GPIOC_PDOR
+#define CORE_PIN10_PORTREG	GPIOC_PDOR
+#define CORE_PIN11_PORTREG	GPIOC_PDOR
+#define CORE_PIN12_PORTREG	GPIOC_PDOR
+#define CORE_PIN13_PORTREG	GPIOC_PDOR
+#define CORE_PIN14_PORTREG	GPIOD_PDOR
+#define CORE_PIN15_PORTREG	GPIOC_PDOR
+#define CORE_PIN16_PORTREG	GPIOB_PDOR
+#define CORE_PIN17_PORTREG	GPIOB_PDOR
+#define CORE_PIN18_PORTREG	GPIOB_PDOR
+#define CORE_PIN19_PORTREG	GPIOB_PDOR
+#define CORE_PIN20_PORTREG	GPIOD_PDOR
+#define CORE_PIN21_PORTREG	GPIOD_PDOR
+#define CORE_PIN22_PORTREG	GPIOC_PDOR
+#define CORE_PIN23_PORTREG	GPIOC_PDOR
+#define CORE_PIN24_PORTREG	GPIOE_PDOR
+#define CORE_PIN25_PORTREG	GPIOA_PDOR
+#define CORE_PIN26_PORTREG	GPIOA_PDOR
+#define CORE_PIN27_PORTREG	GPIOA_PDOR
+#define CORE_PIN28_PORTREG	GPIOA_PDOR
+#define CORE_PIN29_PORTREG	GPIOB_PDOR
+#define CORE_PIN30_PORTREG	GPIOB_PDOR
+#define CORE_PIN31_PORTREG	GPIOB_PDOR
+#define CORE_PIN32_PORTREG	GPIOB_PDOR
+#define CORE_PIN33_PORTREG	GPIOE_PDOR
+#define CORE_PIN34_PORTREG	GPIOE_PDOR
+#define CORE_PIN35_PORTREG	GPIOC_PDOR
+#define CORE_PIN36_PORTREG	GPIOC_PDOR
+#define CORE_PIN37_PORTREG	GPIOC_PDOR
+#define CORE_PIN38_PORTREG	GPIOC_PDOR
+#define CORE_PIN39_PORTREG	GPIOA_PDOR
+
+#define CORE_PIN0_PORTSET	GPIOB_PSOR
+#define CORE_PIN1_PORTSET	GPIOB_PSOR
+#define CORE_PIN2_PORTSET	GPIOD_PSOR
+#define CORE_PIN3_PORTSET	GPIOA_PSOR
+#define CORE_PIN4_PORTSET	GPIOA_PSOR
+#define CORE_PIN5_PORTSET	GPIOD_PSOR
+#define CORE_PIN6_PORTSET	GPIOD_PSOR
+#define CORE_PIN7_PORTSET	GPIOD_PSOR
+#define CORE_PIN8_PORTSET	GPIOD_PSOR
+#define CORE_PIN9_PORTSET	GPIOC_PSOR
+#define CORE_PIN10_PORTSET	GPIOC_PSOR
+#define CORE_PIN11_PORTSET	GPIOC_PSOR
+#define CORE_PIN12_PORTSET	GPIOC_PSOR
+#define CORE_PIN13_PORTSET	GPIOC_PSOR
+#define CORE_PIN14_PORTSET	GPIOD_PSOR
+#define CORE_PIN15_PORTSET	GPIOC_PSOR
+#define CORE_PIN16_PORTSET	GPIOB_PSOR
+#define CORE_PIN17_PORTSET	GPIOB_PSOR
+#define CORE_PIN18_PORTSET	GPIOB_PSOR
+#define CORE_PIN19_PORTSET	GPIOB_PSOR
+#define CORE_PIN20_PORTSET	GPIOD_PSOR
+#define CORE_PIN21_PORTSET	GPIOD_PSOR
+#define CORE_PIN22_PORTSET	GPIOC_PSOR
+#define CORE_PIN23_PORTSET	GPIOC_PSOR
+#define CORE_PIN24_PORTSET	GPIOE_PSOR
+#define CORE_PIN25_PORTSET	GPIOA_PSOR
+#define CORE_PIN26_PORTSET	GPIOA_PSOR
+#define CORE_PIN27_PORTSET	GPIOA_PSOR
+#define CORE_PIN28_PORTSET	GPIOA_PSOR
+#define CORE_PIN29_PORTSET	GPIOB_PSOR
+#define CORE_PIN30_PORTSET	GPIOB_PSOR
+#define CORE_PIN31_PORTSET	GPIOB_PSOR
+#define CORE_PIN32_PORTSET	GPIOB_PSOR
+#define CORE_PIN33_PORTSET	GPIOE_PSOR
+#define CORE_PIN34_PORTSET	GPIOE_PSOR
+#define CORE_PIN35_PORTSET	GPIOC_PSOR
+#define CORE_PIN36_PORTSET	GPIOC_PSOR
+#define CORE_PIN37_PORTSET	GPIOC_PSOR
+#define CORE_PIN38_PORTSET	GPIOC_PSOR
+#define CORE_PIN39_PORTSET	GPIOA_PSOR
+
+#define CORE_PIN0_PORTCLEAR	GPIOB_PCOR
+#define CORE_PIN1_PORTCLEAR	GPIOB_PCOR
+#define CORE_PIN2_PORTCLEAR	GPIOD_PCOR
+#define CORE_PIN3_PORTCLEAR	GPIOA_PCOR
+#define CORE_PIN4_PORTCLEAR	GPIOA_PCOR
+#define CORE_PIN5_PORTCLEAR	GPIOD_PCOR
+#define CORE_PIN6_PORTCLEAR	GPIOD_PCOR
+#define CORE_PIN7_PORTCLEAR	GPIOD_PCOR
+#define CORE_PIN8_PORTCLEAR	GPIOD_PCOR
+#define CORE_PIN9_PORTCLEAR	GPIOC_PCOR
+#define CORE_PIN10_PORTCLEAR	GPIOC_PCOR
+#define CORE_PIN11_PORTCLEAR	GPIOC_PCOR
+#define CORE_PIN12_PORTCLEAR	GPIOC_PCOR
+#define CORE_PIN13_PORTCLEAR	GPIOC_PCOR
+#define CORE_PIN14_PORTCLEAR	GPIOD_PCOR
+#define CORE_PIN15_PORTCLEAR	GPIOC_PCOR
+#define CORE_PIN16_PORTCLEAR	GPIOB_PCOR
+#define CORE_PIN17_PORTCLEAR	GPIOB_PCOR
+#define CORE_PIN18_PORTCLEAR	GPIOB_PCOR
+#define CORE_PIN19_PORTCLEAR	GPIOB_PCOR
+#define CORE_PIN20_PORTCLEAR	GPIOD_PCOR
+#define CORE_PIN21_PORTCLEAR	GPIOD_PCOR
+#define CORE_PIN22_PORTCLEAR	GPIOC_PCOR
+#define CORE_PIN23_PORTCLEAR	GPIOC_PCOR
+#define CORE_PIN24_PORTCLEAR	GPIOE_PCOR
+#define CORE_PIN25_PORTCLEAR	GPIOA_PCOR
+#define CORE_PIN26_PORTCLEAR	GPIOA_PCOR
+#define CORE_PIN27_PORTCLEAR	GPIOA_PCOR
+#define CORE_PIN28_PORTCLEAR	GPIOA_PCOR
+#define CORE_PIN29_PORTCLEAR	GPIOB_PCOR
+#define CORE_PIN30_PORTCLEAR	GPIOB_PCOR
+#define CORE_PIN31_PORTCLEAR	GPIOB_PCOR
+#define CORE_PIN32_PORTCLEAR	GPIOB_PCOR
+#define CORE_PIN33_PORTCLEAR	GPIOE_PCOR
+#define CORE_PIN34_PORTCLEAR	GPIOE_PCOR
+#define CORE_PIN35_PORTCLEAR	GPIOC_PCOR
+#define CORE_PIN36_PORTCLEAR	GPIOC_PCOR
+#define CORE_PIN37_PORTCLEAR	GPIOC_PCOR
+#define CORE_PIN38_PORTCLEAR	GPIOC_PCOR
+#define CORE_PIN39_PORTCLEAR	GPIOA_PCOR
+
+#define CORE_PIN0_DDRREG	GPIOB_PDDR
+#define CORE_PIN1_DDRREG	GPIOB_PDDR
+#define CORE_PIN2_DDRREG	GPIOD_PDDR
+#define CORE_PIN3_DDRREG	GPIOA_PDDR
+#define CORE_PIN4_DDRREG	GPIOA_PDDR
+#define CORE_PIN5_DDRREG	GPIOD_PDDR
+#define CORE_PIN6_DDRREG	GPIOD_PDDR
+#define CORE_PIN7_DDRREG	GPIOD_PDDR
+#define CORE_PIN8_DDRREG	GPIOD_PDDR
+#define CORE_PIN9_DDRREG	GPIOC_PDDR
+#define CORE_PIN10_DDRREG	GPIOC_PDDR
+#define CORE_PIN11_DDRREG	GPIOC_PDDR
+#define CORE_PIN12_DDRREG	GPIOC_PDDR
+#define CORE_PIN13_DDRREG	GPIOC_PDDR
+#define CORE_PIN14_DDRREG	GPIOD_PDDR
+#define CORE_PIN15_DDRREG	GPIOC_PDDR
+#define CORE_PIN16_DDRREG	GPIOB_PDDR
+#define CORE_PIN17_DDRREG	GPIOB_PDDR
+#define CORE_PIN18_DDRREG	GPIOB_PDDR
+#define CORE_PIN19_DDRREG	GPIOB_PDDR
+#define CORE_PIN20_DDRREG	GPIOD_PDDR
+#define CORE_PIN21_DDRREG	GPIOD_PDDR
+#define CORE_PIN22_DDRREG	GPIOC_PDDR
+#define CORE_PIN23_DDRREG	GPIOC_PDDR
+#define CORE_PIN24_DDRREG	GPIOE_PDDR
+#define CORE_PIN25_DDRREG	GPIOA_PDDR
+#define CORE_PIN26_DDRREG	GPIOA_PDDR
+#define CORE_PIN27_DDRREG	GPIOA_PDDR
+#define CORE_PIN28_DDRREG	GPIOA_PDDR
+#define CORE_PIN29_DDRREG	GPIOB_PDDR
+#define CORE_PIN30_DDRREG	GPIOB_PDDR
+#define CORE_PIN31_DDRREG	GPIOB_PDDR
+#define CORE_PIN32_DDRREG	GPIOB_PDDR
+#define CORE_PIN33_DDRREG	GPIOE_PDDR
+#define CORE_PIN34_DDRREG	GPIOE_PDDR
+#define CORE_PIN35_DDRREG	GPIOC_PDDR
+#define CORE_PIN36_DDRREG	GPIOC_PDDR
+#define CORE_PIN37_DDRREG	GPIOC_PDDR
+#define CORE_PIN38_DDRREG	GPIOC_PDDR
+#define CORE_PIN39_DDRREG	GPIOA_PDDR
+
+#define CORE_PIN0_PINREG	GPIOB_PDIR
+#define CORE_PIN1_PINREG	GPIOB_PDIR
+#define CORE_PIN2_PINREG	GPIOD_PDIR
+#define CORE_PIN3_PINREG	GPIOA_PDIR
+#define CORE_PIN4_PINREG	GPIOA_PDIR
+#define CORE_PIN5_PINREG	GPIOD_PDIR
+#define CORE_PIN6_PINREG	GPIOD_PDIR
+#define CORE_PIN7_PINREG	GPIOD_PDIR
+#define CORE_PIN8_PINREG	GPIOD_PDIR
+#define CORE_PIN9_PINREG	GPIOC_PDIR
+#define CORE_PIN10_PINREG	GPIOC_PDIR
+#define CORE_PIN11_PINREG	GPIOC_PDIR
+#define CORE_PIN12_PINREG	GPIOC_PDIR
+#define CORE_PIN13_PINREG	GPIOC_PDIR
+#define CORE_PIN14_PINREG	GPIOD_PDIR
+#define CORE_PIN15_PINREG	GPIOC_PDIR
+#define CORE_PIN16_PINREG	GPIOB_PDIR
+#define CORE_PIN17_PINREG	GPIOB_PDIR
+#define CORE_PIN18_PINREG	GPIOB_PDIR
+#define CORE_PIN19_PINREG	GPIOB_PDIR
+#define CORE_PIN20_PINREG	GPIOD_PDIR
+#define CORE_PIN21_PINREG	GPIOD_PDIR
+#define CORE_PIN22_PINREG	GPIOC_PDIR
+#define CORE_PIN23_PINREG	GPIOC_PDIR
+#define CORE_PIN24_PINREG	GPIOE_PDIR
+#define CORE_PIN25_PINREG	GPIOA_PDIR
+#define CORE_PIN26_PINREG	GPIOA_PDIR
+#define CORE_PIN27_PINREG	GPIOA_PDIR
+#define CORE_PIN28_PINREG	GPIOA_PDIR
+#define CORE_PIN29_PINREG	GPIOB_PDIR
+#define CORE_PIN30_PINREG	GPIOB_PDIR
+#define CORE_PIN31_PINREG	GPIOB_PDIR
+#define CORE_PIN32_PINREG	GPIOB_PDIR
+#define CORE_PIN33_PINREG	GPIOE_PDIR
+#define CORE_PIN34_PINREG	GPIOE_PDIR
+#define CORE_PIN35_PINREG	GPIOC_PDIR
+#define CORE_PIN36_PINREG	GPIOC_PDIR
+#define CORE_PIN37_PINREG	GPIOC_PDIR
+#define CORE_PIN38_PINREG	GPIOC_PDIR
+#define CORE_PIN39_PINREG	GPIOA_PDIR
+
+#define CORE_PIN0_CONFIG	PORTB_PCR16
+#define CORE_PIN1_CONFIG	PORTB_PCR17
+#define CORE_PIN2_CONFIG	PORTD_PCR0
+#define CORE_PIN3_CONFIG	PORTA_PCR12
+#define CORE_PIN4_CONFIG	PORTA_PCR13
+#define CORE_PIN5_CONFIG	PORTD_PCR7
+#define CORE_PIN6_CONFIG	PORTD_PCR4
+#define CORE_PIN7_CONFIG	PORTD_PCR2
+#define CORE_PIN8_CONFIG	PORTD_PCR3
+#define CORE_PIN9_CONFIG	PORTC_PCR3
+#define CORE_PIN10_CONFIG	PORTC_PCR4
+#define CORE_PIN11_CONFIG	PORTC_PCR6
+#define CORE_PIN12_CONFIG	PORTC_PCR7
+#define CORE_PIN13_CONFIG	PORTC_PCR5
+#define CORE_PIN14_CONFIG	PORTD_PCR1
+#define CORE_PIN15_CONFIG	PORTC_PCR0
+#define CORE_PIN16_CONFIG	PORTB_PCR0
+#define CORE_PIN17_CONFIG	PORTB_PCR1
+#define CORE_PIN18_CONFIG	PORTB_PCR3
+#define CORE_PIN19_CONFIG	PORTB_PCR2
+#define CORE_PIN20_CONFIG	PORTD_PCR5
+#define CORE_PIN21_CONFIG	PORTD_PCR6
+#define CORE_PIN22_CONFIG	PORTC_PCR1
+#define CORE_PIN23_CONFIG	PORTC_PCR2
+#define CORE_PIN24_CONFIG	PORTE_PCR26
+#define CORE_PIN25_CONFIG	PORTA_PCR5
+#define CORE_PIN26_CONFIG	PORTA_PCR14
+#define CORE_PIN27_CONFIG	PORTA_PCR15
+#define CORE_PIN28_CONFIG	PORTA_PCR16
+#define CORE_PIN29_CONFIG	PORTB_PCR18
+#define CORE_PIN30_CONFIG	PORTB_PCR19
+#define CORE_PIN31_CONFIG	PORTB_PCR10
+#define CORE_PIN32_CONFIG	PORTB_PCR11
+#define CORE_PIN33_CONFIG	PORTE_PCR24
+#define CORE_PIN34_CONFIG	PORTE_PCR25
+#define CORE_PIN35_CONFIG	PORTC_PCR8
+#define CORE_PIN36_CONFIG	PORTC_PCR9
+#define CORE_PIN37_CONFIG	PORTC_PCR10
+#define CORE_PIN38_CONFIG	PORTC_PCR11
+#define CORE_PIN39_CONFIG	PORTA_PCR17
+
+#define CORE_ADC0_PIN		14
+#define CORE_ADC1_PIN		15
+#define CORE_ADC2_PIN		16
+#define CORE_ADC3_PIN		17
+#define CORE_ADC4_PIN		18
+#define CORE_ADC5_PIN		19
+#define CORE_ADC6_PIN		20
+#define CORE_ADC7_PIN		21
+#define CORE_ADC8_PIN		22
+#define CORE_ADC9_PIN		23
+#define CORE_ADC10_PIN		40
+#define CORE_ADC11_PIN		41
+#define CORE_ADC12_PIN		31
+#define CORE_ADC13_PIN		32
+#define CORE_ADC14_PIN		33
+#define CORE_ADC15_PIN		34
+#define CORE_ADC16_PIN		35
+#define CORE_ADC17_PIN		36
+#define CORE_ADC18_PIN		37
+#define CORE_ADC19_PIN		38
+#define CORE_ADC20_PIN		39
+
+#define CORE_RXD0_PIN		0
+#define CORE_TXD0_PIN		1
+#define CORE_RXD1_PIN		9
+#define CORE_TXD1_PIN		10
+#define CORE_RXD2_PIN		7
+#define CORE_TXD2_PIN		8
+#define CORE_RXD3_PIN		31
+#define CORE_TXD3_PIN		32
+#define CORE_RXD4_PIN		34
+#define CORE_TXD4_PIN		33
+
+#define CORE_INT0_PIN		0
+#define CORE_INT1_PIN		1
+#define CORE_INT2_PIN		2
+#define CORE_INT3_PIN		3
+#define CORE_INT4_PIN		4
+#define CORE_INT5_PIN		5
+#define CORE_INT6_PIN		6
+#define CORE_INT7_PIN		7
+#define CORE_INT8_PIN		8
+#define CORE_INT9_PIN		9
+#define CORE_INT10_PIN		10
+#define CORE_INT11_PIN		11
+#define CORE_INT12_PIN		12
+#define CORE_INT13_PIN		13
+#define CORE_INT14_PIN		14
+#define CORE_INT15_PIN		15
+#define CORE_INT16_PIN		16
+#define CORE_INT17_PIN		17
+#define CORE_INT18_PIN		18
+#define CORE_INT19_PIN		19
+#define CORE_INT20_PIN		20
+#define CORE_INT21_PIN		21
+#define CORE_INT22_PIN		22
+#define CORE_INT23_PIN		23
+#define CORE_INT24_PIN		24
+#define CORE_INT25_PIN		25
+#define CORE_INT26_PIN		26
+#define CORE_INT27_PIN		27
+#define CORE_INT28_PIN		28
+#define CORE_INT29_PIN		29
+#define CORE_INT30_PIN		30
+#define CORE_INT31_PIN		31
+#define CORE_INT32_PIN		32
+#define CORE_INT33_PIN		33
+#define CORE_INT34_PIN		34
+#define CORE_INT35_PIN		35
+#define CORE_INT36_PIN		36
+#define CORE_INT37_PIN		37
+#define CORE_INT38_PIN		38
+#define CORE_INT39_PIN		39
+#define CORE_INT_EVERY_PIN	1
+
 #endif
 
 
@@ -808,6 +1219,21 @@ static inline void digitalWriteFast(uint8_t pin, uint8_t val)
 				CORE_PIN33_PORTSET = CORE_PIN33_BITMASK;
 			}
 			#endif
+			#if defined(CORE_PIN34_PORTSET)
+			  else if (pin == 34) {
+				CORE_PIN34_PORTSET = CORE_PIN34_BITMASK;
+			} else if (pin == 35) {
+				CORE_PIN35_PORTSET = CORE_PIN35_BITMASK;
+			} else if (pin == 36) {
+				CORE_PIN36_PORTSET = CORE_PIN36_BITMASK;
+			} else if (pin == 37) {
+				CORE_PIN37_PORTSET = CORE_PIN37_BITMASK;
+			} else if (pin == 38) {
+				CORE_PIN38_PORTSET = CORE_PIN38_BITMASK;
+			} else if (pin == 39) {
+				CORE_PIN39_PORTSET = CORE_PIN39_BITMASK;
+			}
+			#endif
 		} else {
 			if (pin == 0) {
 				CORE_PIN0_PORTCLEAR = CORE_PIN0_BITMASK;
@@ -881,6 +1307,21 @@ static inline void digitalWriteFast(uint8_t pin, uint8_t val)
 				CORE_PIN33_PORTCLEAR = CORE_PIN33_BITMASK;
 			}
 			#endif
+			#if defined(CORE_PIN34_PORTCLEAR)
+			  else if (pin == 34) {
+				CORE_PIN34_PORTCLEAR = CORE_PIN34_BITMASK;
+			} else if (pin == 35) {
+				CORE_PIN35_PORTCLEAR = CORE_PIN35_BITMASK;
+			} else if (pin == 36) {
+				CORE_PIN36_PORTCLEAR = CORE_PIN36_BITMASK;
+			} else if (pin == 37) {
+				CORE_PIN37_PORTCLEAR = CORE_PIN37_BITMASK;
+			} else if (pin == 38) {
+				CORE_PIN38_PORTCLEAR = CORE_PIN38_BITMASK;
+			} else if (pin == 39) {
+				CORE_PIN39_PORTCLEAR = CORE_PIN39_BITMASK;
+			}
+			#endif
 		}
 	} else {
 		if (val) {
@@ -967,6 +1408,21 @@ static inline uint8_t digitalReadFast(uint8_t pin)
 		} else if (pin == 33) {
 			return (CORE_PIN33_PINREG & CORE_PIN33_BITMASK) ? 1 : 0;
 		}
+		#endif
+		#if defined(CORE_PIN34_PINREG)
+		  else if (pin == 34) {
+			return (CORE_PIN34_PINREG & CORE_PIN34_BITMASK) ? 1 : 0;
+		} else if (pin == 35) {
+			return (CORE_PIN35_PINREG & CORE_PIN35_BITMASK) ? 1 : 0;
+		} else if (pin == 36) {
+			return (CORE_PIN36_PINREG & CORE_PIN36_BITMASK) ? 1 : 0;
+		} else if (pin == 37) {
+			return (CORE_PIN37_PINREG & CORE_PIN37_BITMASK) ? 1 : 0;
+		} else if (pin == 38) {
+			return (CORE_PIN38_PINREG & CORE_PIN38_BITMASK) ? 1 : 0;
+		} else if (pin == 39) {
+			return (CORE_PIN39_PINREG & CORE_PIN39_BITMASK) ? 1 : 0;
+		}
 		#endif
 		  else {
 			return 0;
@@ -988,6 +1444,7 @@ void analogWriteRes(uint32_t bits);
 static inline void analogWriteResolution(uint32_t bits) { analogWriteRes(bits); }
 void analogWriteFrequency(uint8_t pin, float frequency);
 void analogWriteDAC0(int val);
+void analogWriteDAC1(int val);
 #ifdef __cplusplus
 void attachInterruptVector(IRQ_NUMBER_t irq, void (*function)(void));
 #else
@@ -1005,7 +1462,7 @@ void analogReadAveraging(unsigned int num);
 void analog_init(void);
 
 
-#if defined(__MK20DX128__) || defined(__MK20DX256__)
+#if defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK66FX1M0__)
 #define DEFAULT         0
 #define INTERNAL        2
 #define INTERNAL1V2     2

teensy3/kinetis.h

@@ -3001,6 +3001,45 @@ typedef struct {
 #define FTM2_INVCTRL		(*(volatile uint32_t *)0x400B8090) // FTM Inverting Control
 #define FTM2_SWOCTRL		(*(volatile uint32_t *)0x400B8094) // FTM Software Output Control
 #define FTM2_PWMLOAD		(*(volatile uint32_t *)0x400B8098) // FTM PWM Load
+#define FTM3_SC			(*(volatile uint32_t *)0x400B9000) // Status And Control
+#define FTM3_CNT		(*(volatile uint32_t *)0x400B9004) // Counter
+#define FTM3_MOD		(*(volatile uint32_t *)0x400B9008) // Modulo
+#define FTM3_C0SC		(*(volatile uint32_t *)0x400B900C) // Channel 0 Status And Control
+#define FTM3_C0V		(*(volatile uint32_t *)0x400B9010) // Channel 0 Value
+#define FTM3_C1SC		(*(volatile uint32_t *)0x400B9014) // Channel 1 Status And Control
+#define FTM3_C1V		(*(volatile uint32_t *)0x400B9018) // Channel 1 Value
+#define FTM3_C2SC		(*(volatile uint32_t *)0x400B901C) // Channel 1 Status And Control
+#define FTM3_C2V		(*(volatile uint32_t *)0x400B9020) // Channel 1 Value
+#define FTM3_C3SC		(*(volatile uint32_t *)0x400B9024) // Channel 1 Status And Control
+#define FTM3_C3V		(*(volatile uint32_t *)0x400B9028) // Channel 1 Value
+#define FTM3_C4SC		(*(volatile uint32_t *)0x400B902C) // Channel 1 Status And Control
+#define FTM3_C4V		(*(volatile uint32_t *)0x400B9030) // Channel 1 Value
+#define FTM3_C5SC		(*(volatile uint32_t *)0x400B9034) // Channel 1 Status And Control
+#define FTM3_C5V		(*(volatile uint32_t *)0x400B9038) // Channel 1 Value
+#define FTM3_C6SC		(*(volatile uint32_t *)0x400B903C) // Channel 1 Status And Control
+#define FTM3_C6V		(*(volatile uint32_t *)0x400B9040) // Channel 1 Value
+#define FTM3_C7SC		(*(volatile uint32_t *)0x400B9044) // Channel 1 Status And Control
+#define FTM3_C7V		(*(volatile uint32_t *)0x400B9048) // Channel 1 Value
+#define FTM3_CNTIN		(*(volatile uint32_t *)0x400B904C) // Counter Initial Value
+#define FTM3_STATUS		(*(volatile uint32_t *)0x400B9050) // Capture And Compare Status
+#define FTM3_MODE		(*(volatile uint32_t *)0x400B9054) // Features Mode Selection
+#define FTM3_SYNC		(*(volatile uint32_t *)0x400B9058) // Synchronization
+#define FTM3_OUTINIT		(*(volatile uint32_t *)0x400B905C) // Initial State For Channels Output
+#define FTM3_OUTMASK		(*(volatile uint32_t *)0x400B9060) // Output Mask
+#define FTM3_COMBINE		(*(volatile uint32_t *)0x400B9064) // Function For Linked Channels
+#define FTM3_DEADTIME		(*(volatile uint32_t *)0x400B9068) // Deadtime Insertion Control
+#define FTM3_EXTTRIG		(*(volatile uint32_t *)0x400B906C) // FTM External Trigger
+#define FTM3_POL		(*(volatile uint32_t *)0x400B9070) // Channels Polarity
+#define FTM3_FMS		(*(volatile uint32_t *)0x400B9074) // Fault Mode Status
+#define FTM3_FILTER		(*(volatile uint32_t *)0x400B9078) // Input Capture Filter Control
+#define FTM3_FLTCTRL		(*(volatile uint32_t *)0x400B907C) // Fault Control
+#define FTM3_QDCTRL		(*(volatile uint32_t *)0x400B9080) // Quadrature Decoder Control And Status
+#define FTM3_CONF		(*(volatile uint32_t *)0x400B9084) // Configuration
+#define FTM3_FLTPOL		(*(volatile uint32_t *)0x400B9088) // FTM Fault Input Polarity
+#define FTM3_SYNCONF		(*(volatile uint32_t *)0x400B908C) // Synchronization Configuration
+#define FTM3_INVCTRL		(*(volatile uint32_t *)0x400B9090) // FTM Inverting Control
+#define FTM3_SWOCTRL		(*(volatile uint32_t *)0x400B9094) // FTM Software Output Control
+#define FTM3_PWMLOAD		(*(volatile uint32_t *)0x400B9098) // FTM PWM Load
 #elif defined(KINETISL)
 #define FTM2_SC			(*(volatile uint32_t *)0x4003A000) // Status And Control
 #define FTM2_CNT		(*(volatile uint32_t *)0x4003A004) // Counter

teensy3/memcpy-armv7m.S

@@ -26,7 +26,7 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#if defined(__MK20DX128__) || defined(__MK20DX256__)
+#if defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK66FX1M0__)
 #if defined (__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
 #define __ARM_FEATURE_UNALIGNED 1
  
@@ -325,5 +325,5 @@ memcpy:
 	.size	memcpy, .-memcpy
 #endif
 
-#endif // __MK20DX128__ || __MK20DX256__
+#endif // __MK20DX128__ || __MK20DX256__ || __MK66FX1M0__
 

teensy3/mk66fx1m0.ld

@@ -0,0 +1,147 @@
+/* Teensyduino Core Library
+ * http://www.pjrc.com/teensy/
+ * Copyright (c) 2013 PJRC.COM, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * 1. The above copyright notice and this permission notice shall be 
+ * included in all copies or substantial portions of the Software.
+ *
+ * 2. If the Software is incorporated into a build system that allows 
+ * selection among a list of target devices, then similar target
+ * devices manufactured by PJRC.COM must be included in the list of
+ * target devices and selectable in the same manner.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+MEMORY
+{
+	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 1024K
+	RAM  (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 256K
+}
+
+
+/* INCLUDE common.ld */
+
+
+/* Teensyduino Core Library
+ * http://www.pjrc.com/teensy/
+ * Copyright (c) 2013 PJRC.COM, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * 1. The above copyright notice and this permission notice shall be 
+ * included in all copies or substantial portions of the Software.
+ *
+ * 2. If the Software is incorporated into a build system that allows 
+ * selection among a list of target devices, then similar target
+ * devices manufactured by PJRC.COM must be included in the list of
+ * target devices and selectable in the same manner.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+
+
+SECTIONS
+{
+	.text : {
+		. = 0;
+		KEEP(*(.vectors))
+		*(.startup*)
+		/* TODO: does linker detect startup overflow onto flashconfig? */
+		. = 0x400;
+		KEEP(*(.flashconfig*))
+		*(.text*)
+		*(.rodata*)
+		. = ALIGN(4);
+		KEEP(*(.init))
+		. = ALIGN(4);
+		__preinit_array_start = .;
+		KEEP (*(.preinit_array))
+		__preinit_array_end = .;
+		__init_array_start = .;
+		KEEP (*(SORT(.init_array.*)))
+		KEEP (*(.init_array))
+		__init_array_end = .;
+	} > FLASH = 0xFF
+
+	.ARM.exidx : {
+		__exidx_start = .;
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+		__exidx_end = .;
+	} > FLASH
+	_etext = .;
+
+	.usbdescriptortable (NOLOAD) : {
+		/* . = ORIGIN(RAM); */
+		. = ALIGN(512);
+		*(.usbdescriptortable*)
+	} > RAM
+
+	.dmabuffers (NOLOAD) : {
+		. = ALIGN(4);
+		*(.dmabuffers*)
+	} > RAM
+
+	.usbbuffers (NOLOAD) : {
+		. = ALIGN(4);
+		*(.usbbuffers*)
+	} > RAM
+
+	.data : AT (_etext) {
+		. = ALIGN(4);
+		_sdata = .; 
+		*(.fastrun*)
+		*(.data*)
+		. = ALIGN(4);
+		_edata = .; 
+	} > RAM
+
+	.noinit (NOLOAD) : {
+		*(.noinit*)
+	} > RAM
+
+	.bss : {
+		. = ALIGN(4);
+		_sbss = .; 
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		_ebss = .;
+		__bss_end = .;
+	} > RAM
+
+	_estack = ORIGIN(RAM) + LENGTH(RAM);
+}
+
+
+
+

teensy3/pins_arduino.h

@@ -65,6 +65,20 @@ const static uint8_t A20 = 31;
 const static uint8_t A10 = 24;
 const static uint8_t A11 = 25;
 const static uint8_t A12 = 26;
+#elif defined(__MK66FX1M0__)
+const static uint8_t A10 = 40;
+const static uint8_t A11 = 41;
+const static uint8_t A12 = 31;
+const static uint8_t A13 = 32;
+const static uint8_t A14 = 33;
+const static uint8_t A15 = 34;
+const static uint8_t A16 = 35;
+const static uint8_t A17 = 36;
+const static uint8_t A18 = 37;
+const static uint8_t A19 = 38;
+const static uint8_t A20 = 39;
+const static uint8_t A21 = 42;
+const static uint8_t A22 = 43;
 #endif
 
 const static uint8_t SS = 10;
@@ -95,6 +109,10 @@ const static uint8_t SCL = 19;
   #define analogInputToDigitalPin(p) (((p) <= 9) ? (p) + 14 : (((p) <= 12) ? (p) + 14 : -1))
   #define digitalPinHasPWM(p) ((p) == 3 || (p) == 4 || (p) == 6 || (p) == 9 || (p) == 10 || (p) == 16 || (p) == 17 || (p) == 20 || (p) == 22 || (p) == 23)
   #define digitalPinToInterrupt(p)  ((((p) >= 2 && (p) <= 15) || ((p) >= 20 && (p) <= 23)) ? (p) : -1)
+#elif defined(__MK66FX1M0__)
+  #define analogInputToDigitalPin(p) (((p) <= 9) ? (p) + 14 : (((p) >= 12 && (p) <= 20) ? (p) + 19 : -1))
+  #define digitalPinHasPWM(p) (((p) >= 2 && (p) <= 10) || (p) == 14 || ((p) >= 20 && (p) <= 23) || (p) == 29 || (p) == 30 || ((p) >= 35 && (p) <= 38))
+  #define digitalPinToInterrupt(p)  ((p) < NUM_DIGITAL_PINS ? (p) : -1)
 #endif
 
 

teensy3/pins_teensy.c

@@ -72,7 +72,15 @@ const struct digital_pin_bitband_and_config_table_struct digital_pin_to_info_PGM
 	{GPIO_BITBAND_PTR(CORE_PIN30_PORTREG, CORE_PIN30_BIT), &CORE_PIN30_CONFIG},
 	{GPIO_BITBAND_PTR(CORE_PIN31_PORTREG, CORE_PIN31_BIT), &CORE_PIN31_CONFIG},
 	{GPIO_BITBAND_PTR(CORE_PIN32_PORTREG, CORE_PIN32_BIT), &CORE_PIN32_CONFIG},
-	{GPIO_BITBAND_PTR(CORE_PIN33_PORTREG, CORE_PIN33_BIT), &CORE_PIN33_CONFIG}
+	{GPIO_BITBAND_PTR(CORE_PIN33_PORTREG, CORE_PIN33_BIT), &CORE_PIN33_CONFIG},
+#ifdef CORE_PIN34_PORTREG
+	{GPIO_BITBAND_PTR(CORE_PIN34_PORTREG, CORE_PIN34_BIT), &CORE_PIN34_CONFIG},
+	{GPIO_BITBAND_PTR(CORE_PIN35_PORTREG, CORE_PIN35_BIT), &CORE_PIN35_CONFIG},
+	{GPIO_BITBAND_PTR(CORE_PIN36_PORTREG, CORE_PIN36_BIT), &CORE_PIN36_CONFIG},
+	{GPIO_BITBAND_PTR(CORE_PIN37_PORTREG, CORE_PIN37_BIT), &CORE_PIN37_CONFIG},
+	{GPIO_BITBAND_PTR(CORE_PIN38_PORTREG, CORE_PIN38_BIT), &CORE_PIN38_CONFIG},
+	{GPIO_BITBAND_PTR(CORE_PIN39_PORTREG, CORE_PIN39_BIT), &CORE_PIN39_CONFIG},
+#endif
 };
 
 #elif defined(KINETISL)
@@ -175,7 +183,7 @@ void detachInterrupt(uint8_t pin)
 	__enable_irq();
 }
 
-#if defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK66FX1M0__)
+#if defined(__MK20DX128__) || defined(__MK20DX256__)
 
 static void porta_interrupt(void)
 {
@@ -276,10 +284,83 @@ static void portcd_interrupt(void)
 	if ((isfr & CORE_PIN21_BITMASK) && intFunc[21]) intFunc[21]();
 }
 
+#elif defined(__MK66FX1M0__)
+
+static void porta_interrupt(void)
+{
+	uint32_t isfr = PORTA_ISFR;
+	PORTA_ISFR = isfr;
+	if ((isfr & CORE_PIN3_BITMASK) && intFunc[3]) intFunc[3]();
+	if ((isfr & CORE_PIN4_BITMASK) && intFunc[4]) intFunc[4]();
+	if ((isfr & CORE_PIN25_BITMASK) && intFunc[25]) intFunc[25]();
+	if ((isfr & CORE_PIN26_BITMASK) && intFunc[26]) intFunc[26]();
+	if ((isfr & CORE_PIN27_BITMASK) && intFunc[27]) intFunc[27]();
+	if ((isfr & CORE_PIN28_BITMASK) && intFunc[28]) intFunc[28]();
+	if ((isfr & CORE_PIN39_BITMASK) && intFunc[39]) intFunc[39]();
+}
+
+static void portb_interrupt(void)
+{
+	uint32_t isfr = PORTB_ISFR;
+	PORTB_ISFR = isfr;
+	if ((isfr & CORE_PIN0_BITMASK) && intFunc[0]) intFunc[0]();
+	if ((isfr & CORE_PIN1_BITMASK) && intFunc[1]) intFunc[1]();
+	if ((isfr & CORE_PIN16_BITMASK) && intFunc[16]) intFunc[16]();
+	if ((isfr & CORE_PIN17_BITMASK) && intFunc[17]) intFunc[17]();
+	if ((isfr & CORE_PIN18_BITMASK) && intFunc[18]) intFunc[18]();
+	if ((isfr & CORE_PIN19_BITMASK) && intFunc[19]) intFunc[19]();
+	if ((isfr & CORE_PIN29_BITMASK) && intFunc[29]) intFunc[29]();
+	if ((isfr & CORE_PIN30_BITMASK) && intFunc[30]) intFunc[30]();
+	if ((isfr & CORE_PIN31_BITMASK) && intFunc[31]) intFunc[31]();
+	if ((isfr & CORE_PIN32_BITMASK) && intFunc[32]) intFunc[32]();
+}
+
+static void portc_interrupt(void)
+{
+	// TODO: these are inefficent.  Use CLZ somehow....
+	uint32_t isfr = PORTC_ISFR;
+	PORTC_ISFR = isfr;
+	if ((isfr & CORE_PIN9_BITMASK) && intFunc[9]) intFunc[9]();
+	if ((isfr & CORE_PIN10_BITMASK) && intFunc[10]) intFunc[10]();
+	if ((isfr & CORE_PIN11_BITMASK) && intFunc[11]) intFunc[11]();
+	if ((isfr & CORE_PIN12_BITMASK) && intFunc[12]) intFunc[12]();
+	if ((isfr & CORE_PIN13_BITMASK) && intFunc[13]) intFunc[13]();
+	if ((isfr & CORE_PIN15_BITMASK) && intFunc[15]) intFunc[15]();
+	if ((isfr & CORE_PIN22_BITMASK) && intFunc[22]) intFunc[22]();
+	if ((isfr & CORE_PIN23_BITMASK) && intFunc[23]) intFunc[23]();
+	if ((isfr & CORE_PIN35_BITMASK) && intFunc[35]) intFunc[35]();
+	if ((isfr & CORE_PIN36_BITMASK) && intFunc[36]) intFunc[36]();
+	if ((isfr & CORE_PIN37_BITMASK) && intFunc[37]) intFunc[37]();
+	if ((isfr & CORE_PIN38_BITMASK) && intFunc[38]) intFunc[38]();
+}
+
+static void portd_interrupt(void)
+{
+	uint32_t isfr = PORTD_ISFR;
+	PORTD_ISFR = isfr;
+	if ((isfr & CORE_PIN2_BITMASK) && intFunc[2]) intFunc[2]();
+	if ((isfr & CORE_PIN5_BITMASK) && intFunc[5]) intFunc[5]();
+	if ((isfr & CORE_PIN6_BITMASK) && intFunc[6]) intFunc[6]();
+	if ((isfr & CORE_PIN7_BITMASK) && intFunc[7]) intFunc[7]();
+	if ((isfr & CORE_PIN8_BITMASK) && intFunc[8]) intFunc[8]();
+	if ((isfr & CORE_PIN14_BITMASK) && intFunc[14]) intFunc[14]();
+	if ((isfr & CORE_PIN20_BITMASK) && intFunc[20]) intFunc[20]();
+	if ((isfr & CORE_PIN21_BITMASK) && intFunc[21]) intFunc[21]();
+}
+
+static void porte_interrupt(void)
+{
+	uint32_t isfr = PORTE_ISFR;
+	PORTE_ISFR = isfr;
+	if ((isfr & CORE_PIN24_BITMASK) && intFunc[24]) intFunc[24]();
+	if ((isfr & CORE_PIN33_BITMASK) && intFunc[33]) intFunc[33]();
+	if ((isfr & CORE_PIN34_BITMASK) && intFunc[34]) intFunc[34]();
+}
+
 #endif
 
 
-#if defined(__MK20DX128__) || defined(__MK20DX256__)
+#if defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK66FX1M0__)
 
 unsigned long rtc_get(void)
 {
@@ -435,7 +516,7 @@ extern void usb_init(void);
 //void init_pins(void)
 void _init_Teensyduino_internal_(void)
 {
-#if defined(__MK20DX128__) || defined(__MK20DX256__)
+#if defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK66FX1M0__)
 	NVIC_ENABLE_IRQ(IRQ_PORTA);
 	NVIC_ENABLE_IRQ(IRQ_PORTB);
 	NVIC_ENABLE_IRQ(IRQ_PORTC);
@@ -455,9 +536,19 @@ void _init_Teensyduino_internal_(void)
 	FTM0_C3SC = 0x28;
 	FTM0_C4SC = 0x28;
 	FTM0_C5SC = 0x28;
-#if defined(__MK20DX128__) || defined(__MK20DX256__)
+#if defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK66FX1M0__)
 	FTM0_C6SC = 0x28;
 	FTM0_C7SC = 0x28;
+#endif
+#if defined(__MK66FX1M0__)
+	FTM3_C0SC = 0x28;
+	FTM3_C1SC = 0x28;
+	FTM3_C2SC = 0x28;
+	FTM3_C3SC = 0x28;
+	FTM3_C4SC = 0x28;
+	FTM3_C5SC = 0x28;
+	FTM3_C6SC = 0x28;
+	FTM3_C7SC = 0x28;
 #endif
 	FTM0_SC = FTM_SC_CLKS(1) | FTM_SC_PS(DEFAULT_FTM_PRESCALE);
 	FTM1_CNT = 0;
@@ -465,12 +556,19 @@ void _init_Teensyduino_internal_(void)
 	FTM1_C0SC = 0x28;
 	FTM1_C1SC = 0x28;
 	FTM1_SC = FTM_SC_CLKS(1) | FTM_SC_PS(DEFAULT_FTM_PRESCALE);
-#if defined(__MK20DX256__) || defined(__MKL26Z64__)
+#if defined(__MK20DX256__) || defined(__MK66FX1M0__) || defined(__MKL26Z64__)
 	FTM2_CNT = 0;
 	FTM2_MOD = DEFAULT_FTM_MOD;
 	FTM2_C0SC = 0x28;
 	FTM2_C1SC = 0x28;
 	FTM2_SC = FTM_SC_CLKS(1) | FTM_SC_PS(DEFAULT_FTM_PRESCALE);
+#endif
+#if defined(__MK66FX1M0__)
+	FTM3_CNT = 0;
+	FTM3_MOD = DEFAULT_FTM_MOD;
+	FTM3_C0SC = 0x28;
+	FTM3_C1SC = 0x28;
+	FTM3_SC = FTM_SC_CLKS(1) | FTM_SC_PS(DEFAULT_FTM_PRESCALE);
 #endif
 	analog_init();
 	//delay(100); // TODO: this is not necessary, right?
@@ -490,7 +588,7 @@ void _init_Teensyduino_internal_(void)
 #define FTM0_CH7_PIN  5
 #define FTM1_CH0_PIN  3
 #define FTM1_CH1_PIN  4
-#elif defined(__MK20DX256__) || defined(__MK66FX1M0__)
+#elif defined(__MK20DX256__)
 #define FTM0_CH0_PIN 22
 #define FTM0_CH1_PIN 23
 #define FTM0_CH2_PIN  9
@@ -514,6 +612,27 @@ void _init_Teensyduino_internal_(void)
 #define FTM1_CH1_PIN 17
 #define FTM2_CH0_PIN  3
 #define FTM2_CH1_PIN  4
+#elif defined(__MK66FX1M0__)
+#define FTM0_CH0_PIN 22
+#define FTM0_CH1_PIN 23
+#define FTM0_CH2_PIN  9
+#define FTM0_CH3_PIN 10
+#define FTM0_CH4_PIN  6
+#define FTM0_CH5_PIN 20
+#define FTM0_CH6_PIN 21
+#define FTM0_CH7_PIN  5
+#define FTM1_CH0_PIN  3
+#define FTM1_CH1_PIN  4
+#define FTM2_CH0_PIN 29
+#define FTM2_CH1_PIN 30
+#define FTM3_CH0_PIN  2
+#define FTM3_CH1_PIN 14
+#define FTM3_CH2_PIN  7
+#define FTM3_CH3_PIN  8
+#define FTM3_CH4_PIN 35
+#define FTM3_CH5_PIN 36
+#define FTM3_CH6_PIN 37
+#define FTM3_CH7_PIN 38
 #endif
 #define FTM_PINCFG(pin) FTM_PINCFG2(pin)
 #define FTM_PINCFG2(pin) CORE_PIN ## pin ## _CONFIG
@@ -551,6 +670,18 @@ void analogWrite(uint8_t pin, int val)
 		analogWriteDAC0(val);
 		return;
 	}
+#elif defined(__MK66FX1M0__)
+	if (pin == A21 || pin == A22) {
+		uint8_t res = analog_write_res;
+		if (res < 12) {
+			val <<= 12 - res;
+		} else if (res > 12) {
+			val >>= res - 12;
+		}
+		if (pin == A21) analogWriteDAC0(val);
+		else analogWriteDAC1(val);
+		return;
+	}
 #endif
 
 	max = 1 << analog_write_res;
@@ -655,6 +786,54 @@ void analogWrite(uint8_t pin, int val)
 		FTM2_C1V = cval;
 		FTM_PINCFG(FTM2_CH1_PIN) = PORT_PCR_MUX(3) | PORT_PCR_DSE | PORT_PCR_SRE;
 		break;
+#endif
+#ifdef FTM3_CH0_PIN
+	  case FTM3_CH0_PIN:
+		FTM3_C0V = cval;
+		FTM_PINCFG(FTM3_CH0_PIN) = PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE;
+		break;
+#endif
+#ifdef FTM3_CH1_PIN
+	  case FTM3_CH1_PIN:
+		FTM3_C1V = cval;
+		FTM_PINCFG(FTM3_CH1_PIN) = PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE;
+		break;
+#endif
+#ifdef FTM3_CH2_PIN
+	  case FTM3_CH2_PIN:
+		FTM3_C2V = cval;
+		FTM_PINCFG(FTM3_CH2_PIN) = PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE;
+		break;
+#endif
+#ifdef FTM3_CH3_PIN
+	  case FTM3_CH3_PIN:
+		FTM3_C3V = cval;
+		FTM_PINCFG(FTM3_CH3_PIN) = PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE;
+		break;
+#endif
+#ifdef FTM3_CH4_PIN
+	  case FTM3_CH4_PIN:
+		FTM3_C4V = cval;
+		FTM_PINCFG(FTM3_CH4_PIN) = PORT_PCR_MUX(3) | PORT_PCR_DSE | PORT_PCR_SRE;
+		break;
+#endif
+#ifdef FTM3_CH5_PIN
+	  case FTM3_CH5_PIN:
+		FTM3_C5V = cval;
+		FTM_PINCFG(FTM3_CH5_PIN) = PORT_PCR_MUX(3) | PORT_PCR_DSE | PORT_PCR_SRE;
+		break;
+#endif
+#ifdef FTM3_CH6_PIN
+	  case FTM3_CH6_PIN:
+		FTM3_C6V = cval;
+		FTM_PINCFG(FTM3_CH6_PIN) = PORT_PCR_MUX(3) | PORT_PCR_DSE | PORT_PCR_SRE;
+		break;
+#endif
+#ifdef FTM3_CH7_PIN
+	  case FTM3_CH7_PIN:
+		FTM3_C7V = cval;
+		FTM_PINCFG(FTM3_CH7_PIN) = PORT_PCR_MUX(3) | PORT_PCR_DSE | PORT_PCR_SRE;
+		break;
 #endif
 	  default:
 		digitalWrite(pin, (val > 127) ? HIGH : LOW);
@@ -724,6 +903,17 @@ void analogWriteFrequency(uint8_t pin, float frequency)
 		FTM2_SC = FTM_SC_CLKS(1) | FTM_SC_PS(prescale);
 	}
 #endif
+#ifdef FTM3_CH0_PIN
+	  else if (pin == FTM3_CH0_PIN || pin == FTM3_CH1_PIN
+	  || pin == FTM3_CH2_PIN || pin == FTM3_CH3_PIN
+	  || pin == FTM3_CH4_PIN || pin == FTM3_CH5_PIN
+	  || pin == FTM3_CH6_PIN || pin == FTM3_CH7_PIN) {
+		FTM3_SC = 0;
+		FTM3_CNT = 0;
+		FTM3_MOD = mod;
+		FTM3_SC = FTM_SC_CLKS(1) | FTM_SC_PS(prescale);
+	}
+#endif
 }
 
 

teensy3/touch.c

@@ -31,7 +31,7 @@
 #include "core_pins.h"
 //#include "HardwareSerial.h"
 
-#if defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK66FX1M0__)
+#if defined(__MK20DX128__) || defined(__MK20DX256__)
 // These settings give approx 0.02 pF sensitivity and 1200 pF range
 // Lower current, higher number of scans, and higher prescaler
 // increase sensitivity, but the trade-off is longer measurement
@@ -47,6 +47,18 @@ static const uint8_t pin2tsi[] = {
 255, 255,  11,   5
 };
 
+#elif defined(__MK66FX1M0__)
+#define CURRENT   2
+#define NSCAN     9
+#define PRESCALE  2
+static const uint8_t pin2tsi[] = {
+//0    1    2    3    4    5    6    7    8    9
+  9,  10, 255, 255, 255, 255, 255, 255, 255, 255,
+255, 255, 255, 255, 255,  13,   0,   6,   8,   7,
+255, 255,  14,  15, 255, 255, 255, 255, 255,  11,
+ 12, 255, 255, 255, 255, 255, 255, 255, 255, 255
+};
+
 #elif defined(__MKL26Z64__)
 #define NSCAN     9
 #define PRESCALE  2

teensy3/usb_dev.c

@@ -947,6 +947,9 @@ void usb_init(void)
 	// assume 48 MHz clock already running
 	// SIM - enable clock
 	SIM_SCGC4 |= SIM_SCGC4_USBOTG;
+#ifdef HAS_KINETIS_MPU
+	MPU_RGDAAC0 |= 0x03000000;
+#endif
 
 	// reset USB module
 	//USB0_USBTRC0 = USB_USBTRC_USBRESET;