Minor DPIFIFO tweaks

teensy3/SPIFIFO.h

@@ -1,8 +1,12 @@
+#ifndef _SPIFIFO_h_
+#define _SPIFIFO_h_
 
 #include "avr_emulation.h"
 
+
 #if F_BUS == 48000000
 
+#define HAS_SPIFIFO
 #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(48 / 2) * ((1+1)/2)
 #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(48 / 3) * ((1+1)/2)  33% duty cycle
 #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0)) //(48 / 2) * ((1+0)/2)
@@ -12,6 +16,7 @@
 
 #elif F_BUS == 24000000
 
+#define HAS_SPIFIFO
 #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(24 / 2) * ((1+1)/2)  12 MHz
 #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(24 / 2) * ((1+1)/2)  12 MHz
 #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(24 / 2) * ((1+1)/2)
@@ -26,6 +31,9 @@
 //  DBR = 0, 1         -- zero preferred
 //  BR = 2, 4, 6, 8, 16, 32, 64, 128, 256, 512
 
+
+#ifdef HAS_SPIFIFO
+
 #ifndef SPI_MODE0
 #define SPI_MODE0 0x00  // CPOL = 0, CPHA = 0
 #define SPI_MODE1 0x04  // CPOL = 0, CPHA = 1
@@ -35,9 +43,6 @@
 
 #define SPI_CONTINUE 1
 
-static uint8_t pcs = 0;
-static volatile uint8_t *reg = 0;
-
 class SPIFIFOclass
 {
 public:
@@ -134,8 +139,11 @@ public:
 	inline void clear(void) __attribute__((always_inline)) {
 		SPI0.MCR = SPI_MCR_MSTR | SPI_MCR_PCSIS(0x1F) | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;
 	}
+private:
+	static uint8_t pcs;
+	static volatile uint8_t *reg;
 };
 extern SPIFIFOclass SPIFIFO;
 
-
-
+#endif
+#endif

teensy3/avr_emulation.cpp

@@ -30,5 +30,16 @@
 
 
 #include "avr_emulation.h"
+#include "SPIFIFO.h"
 
 uint8_t SPCRemulation::pinout = 0;
+
+#ifdef HAS_SPIFIFO
+
+uint8_t SPIFIFOclass::pcs = 0;
+volatile uint8_t * SPIFIFOclass::reg = 0;
+
+#endif
+
+
+