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@@ -640,9 +640,21 @@ extern "C" { |
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#define DMA_DCHPRI2 *(volatile uint8_t *)0x40008101 // Channel n Priority Register |
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#define DMA_DCHPRI1 *(volatile uint8_t *)0x40008102 // Channel n Priority Register |
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#define DMA_DCHPRI0 *(volatile uint8_t *)0x40008103 // Channel n Priority Register |
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#define DMA_DCHPRI_CHPRI(n) ((uint8_t)(n & 3)<<0) // Channel Arbitration Priority |
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#define DMA_DCHPRI_CHPRI(n) ((uint8_t)(n & 15)<<0) // Channel Arbitration Priority |
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#define DMA_DCHPRI_DPA ((uint8_t)1<<6) // Disable PreEmpt Ability |
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#define DMA_DCHPRI_ECP ((uint8_t)1<<7) // Enable PreEmption |
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#define DMA_DCHPRI7 *(volatile uint8_t *)0x40008104 // Channel n Priority Register |
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#define DMA_DCHPRI6 *(volatile uint8_t *)0x40008105 // Channel n Priority Register |
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#define DMA_DCHPRI5 *(volatile uint8_t *)0x40008106 // Channel n Priority Register |
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#define DMA_DCHPRI4 *(volatile uint8_t *)0x40008107 // Channel n Priority Register |
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#define DMA_DCHPRI11 *(volatile uint8_t *)0x40008108 // Channel n Priority Register |
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#define DMA_DCHPRI10 *(volatile uint8_t *)0x40008109 // Channel n Priority Register |
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#define DMA_DCHPRI9 *(volatile uint8_t *)0x4000810A // Channel n Priority Register |
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#define DMA_DCHPRI8 *(volatile uint8_t *)0x4000810B // Channel n Priority Register |
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#define DMA_DCHPRI15 *(volatile uint8_t *)0x4000810C // Channel n Priority Register |
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#define DMA_DCHPRI14 *(volatile uint8_t *)0x4000810D // Channel n Priority Register |
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#define DMA_DCHPRI13 *(volatile uint8_t *)0x4000810E // Channel n Priority Register |
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#define DMA_DCHPRI12 *(volatile uint8_t *)0x4000810F // Channel n Priority Register |
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#define DMA_TCD_ATTR_SMOD(n) (((n) & 0x1F) << 11) |