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Pad DMAMEM to 32 byte cache line size

teensy4-core
PaulStoffregen 4 years ago
parent
commit
bef18c9869
2 changed files with 2 additions and 2 deletions
  1. +1
    -1
      teensy4/imxrt1062.ld
  2. +1
    -1
      teensy4/imxrt1062_t41.ld

+ 1
- 1
teensy4/imxrt1062.ld View File

@@ -57,7 +57,7 @@ SECTIONS

.bss.dma (NOLOAD) : {
*(.dmabuffers)
. = ALIGN(16);
. = ALIGN(32);
} > RAM

_stext = ADDR(.text.itcm);

+ 1
- 1
teensy4/imxrt1062_t41.ld View File

@@ -58,7 +58,7 @@ SECTIONS

.bss.dma (NOLOAD) : {
*(.dmabuffers)
. = ALIGN(16);
. = ALIGN(32);
} > RAM

.bss.extram (NOLOAD) : {

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