| #define CCM_CCGR1_CSU(n) ((uint32_t)(((n) & 0x03) << 28)) | #define CCM_CCGR1_CSU(n) ((uint32_t)(((n) & 0x03) << 28)) | ||||
| #define CCM_CCGR1_GPIO1(n) ((uint32_t)(((n) & 0x03) << 26)) | #define CCM_CCGR1_GPIO1(n) ((uint32_t)(((n) & 0x03) << 26)) | ||||
| #define CCM_CCGR1_LPUART4(n) ((uint32_t)(((n) & 0x03) << 24)) | #define CCM_CCGR1_LPUART4(n) ((uint32_t)(((n) & 0x03) << 24)) | ||||
| #define CCM_CCGR1_GPT1_SERIAL(n) ((uint32_t)(((n) & 0x03) << 22)) | |||||
| #define CCM_CCGR1_GPT1_SERIAL(n) ((uint32_t)(((n) & 0x03) << 22)) | |||||
| #define CCM_CCGR1_GPT1_BUS(n) ((uint32_t)(((n) & 0x03) << 20)) | #define CCM_CCGR1_GPT1_BUS(n) ((uint32_t)(((n) & 0x03) << 20)) | ||||
| #define CCM_CCGR1_GPT(n) ((uint32_t)(((n) & 0x03) << 20)) | |||||
| #define CCM_CCGR1_ADC1(n) ((uint32_t)(((n) & 0x03) << 16)) | #define CCM_CCGR1_ADC1(n) ((uint32_t)(((n) & 0x03) << 16)) | ||||
| #define CCM_CCGR1_AOI2(n) ((uint32_t)(((n) & 0x03) << 14)) | #define CCM_CCGR1_AOI2(n) ((uint32_t)(((n) & 0x03) << 14)) | ||||
| #define CCM_CCGR1_PIT(n) ((uint32_t)(((n) & 0x03) << 12)) | #define CCM_CCGR1_PIT(n) ((uint32_t)(((n) & 0x03) << 12)) | ||||
| } while (location < end_addr); | } while (location < end_addr); | ||||
| asm("dsb"); | asm("dsb"); | ||||
| asm("isb"); | asm("isb"); | ||||
| } | |||||
| } |