Add HardwareSerial setRX(pin) & setTX(pin)

teensy3/HardwareSerial.h

 void serial_format(uint32_t format);
 void serial_end(void);
 void serial_set_transmit_pin(uint8_t pin);
+void serial_set_rx(uint8_t pin);
+void serial_set_tx(uint8_t pin);
 int serial_set_rts(uint8_t pin);
 int serial_set_cts(uint8_t pin);
 void serial_putchar(uint32_t c);
 void serial2_format(uint32_t format);
 void serial2_end(void);
 void serial2_set_transmit_pin(uint8_t pin);
+void serial2_set_rx(uint8_t pin);
+void serial2_set_tx(uint8_t pin);
 int serial2_set_rts(uint8_t pin);
 int serial2_set_cts(uint8_t pin);
 void serial2_putchar(uint32_t c);
 void serial3_format(uint32_t format);
 void serial3_end(void);
 void serial3_set_transmit_pin(uint8_t pin);
+void serial3_set_rx(uint8_t pin);
+void serial3_set_tx(uint8_t pin);
 int serial3_set_rts(uint8_t pin);
 int serial3_set_cts(uint8_t pin);
 void serial3_putchar(uint32_t c);
 					  serial_format(format); }
 	virtual void end(void)		{ serial_end(); }
 	virtual void transmitterEnable(uint8_t pin) { serial_set_transmit_pin(pin); }
+	virtual void setRX(uint8_t pin) { serial_set_rx(pin); }
+	virtual void setTX(uint8_t pin) { serial_set_tx(pin); }
 	virtual bool attachRts(uint8_t pin) { return serial_set_rts(pin); }
 	virtual bool attachCts(uint8_t pin) { return serial_set_cts(pin); }
 	virtual int available(void)     { return serial_available(); }
 					  serial2_format(format); }
 	virtual void end(void)		{ serial2_end(); }
 	virtual void transmitterEnable(uint8_t pin) { serial2_set_transmit_pin(pin); }
+	virtual void setRX(uint8_t pin) { serial2_set_rx(pin); }
+	virtual void setTX(uint8_t pin) { serial2_set_tx(pin); }
 	virtual bool attachRts(uint8_t pin) { return serial2_set_rts(pin); }
 	virtual bool attachCts(uint8_t pin) { return serial2_set_cts(pin); }
 	virtual int available(void)     { return serial2_available(); }
 					  serial3_format(format); }
 	virtual void end(void)          { serial3_end(); }
 	virtual void transmitterEnable(uint8_t pin) { serial3_set_transmit_pin(pin); }
+	virtual void setRX(uint8_t pin) { serial3_set_rx(pin); }
+	virtual void setTX(uint8_t pin) { serial3_set_tx(pin); }
 	virtual bool attachRts(uint8_t pin) { return serial3_set_rts(pin); }
 	virtual bool attachCts(uint8_t pin) { return serial3_set_cts(pin); }
 	virtual int available(void)     { return serial3_available(); }

teensy3/serial1.c

 static volatile uint8_t rx_buffer_head = 0;
 static volatile uint8_t rx_buffer_tail = 0;
 #endif
+static uint8_t rx_pin_num = 0;
+static uint8_t tx_pin_num = 1;
 
 // UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS
 // UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer
 	tx_buffer_head = 0;
 	tx_buffer_tail = 0;
 	transmitting = 0;
-	CORE_PIN0_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3);
-	CORE_PIN1_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3);
+	switch (rx_pin_num) {
+		case 0:  CORE_PIN0_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
+		case 21: CORE_PIN21_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
+		#if defined(KINETISL)
+		case 3:  CORE_PIN3_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(2); break;
+		#endif
+	}
+	switch (tx_pin_num) {
+		case 1:  CORE_PIN1_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
+		case 5:  CORE_PIN5_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
+		#if defined(KINETISL)
+		case 4:  CORE_PIN4_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(2); break;
+		#endif
+	}
 #if defined(HAS_KINETISK_UART0)
 	UART0_BDH = (divisor >> 13) & 0x1F;
 	UART0_BDL = (divisor >> 5) & 0xFF;
 	#endif
 }
 
+void serial_set_tx(uint8_t pin)
+{
+	if (pin == tx_pin_num) return;
+	if ((SIM_SCGC4 & SIM_SCGC4_UART0)) {
+		switch (tx_pin_num) {
+			case 1:  CORE_PIN1_CONFIG = 0; break; // PTB17
+			case 5:  CORE_PIN5_CONFIG = 0; break; // PTD7
+			#if defined(KINETISL)
+			case 4:  CORE_PIN4_CONFIG = 0; break; // PTA2
+			#endif
+		}
+		switch (pin) {
+			case 1:  CORE_PIN1_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
+			case 5:  CORE_PIN5_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
+			#if defined(KINETISL)
+			case 4:  CORE_PIN4_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(2); break;
+			#endif
+		}
+	}
+	tx_pin_num = pin;
+}
+
+void serial_set_rx(uint8_t pin)
+{
+	if (pin == rx_pin_num) return;
+	if ((SIM_SCGC4 & SIM_SCGC4_UART0)) {
+		switch (rx_pin_num) {
+			case 0:  CORE_PIN0_CONFIG = 0; break; // PTB16
+			case 21: CORE_PIN21_CONFIG = 0; break; // PTD6
+			#if defined(KINETISL)
+			case 3:  CORE_PIN3_CONFIG = 0; break; // PTA1
+			#endif
+		}
+		switch (pin) {
+			case 0:  CORE_PIN0_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
+			case 21: CORE_PIN21_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
+			#if defined(KINETISL)
+			case 3:  CORE_PIN3_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(2); break;
+			#endif
+		}
+	}
+	rx_pin_num = pin;
+}
+
+
+
 int serial_set_rts(uint8_t pin)
 {
 	if (!(SIM_SCGC4 & SIM_SCGC4_UART0)) return 0;

teensy3/serial2.c

 static volatile uint8_t rx_buffer_head = 0;
 static volatile uint8_t rx_buffer_tail = 0;
 #endif
+#if defined(KINETISK)
+static uint8_t rx_pin_num = 9;
+static uint8_t tx_pin_num = 10;
+#endif
 
 // UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS
 // UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer
 	tx_buffer_head = 0;
 	tx_buffer_tail = 0;
 	transmitting = 0;
+#if defined(KINETISK)
+	switch (rx_pin_num) {
+		case 9: CORE_PIN9_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
+		case 26: CORE_PIN26_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
+	}
+	switch (tx_pin_num) {
+		case 10: CORE_PIN10_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
+		case 31: CORE_PIN31_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
+	}
+#elif defined(KINETISL)
 	CORE_PIN9_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3);
 	CORE_PIN10_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3);
+#endif
 #if defined(HAS_KINETISK_UART1)
 	UART1_BDH = (divisor >> 13) & 0x1F;
 	UART1_BDL = (divisor >> 5) & 0xFF;
 	#endif
 }
 
+void serial2_set_tx(uint8_t pin)
+{
+	#if defined(KINETISK)
+	if (pin == tx_pin_num) return;
+	if ((SIM_SCGC4 & SIM_SCGC4_UART2)) {
+		switch (tx_pin_num) {
+			case 10: CORE_PIN10_CONFIG = 0; break; // PTC4
+			case 31: CORE_PIN31_CONFIG = 0; break; // PTE0
+		}
+		switch (pin) {
+			case 10: CORE_PIN10_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
+			case 31: CORE_PIN31_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
+		}
+	}
+	tx_pin_num = pin;
+	#endif
+}
+
+void serial2_set_rx(uint8_t pin)
+{
+	#if defined(KINETISK)
+	if (pin == rx_pin_num) return;
+	if ((SIM_SCGC4 & SIM_SCGC4_UART2)) {
+		switch (rx_pin_num) {
+			case 9: CORE_PIN9_CONFIG = 0; break; // PTC3
+			case 26: CORE_PIN26_CONFIG = 0; break; // PTE1
+		}
+		switch (pin) {
+			case 9: CORE_PIN9_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
+			case 26: CORE_PIN26_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
+		}
+	}
+	rx_pin_num = pin;
+	#endif
+}
+
 int serial2_set_rts(uint8_t pin)
 {
 	if (!(SIM_SCGC4 & SIM_SCGC4_UART1)) return 0;

teensy3/serial3.c

 static volatile uint8_t rx_buffer_head = 0;
 static volatile uint8_t rx_buffer_tail = 0;
 #endif
+#if defined(KINETISL)
+static uint8_t rx_pin_num = 7;
+static uint8_t tx_pin_num = 8;
+#endif
 
 // UART0 and UART1 are clocked by F_CPU, UART2 is clocked by F_BUS
 // UART0 has 8 byte fifo, UART1 and UART2 have 1 byte buffer
 	tx_buffer_head = 0;
 	tx_buffer_tail = 0;
 	transmitting = 0;
+#if defined(KINETISK)
 	CORE_PIN7_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3);
 	CORE_PIN8_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3);
+#elif defined(KINETISL)
+	switch (rx_pin_num) {
+		case 7: CORE_PIN7_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
+		case 6: CORE_PIN6_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
+	}
+	switch (tx_pin_num) {
+		case 8:  CORE_PIN8_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
+		case 20: CORE_PIN20_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
+	}
+#endif
 #if defined(HAS_KINETISK_UART2)
 	UART2_BDH = (divisor >> 13) & 0x1F;
 	UART2_BDL = (divisor >> 5) & 0xFF;
 	#endif
 }
 
+void serial3_set_tx(uint8_t pin)
+{
+	#if defined(KINETISL)
+	if (pin == tx_pin_num) return;
+	if ((SIM_SCGC4 & SIM_SCGC4_UART2)) {
+		switch (tx_pin_num) {
+			case 8:  CORE_PIN8_CONFIG = 0; break; // PTD3
+			case 20: CORE_PIN20_CONFIG = 0; break; // PTD5
+		}
+		switch (pin) {
+			case 8:  CORE_PIN8_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
+			case 20: CORE_PIN20_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
+		}
+	}
+	tx_pin_num = pin;
+	#endif
+}
+
+void serial3_set_rx(uint8_t pin)
+{
+	#if defined(KINETISL)
+	if (pin == rx_pin_num) return;
+	if ((SIM_SCGC4 & SIM_SCGC4_UART2)) {
+		switch (rx_pin_num) {
+			case 7: CORE_PIN7_CONFIG = 0; break; // PTD2
+			case 6: CORE_PIN6_CONFIG = 0; break; // PTD4
+		}
+		switch (pin) {
+			case 7: CORE_PIN7_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
+			case 6: CORE_PIN6_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
+		}
+	}
+	rx_pin_num = pin;
+	#endif
+}
+
 int serial3_set_rts(uint8_t pin)
 {
 	if (!(SIM_SCGC4 & SIM_SCGC4_UART2)) return 0;