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Add IOMUXC_GPR_GPR register defs

teensy4-core
PaulStoffregen 7 年之前
父節點
859aeb85e8
當前提交
e6550e2a8e
共有 1 個檔案被更改，包括 226 行新增 和 224 行删除
分割檢視 顯示文件統計
  1. +226
    -224
      teensy4/imxrt.h

+ 226
- 224
teensy4/imxrt.h 查看文件

@@ -1,3 +1,4 @@
#if !defined(KINETISL) && !defined(KINETISK)
enum IRQ_NUMBER_t {
IRQ_DMA_CH0 = 0,
IRQ_DMA_CH1 = 1,
@@ -160,6 +161,8 @@ enum IRQ_NUMBER_t {
IRQ_SJC_DEBUG = 158,
IRQ_NMI_WAKEUP = 159
};
#endif


typedef struct {
volatile uint32_t offset000;
@@ -2466,32 +2469,32 @@ typedef struct {

// page 1705
#define IMXRT_IOMUXC_GPR (*(IMXRT_REGISTER32_t *)0x400AC000)
#define IOMUXC_GPR_GPR0 (IMXRT_IOMUXC.offset000)
#define IOMUXC_GPR_GPR1 (IMXRT_IOMUXC.offset004)
#define IOMUXC_GPR_GPR2 (IMXRT_IOMUXC.offset008)
#define IOMUXC_GPR_GPR3 (IMXRT_IOMUXC.offset00C)
#define IOMUXC_GPR_GPR4 (IMXRT_IOMUXC.offset010)
#define IOMUXC_GPR_GPR5 (IMXRT_IOMUXC.offset014)
#define IOMUXC_GPR_GPR6 (IMXRT_IOMUXC.offset018)
#define IOMUXC_GPR_GPR7 (IMXRT_IOMUXC.offset01C)
#define IOMUXC_GPR_GPR8 (IMXRT_IOMUXC.offset020)
#define IOMUXC_GPR_GPR9 (IMXRT_IOMUXC.offset024)
#define IOMUXC_GPR_GPR10 (IMXRT_IOMUXC.offset028)
#define IOMUXC_GPR_GPR11 (IMXRT_IOMUXC.offset02C)
#define IOMUXC_GPR_GPR12 (IMXRT_IOMUXC.offset030)
#define IOMUXC_GPR_GPR13 (IMXRT_IOMUXC.offset034)
#define IOMUXC_GPR_GPR14 (IMXRT_IOMUXC.offset038)
#define IOMUXC_GPR_GPR15 (IMXRT_IOMUXC.offset03C)
#define IOMUXC_GPR_GPR16 (IMXRT_IOMUXC.offset040)
#define IOMUXC_GPR_GPR17 (IMXRT_IOMUXC.offset044)
#define IOMUXC_GPR_GPR18 (IMXRT_IOMUXC.offset048)
#define IOMUXC_GPR_GPR19 (IMXRT_IOMUXC.offset04C)
#define IOMUXC_GPR_GPR20 (IMXRT_IOMUXC.offset050)
#define IOMUXC_GPR_GPR21 (IMXRT_IOMUXC.offset054)
#define IOMUXC_GPR_GPR22 (IMXRT_IOMUXC.offset058)
#define IOMUXC_GPR_GPR23 (IMXRT_IOMUXC.offset05C)
#define IOMUXC_GPR_GPR24 (IMXRT_IOMUXC.offset060)
#define IOMUXC_GPR_GPR25 (IMXRT_IOMUXC.offset064)
#define IOMUXC_GPR_GPR0 (IMXRT_IOMUXC_GPR.offset000)
#define IOMUXC_GPR_GPR1 (IMXRT_IOMUXC_GPR.offset004)
#define IOMUXC_GPR_GPR2 (IMXRT_IOMUXC_GPR.offset008)
#define IOMUXC_GPR_GPR3 (IMXRT_IOMUXC_GPR.offset00C)
#define IOMUXC_GPR_GPR4 (IMXRT_IOMUXC_GPR.offset010)
#define IOMUXC_GPR_GPR5 (IMXRT_IOMUXC_GPR.offset014)
#define IOMUXC_GPR_GPR6 (IMXRT_IOMUXC_GPR.offset018)
#define IOMUXC_GPR_GPR7 (IMXRT_IOMUXC_GPR.offset01C)
#define IOMUXC_GPR_GPR8 (IMXRT_IOMUXC_GPR.offset020)
#define IOMUXC_GPR_GPR9 (IMXRT_IOMUXC_GPR.offset024)
#define IOMUXC_GPR_GPR10 (IMXRT_IOMUXC_GPR.offset028)
#define IOMUXC_GPR_GPR11 (IMXRT_IOMUXC_GPR.offset02C)
#define IOMUXC_GPR_GPR12 (IMXRT_IOMUXC_GPR.offset030)
#define IOMUXC_GPR_GPR13 (IMXRT_IOMUXC_GPR.offset034)
#define IOMUXC_GPR_GPR14 (IMXRT_IOMUXC_GPR.offset038)
#define IOMUXC_GPR_GPR15 (IMXRT_IOMUXC_GPR.offset03C)
#define IOMUXC_GPR_GPR16 (IMXRT_IOMUXC_GPR.offset040)
#define IOMUXC_GPR_GPR17 (IMXRT_IOMUXC_GPR.offset044)
#define IOMUXC_GPR_GPR18 (IMXRT_IOMUXC_GPR.offset048)
#define IOMUXC_GPR_GPR19 (IMXRT_IOMUXC_GPR.offset04C)
#define IOMUXC_GPR_GPR20 (IMXRT_IOMUXC_GPR.offset050)
#define IOMUXC_GPR_GPR21 (IMXRT_IOMUXC_GPR.offset054)
#define IOMUXC_GPR_GPR22 (IMXRT_IOMUXC_GPR.offset058)
#define IOMUXC_GPR_GPR23 (IMXRT_IOMUXC_GPR.offset05C)
#define IOMUXC_GPR_GPR24 (IMXRT_IOMUXC_GPR.offset060)
#define IOMUXC_GPR_GPR25 (IMXRT_IOMUXC_GPR.offset064)
#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN ((uint32_t)0x80000000)
#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN ((uint32_t)0x00800000)
#define IOMUXC_GPR_GPR1_EXC_MON ((uint32_t)0x00400000)
@@ -2523,204 +2526,203 @@ typedef struct {
#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP ((uint32_t)0x00004000)
#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING ((uint32_t)0x00001000)
#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK IOMUXC_GPR_GPR2_MQS_CLK_DIV(255)
#define IOMUXC_GPR_GPR3_OCRAM_STATUS(n)
#define IOMUXC_GPR_GPR3_DCP_KEY_SEL
#define IOMUXC_GPR_GPR3_OCRAM_CTL(n)
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK
#define IOMUXC_GPR_GPR4_PIT_STOP_ACK
#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK
#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK
#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK
#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK
#define IOMUXC_GPR_GPR4_ENET_STOP_ACK
#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK
#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK
#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK
#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ
#define IOMUXC_GPR_GPR4_PIT_STOP_REQ
#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ
#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ
#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ
#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ
#define IOMUXC_GPR_GPR4_ENET_STOP_REQ
#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ
#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ
#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ
#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1
#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL
#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL
#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL
#define IOMUXC_GPR_GPR5_WDOG2_MASK
#define IOMUXC_GPR_GPR5_WDOG1_MASK
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4
#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL
#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL
#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL
#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL
#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL
#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL
#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL
#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL
#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL
#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL
#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL
#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL
#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL
#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL
#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL
#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL
#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK
#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK
#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK
#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK
#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK
#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK
#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK
#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK
#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ
#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ
#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ
#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ
#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ
#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ
#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ
#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ
#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE
#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE
#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE
#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE
#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE
#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE
#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE
#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE
#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE
#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE
#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE
#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE
#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE
#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE
#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE
#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(n)
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN
#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX
#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP
#define IOMUXC_GPR_GPR10_LOCK_DBG_EN
#define IOMUXC_GPR_GPR10_LOCK_NIDEN
#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(n)
#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN
#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX
#define IOMUXC_GPR_GPR10_SEC_ERR_RESP
#define IOMUXC_GPR_GPR10_DBG_EN
#define IOMUXC_GPR_GPR10_NIDEN
#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN(n)
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL(n)
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL(n)
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL(n)
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL(n)
#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN(n)
#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(n)
#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(n)
#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(n)
#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(n)
#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE
#define IOMUXC_GPR_GPR13_CACHE_USB
#define IOMUXC_GPR_GPR13_CACHE_ENET
#define IOMUXC_GPR_GPR13_AWCACHE_USDHC
#define IOMUXC_GPR_GPR13_ARCACHE_USDHC
#define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ(n)
#define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ(n)
#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN
#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN
#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN
#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN
#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR(n)
#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL
#define IOMUXC_GPR_GPR16_INIT_DTCM_EN
#define IOMUXC_GPR_GPR16_INIT_ITCM_EN
#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(n)
#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(n)
#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT
#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(n)
#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP
#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(n)
#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT
#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(n)
#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP
#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(n)
#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT
#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(n)
#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP
#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT(n)
#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT
#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(n)
#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP
#define IOMUXC_GPR_GPR3_OCRAM_STATUS(n) ((uint32_t)(((n) & 0x0F) << 16))
#define IOMUXC_GPR_GPR3_DCP_KEY_SEL ((uint32_t)0x00000010)
#define IOMUXC_GPR_GPR3_OCRAM_CTL(n) ((uint32_t)(((n) & 0x0F) << 0))
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK ((uint32_t)0x20000000)
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK ((uint32_t)0x10000000)
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK ((uint32_t)0x08000000)
#define IOMUXC_GPR_GPR4_PIT_STOP_ACK ((uint32_t)0x04000000)
#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK ((uint32_t)0x02000000)
#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK ((uint32_t)0x00800000)
#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK ((uint32_t)0x00400000)
#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK ((uint32_t)0x00200000)
#define IOMUXC_GPR_GPR4_ENET_STOP_ACK ((uint32_t)0x00100000)
#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK ((uint32_t)0x00080000)
#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK ((uint32_t)0x00040000)
#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK ((uint32_t)0x00020000)
#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK ((uint32_t)0x00010000)
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ ((uint32_t)0x00002000)
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ ((uint32_t)0x00001000)
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ ((uint32_t)0x00000800)
#define IOMUXC_GPR_GPR4_PIT_STOP_REQ ((uint32_t)0x00000400)
#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ ((uint32_t)0x00000200)
#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ ((uint32_t)0x00000080)
#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ ((uint32_t)0x00000040)
#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ ((uint32_t)0x00000020)
#define IOMUXC_GPR_GPR4_ENET_STOP_REQ ((uint32_t)0x00000010)
#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ ((uint32_t)0x00000008)
#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ ((uint32_t)0x00000004)
#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ ((uint32_t)0x00000002)
#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2 ((uint32_t)0x20000000)
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1 ((uint32_t)0x10000000)
#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL ((uint32_t)0x02000000)
#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL ((uint32_t)0x01000000)
#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL ((uint32_t)0x00800000)
#define IOMUXC_GPR_GPR5_WDOG2_MASK ((uint32_t)0x00000080)
#define IOMUXC_GPR_GPR5_WDOG1_MASK ((uint32_t)0x00000040)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19 ((uint32_t)0x80000000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18 ((uint32_t)0x40000000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17 ((uint32_t)0x20000000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16 ((uint32_t)0x10000000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15 ((uint32_t)0x08000000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14 ((uint32_t)0x04000000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13 ((uint32_t)0x02000000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12 ((uint32_t)0x01000000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11 ((uint32_t)0x00800000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10 ((uint32_t)0x00400000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9 ((uint32_t)0x00200000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8 ((uint32_t)0x00100000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7 ((uint32_t)0x00080000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6 ((uint32_t)0x00040000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5 ((uint32_t)0x00020000)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4 ((uint32_t)0x00010000)
#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL ((uint32_t)0x00008000)
#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL ((uint32_t)0x00004000)
#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL ((uint32_t)0x00002000)
#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL ((uint32_t)0x00001000)
#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL ((uint32_t)0x00000800)
#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL ((uint32_t)0x00000400)
#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL ((uint32_t)0x00000200)
#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL ((uint32_t)0x00000100)
#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL ((uint32_t)0x00000080)
#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL ((uint32_t)0x00000040)
#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL ((uint32_t)0x00000020)
#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL ((uint32_t)0x00000010)
#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL ((uint32_t)0x00000008)
#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL ((uint32_t)0x00000004)
#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL ((uint32_t)0x00000002)
#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK ((uint32_t)0x80000000)
#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK ((uint32_t)0x40000000)
#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK ((uint32_t)0x20000000)
#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK ((uint32_t)0x10000000)
#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK ((uint32_t)0x08000000)
#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK ((uint32_t)0x04000000)
#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK ((uint32_t)0x02000000)
#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK ((uint32_t)0x01000000)
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK ((uint32_t)0x00800000)
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK ((uint32_t)0x00400000)
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK ((uint32_t)0x00200000)
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK ((uint32_t)0x00100000)
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK ((uint32_t)0x00080000)
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK ((uint32_t)0x00040000)
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK ((uint32_t)0x00020000)
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK ((uint32_t)0x00010000)
#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ ((uint32_t)0x00008000)
#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ ((uint32_t)0x00004000)
#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ ((uint32_t)0x00002000)
#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ ((uint32_t)0x00001000)
#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ ((uint32_t)0x00000800)
#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ ((uint32_t)0x00000400)
#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ ((uint32_t)0x00000200)
#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ ((uint32_t)0x00000100)
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ ((uint32_t)0x00000080)
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ ((uint32_t)0x00000040)
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ ((uint32_t)0x00000020)
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ ((uint32_t)0x00000010)
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ ((uint32_t)0x00000008)
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ ((uint32_t)0x00000004)
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ ((uint32_t)0x00000002)
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE ((uint32_t)0x80000000)
#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE ((uint32_t)0x40000000)
#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE ((uint32_t)0x20000000)
#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE ((uint32_t)0x10000000)
#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE ((uint32_t)0x08000000)
#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE ((uint32_t)0x04000000)
#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE ((uint32_t)0x02000000)
#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE ((uint32_t)0x01000000)
#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE ((uint32_t)0x00800000)
#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE ((uint32_t)0x00400000)
#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE ((uint32_t)0x00200000)
#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE ((uint32_t)0x00100000)
#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE ((uint32_t)0x00080000)
#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE ((uint32_t)0x00040000)
#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE ((uint32_t)0x00020000)
#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE ((uint32_t)0x00010000)
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE ((uint32_t)0x00008000)
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE ((uint32_t)0x00004000)
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE ((uint32_t)0x00002000)
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE ((uint32_t)0x00001000)
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE ((uint32_t)0x00000800)
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE ((uint32_t)0x00000400)
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE ((uint32_t)0x00000200)
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE ((uint32_t)0x00000100)
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE ((uint32_t)0x00000080)
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE ((uint32_t)0x00000040)
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE ((uint32_t)0x00000020)
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE ((uint32_t)0x00000010)
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE ((uint32_t)0x00000008)
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE ((uint32_t)0x00000004)
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE ((uint32_t)0x00000002)
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(n) ((uint32_t)(((n) & 0x7F) << 25))
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN ((uint32_t)0x01000000)
#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX ((uint32_t)0x00100000)
#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP ((uint32_t)0x00040000)
#define IOMUXC_GPR_GPR10_LOCK_DBG_EN ((uint32_t)0x00020000)
#define IOMUXC_GPR_GPR10_LOCK_NIDEN ((uint32_t)0x00010000)
#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(n) ((uint32_t)(((n) & 0x7F) << 9))
#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN ((uint32_t)0x00000100)
#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX ((uint32_t)0x00000010)
#define IOMUXC_GPR_GPR10_SEC_ERR_RESP ((uint32_t)0x00000004)
#define IOMUXC_GPR_GPR10_DBG_EN ((uint32_t)0x00000002)
#define IOMUXC_GPR_GPR10_NIDEN ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN(n) ((uint32_t)(((n) & 0x0F) << 24))
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL(n) ((uint32_t)(((n) & 0x03) << 22))
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL(n) ((uint32_t)(((n) & 0x03) << 20))
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL(n) ((uint32_t)(((n) & 0x03) << 18))
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL(n) ((uint32_t)(((n) & 0x03) << 16))
#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN(n) ((uint32_t)(((n) & 0x0F) << 8))
#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(n) ((uint32_t)(((n) & 0x03) << 6))
#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(n) ((uint32_t)(((n) & 0x03) << 4))
#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(n) ((uint32_t)(((n) & 0x03) << 2))
#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(n) ((uint32_t)(((n) & 0x03) << 0))
#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE ((uint32_t)0x00000010)
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE ((uint32_t)0x00000008)
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE ((uint32_t)0x00000004)
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE ((uint32_t)0x00000002)
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR13_CACHE_USB ((uint32_t)0x00002000)
#define IOMUXC_GPR_GPR13_CACHE_ENET ((uint32_t)0x00000080)
#define IOMUXC_GPR_GPR13_AWCACHE_USDHC ((uint32_t)0x00000002)
#define IOMUXC_GPR_GPR13_ARCACHE_USDHC ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ(n) ((uint32_t)(((n) & 0x0F) << 20))
#define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ(n) ((uint32_t)(((n) & 0x0F) << 16))
#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN ((uint32_t)0x00000800)
#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN ((uint32_t)0x00000400)
#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN ((uint32_t)0x00000200)
#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN ((uint32_t)0x00000100)
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP ((uint32_t)0x00000080)
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP ((uint32_t)0x00000040)
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP ((uint32_t)0x00000020)
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP ((uint32_t)0x00000010)
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN ((uint32_t)0x00000008)
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN ((uint32_t)0x00000004)
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN ((uint32_t)0x00000002)
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR(n) ((uint32_t)(((n) & 0x1FFFFFF) << 7))
#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL ((uint32_t)0x00000004)
#define IOMUXC_GPR_GPR16_INIT_DTCM_EN ((uint32_t)0x00000002)
#define IOMUXC_GPR_GPR16_INIT_ITCM_EN ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(n) ((uint32_t)(((n) & 0x1FFFFFFF) << 3))
#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(n) ((uint32_t)(((n) & 0x1FFFFFFF) << 3))
#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(n) ((uint32_t)(((n) & 0x1FFFFFFF) << 3))
#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(n) ((uint32_t)(((n) & 0x1FFFFFFF) << 3))
#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(n) ((uint32_t)(((n) & 0x1FFFFFFF) << 3))
#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(n) ((uint32_t)(((n) & 0x1FFFFFFF) << 3))
#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT(n) ((uint32_t)(((n) & 0x1FFFFFFF) << 3))
#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT ((uint32_t)0x00000001)
#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(n) ((uint32_t)(((n) & 0x1FFFFFFF) << 3))
#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP ((uint32_t)0x00000001)

// page 1750
#define IMXRT_IOMUXC_SNVS (*(IMXRT_REGISTER32_t *)0x400A8000)

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