Update pins 30 and 31 in core_pins.h

The B2 board has different IO pins here for these two pins

teensy4/core_pins.h

@@ -86,8 +86,8 @@
 #define CORE_PIN27_BIT		31
 #define CORE_PIN28_BIT		18
 #define CORE_PIN29_BIT		31
-#define CORE_PIN30_BIT		24
-#define CORE_PIN31_BIT		23
+#define CORE_PIN30_BIT		23
+#define CORE_PIN31_BIT		22
 #define CORE_PIN32_BIT		12
 #define CORE_PIN33_BIT		7
 #define CORE_PIN34_BIT		15
@@ -171,8 +171,8 @@
 #define CORE_PIN27_PORTREG	GPIO6_DR
 #define CORE_PIN28_PORTREG	GPIO8_DR
 #define CORE_PIN29_PORTREG	GPIO9_DR
-#define CORE_PIN30_PORTREG	GPIO9_DR
-#define CORE_PIN31_PORTREG	GPIO9_DR
+#define CORE_PIN30_PORTREG	GPIO8_DR
+#define CORE_PIN31_PORTREG	GPIO8_DR
 #define CORE_PIN32_PORTREG	GPIO7_DR
 #define CORE_PIN33_PORTREG	GPIO9_DR
 #define CORE_PIN34_PORTREG	GPIO8_DR
@@ -212,8 +212,8 @@
 #define CORE_PIN27_PORTSET	GPIO6_DR_SET
 #define CORE_PIN28_PORTSET	GPIO8_DR_SET
 #define CORE_PIN29_PORTSET	GPIO9_DR_SET
-#define CORE_PIN30_PORTSET	GPIO9_DR_SET
-#define CORE_PIN31_PORTSET	GPIO9_DR_SET
+#define CORE_PIN30_PORTSET	GPIO8_DR_SET
+#define CORE_PIN31_PORTSET	GPIO8_DR_SET
 #define CORE_PIN32_PORTSET	GPIO7_DR_SET
 #define CORE_PIN33_PORTSET	GPIO9_DR_SET
 #define CORE_PIN34_PORTSET	GPIO8_DR_SET
@@ -253,8 +253,8 @@
 #define CORE_PIN27_PORTCLEAR	GPIO6_DR_CLEAR
 #define CORE_PIN28_PORTCLEAR	GPIO8_DR_CLEAR
 #define CORE_PIN29_PORTCLEAR	GPIO9_DR_CLEAR
-#define CORE_PIN30_PORTCLEAR	GPIO9_DR_CLEAR
-#define CORE_PIN31_PORTCLEAR	GPIO9_DR_CLEAR
+#define CORE_PIN30_PORTCLEAR	GPIO8_DR_CLEAR
+#define CORE_PIN31_PORTCLEAR	GPIO8_DR_CLEAR
 #define CORE_PIN32_PORTCLEAR	GPIO7_DR_CLEAR
 #define CORE_PIN33_PORTCLEAR	GPIO9_DR_CLEAR
 #define CORE_PIN34_PORTCLEAR	GPIO8_DR_CLEAR
@@ -294,8 +294,8 @@
 #define CORE_PIN27_DDRREG	GPIO6_GDIR
 #define CORE_PIN28_DDRREG	GPIO8_GDIR
 #define CORE_PIN29_DDRREG	GPIO9_GDIR
-#define CORE_PIN30_DDRREG	GPIO9_GDIR
-#define CORE_PIN31_DDRREG	GPIO9_GDIR
+#define CORE_PIN30_DDRREG	GPIO8_GDIR
+#define CORE_PIN31_DDRREG	GPIO8_GDIR
 #define CORE_PIN32_DDRREG	GPIO7_GDIR
 #define CORE_PIN33_DDRREG	GPIO9_GDIR
 #define CORE_PIN34_DDRREG	GPIO8_GDIR
@@ -335,8 +335,8 @@
 #define CORE_PIN27_PINREG	GPIO6_PSR
 #define CORE_PIN28_PINREG	GPIO8_PSR
 #define CORE_PIN29_PINREG	GPIO9_PSR
-#define CORE_PIN30_PINREG	GPIO9_PSR
-#define CORE_PIN31_PINREG	GPIO9_PSR
+#define CORE_PIN30_PINREG	GPIO8_PSR
+#define CORE_PIN31_PINREG	GPIO8_PSR
 #define CORE_PIN32_PINREG	GPIO7_PSR
 #define CORE_PIN33_PINREG	GPIO9_PSR
 #define CORE_PIN34_PINREG	GPIO8_PSR
@@ -379,8 +379,8 @@
 #define CORE_PIN27_PORTREG	GPIO1_DR
 #define CORE_PIN28_PORTREG	GPIO3_DR
 #define CORE_PIN29_PORTREG	GPIO4_DR
-#define CORE_PIN30_PORTREG	GPIO4_DR
-#define CORE_PIN31_PORTREG	GPIO4_DR
+#define CORE_PIN30_PORTREG	GPIO3_DR
+#define CORE_PIN31_PORTREG	GPIO3_DR
 #define CORE_PIN32_PORTREG	GPIO2_DR
 #define CORE_PIN33_PORTREG	GPIO4_DR
 #define CORE_PIN34_PORTREG	GPIO3_DR
@@ -420,8 +420,8 @@
 #define CORE_PIN27_PORTSET	GPIO1_DR_SET
 #define CORE_PIN28_PORTSET	GPIO3_DR_SET
 #define CORE_PIN29_PORTSET	GPIO4_DR_SET
-#define CORE_PIN30_PORTSET	GPIO4_DR_SET
-#define CORE_PIN31_PORTSET	GPIO4_DR_SET
+#define CORE_PIN30_PORTSET	GPIO3_DR_SET
+#define CORE_PIN31_PORTSET	GPIO3_DR_SET
 #define CORE_PIN32_PORTSET	GPIO2_DR_SET
 #define CORE_PIN33_PORTSET	GPIO4_DR_SET
 #define CORE_PIN34_PORTSET	GPIO3_DR_SET
@@ -461,8 +461,8 @@
 #define CORE_PIN27_PORTCLEAR	GPIO1_DR_CLEAR
 #define CORE_PIN28_PORTCLEAR	GPIO3_DR_CLEAR
 #define CORE_PIN29_PORTCLEAR	GPIO4_DR_CLEAR
-#define CORE_PIN30_PORTCLEAR	GPIO4_DR_CLEAR
-#define CORE_PIN31_PORTCLEAR	GPIO4_DR_CLEAR
+#define CORE_PIN30_PORTCLEAR	GPIO3_DR_CLEAR
+#define CORE_PIN31_PORTCLEAR	GPIO3_DR_CLEAR
 #define CORE_PIN32_PORTCLEAR	GPIO2_DR_CLEAR
 #define CORE_PIN33_PORTCLEAR	GPIO4_DR_CLEAR
 #define CORE_PIN34_PORTCLEAR	GPIO3_DR_CLEAR
@@ -502,8 +502,8 @@
 #define CORE_PIN27_DDRREG	GPIO1_GDIR
 #define CORE_PIN28_DDRREG	GPIO3_GDIR
 #define CORE_PIN29_DDRREG	GPIO4_GDIR
-#define CORE_PIN30_DDRREG	GPIO4_GDIR
-#define CORE_PIN31_DDRREG	GPIO4_GDIR
+#define CORE_PIN30_DDRREG	GPIO3_GDIR
+#define CORE_PIN31_DDRREG	GPIO3_GDIR
 #define CORE_PIN32_DDRREG	GPIO2_GDIR
 #define CORE_PIN33_DDRREG	GPIO4_GDIR
 #define CORE_PIN34_DDRREG	GPIO3_GDIR
@@ -543,8 +543,8 @@
 #define CORE_PIN27_PINREG	GPIO1_PSR
 #define CORE_PIN28_PINREG	GPIO3_PSR
 #define CORE_PIN29_PINREG	GPIO4_PSR
-#define CORE_PIN30_PINREG	GPIO4_PSR
-#define CORE_PIN31_PINREG	GPIO4_PSR
+#define CORE_PIN30_PINREG	GPIO3_PSR
+#define CORE_PIN31_PINREG	GPIO3_PSR
 #define CORE_PIN32_PINREG	GPIO2_PSR
 #define CORE_PIN33_PINREG	GPIO4_PSR
 #define CORE_PIN34_PINREG	GPIO3_PSR
@@ -587,8 +587,8 @@
 #define CORE_PIN27_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15
 #define CORE_PIN28_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32
 #define CORE_PIN29_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31
-#define CORE_PIN30_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24
-#define CORE_PIN31_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23
+#define CORE_PIN30_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37
+#define CORE_PIN31_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36
 #define CORE_PIN32_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12
 #define CORE_PIN33_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07
 #define CORE_PIN34_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03
@@ -629,8 +629,8 @@
 #define CORE_PIN27_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15
 #define CORE_PIN28_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32
 #define CORE_PIN29_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31
-#define CORE_PIN30_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24
-#define CORE_PIN31_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23
+#define CORE_PIN30_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37
+#define CORE_PIN31_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36
 #define CORE_PIN32_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12
 #define CORE_PIN33_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07
 #define CORE_PIN34_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03