Always define the SD card pins - do it like we mean it!

teensy3/avr_emulation.h

 		return ret;
 	}
 	inline void setMOSI(uint8_t pin) __attribute__((always_inline)) {
-#ifdef USE_SDCARD_PINS
 		// More options, so 2 bits
 		pinout &= ~3;
 		switch (pin) {
 			case 61: pinout |= 2; break;
 			case 59: pinout |= 3; break;
 		}
-#else
-		if (pin == 0) pinout &= ~1; // MOSI1 = 0  (PTB16)
-		if (pin == 21) pinout |= 1; // MOSI1 = 21 (PTD6)
-#endif
 	}
 	inline void setMISO(uint8_t pin) __attribute__((always_inline)) {
-#ifdef USE_SDCARD_PINS
 		// More options, so 2 bits
 		pinout &= ~0xc;
 		switch (pin) {
 			case 61: pinout |= 0x8; break;
 			case 59: pinout |= 0xc; break;
 		}
-#else
-		if (pin == 1) pinout &= ~2; // MISO1 = 1  (PTB17)
-		if (pin == 5) pinout |= 2;  // MISO1 = 5  (PTD7)
-#endif		
 	}
 	inline void setSCK(uint8_t pin) __attribute__((always_inline)) {
-#ifdef USE_SDCARD_PINS
 		// More options, so 2 bits
 		pinout &= ~0x30;
 		switch (pin) {
 			case 32: pinout |= 0x10; break; 
 			case 60: pinout |= 0x20; break;
 		}
-#else
-		if (pin == 20) pinout &= ~4; // SCK = 20  (PTD5)
-		if (pin == 32) pinout |= 4;  // MISO1 = 32  (PTB11)
-#endif
 	}
 	inline void enable_pins(void) __attribute__((always_inline)) {
 		//serial_print("enable_pins\n");
-#ifdef USE_SDCARD_PINS
 		// MOSI (SOUT)
 		switch (pinout & 0x3) {
 			case 0: CORE_PIN0_CONFIG = PORT_PCR_MUX(2); break;
 			case 0x10: CORE_PIN32_CONFIG = PORT_PCR_MUX(2); break;
 			case 0x20: CORE_PIN60_CONFIG = PORT_PCR_MUX(2); break;
 		}
-
-#else
-		if ((pinout & 1) == 0) {
-			CORE_PIN0_CONFIG = PORT_PCR_MUX(2);  // MOSI1 = 0  (PTB16)
-		} else {
-			CORE_PIN21_CONFIG = PORT_PCR_MUX(7); // MOSI1 = 21 (PTD6)
-		}
-		if ((pinout & 2) == 0) {
-			CORE_PIN1_CONFIG = PORT_PCR_MUX(2);  // MISO1 = 1  (PTB17)
-		} else {
-			CORE_PIN5_CONFIG = PORT_PCR_MUX(7);  // MISO1 = 5  (PTD7)
-		}
-		if ((pinout & 4) == 0) {
-			CORE_PIN20_CONFIG = PORT_PCR_MUX(7); // SCK1 = 20 (PTD5)
-		} else {
-			CORE_PIN32_CONFIG = PORT_PCR_MUX(2);  // MISO1 = 5  (PTD7)
-		}
-#endif
 	}
 	inline void disable_pins(void) __attribute__((always_inline)) {
-#ifdef USE_SDCARD_PINS
 		switch (pinout & 0x3) {
 			case 0: CORE_PIN0_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1); break;
 			case 1: CORE_PIN21_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1); break;
 			case 0x10: CORE_PIN32_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1); break;
 			case 0x20: CORE_PIN60_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1); break;
 		}
-#else
-		//serial_print("disable_pins\n");
-		if ((pinout & 1) == 0) {
-			CORE_PIN0_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1);
-		} else {
-			CORE_PIN21_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1);
-		}
-		if ((pinout & 2) == 0) {
-			CORE_PIN1_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1);
-		} else {
-			CORE_PIN5_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1);
-		}
-		if ((pinout & 4) == 0) {
-			CORE_PIN20_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1); // SCK1 = 20 (PTD5)
-		} else {
-			CORE_PIN32_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1);  // MISO1 = 5  (PTD7)
-		}
-#endif
 	}
 	friend class SPIFIFO1class;
 private:

teensy3/core_pins.h

 #include "kinetis.h"
 #include "pins_arduino.h"
 
-// TESTING: Use the SDCARD pins on T3.5 beta for other purposes. 
-#define USE_SDCARD_PINS
-
 #define HIGH		1
 #define LOW		0
 #define INPUT		0
 #define CORE_NUM_ANALOG         13
 #define CORE_NUM_PWM            10
 #elif defined(__MK64FX512__) || defined(__MK66FX1M0__)
-#ifdef USE_SDCARD_PINS
 #define CORE_NUM_TOTAL_PINS     64
 #define CORE_NUM_DIGITAL        64
 #define CORE_NUM_INTERRUPT      64
-#else
-#define CORE_NUM_TOTAL_PINS     58
-#define CORE_NUM_DIGITAL        58
-#define CORE_NUM_INTERRUPT      58
-#endif 
 #define CORE_NUM_ANALOG         23
 #define CORE_NUM_PWM            20
 #endif
 #define CORE_PIN55_BIT		11
 #define CORE_PIN56_BIT		10
 #define CORE_PIN57_BIT		11
-#ifdef USE_SDCARD_PINS
 #define CORE_PIN58_BIT		0
 #define CORE_PIN59_BIT		1
 #define CORE_PIN60_BIT		2
 #define CORE_PIN61_BIT		3
 #define CORE_PIN62_BIT		4
 #define CORE_PIN63_BIT		5
-#endif
 
 #define CORE_PIN0_BITMASK	(1<<(CORE_PIN0_BIT))
 #define CORE_PIN1_BITMASK	(1<<(CORE_PIN1_BIT))
 #define CORE_PIN55_BITMASK	(1<<(CORE_PIN55_BIT))
 #define CORE_PIN56_BITMASK	(1<<(CORE_PIN56_BIT))
 #define CORE_PIN57_BITMASK	(1<<(CORE_PIN57_BIT))
-#ifdef USE_SDCARD_PINS
 #define CORE_PIN58_BITMASK	(1<<(CORE_PIN58_BIT))
 #define CORE_PIN59_BITMASK	(1<<(CORE_PIN59_BIT))
 #define CORE_PIN60_BITMASK	(1<<(CORE_PIN60_BIT))
 #define CORE_PIN61_BITMASK	(1<<(CORE_PIN61_BIT))
 #define CORE_PIN62_BITMASK	(1<<(CORE_PIN62_BIT))
 #define CORE_PIN63_BITMASK	(1<<(CORE_PIN63_BIT))
-#endif
 
 
 #define CORE_PIN0_PORTREG	GPIOB_PDOR
 #define CORE_PIN55_PORTREG	GPIOD_PDOR
 #define CORE_PIN56_PORTREG	GPIOE_PDOR
 #define CORE_PIN57_PORTREG	GPIOE_PDOR
-#ifdef USE_SDCARD_PINS
 #define CORE_PIN58_PORTREG	GPIOE_PDOR
 #define CORE_PIN59_PORTREG	GPIOE_PDOR
 #define CORE_PIN60_PORTREG	GPIOE_PDOR
 #define CORE_PIN61_PORTREG	GPIOE_PDOR
 #define CORE_PIN62_PORTREG	GPIOE_PDOR
 #define CORE_PIN63_PORTREG	GPIOE_PDOR
-#endif
 
 #define CORE_PIN0_PORTSET	GPIOB_PSOR
 #define CORE_PIN1_PORTSET	GPIOB_PSOR
 #define CORE_PIN55_PORTSET	GPIOD_PSOR
 #define CORE_PIN56_PORTSET	GPIOE_PSOR
 #define CORE_PIN57_PORTSET	GPIOE_PSOR
-#ifdef USE_SDCARD_PINS
 #define CORE_PIN58_PORTSET	GPIOE_PSOR
 #define CORE_PIN59_PORTSET	GPIOE_PSOR
 #define CORE_PIN60_PORTSET	GPIOE_PSOR
 #define CORE_PIN61_PORTSET	GPIOE_PSOR
 #define CORE_PIN62_PORTSET	GPIOE_PSOR
 #define CORE_PIN63_PORTSET	GPIOE_PSOR
-#endif
 
 #define CORE_PIN0_PORTCLEAR	GPIOB_PCOR
 #define CORE_PIN1_PORTCLEAR	GPIOB_PCOR
 #define CORE_PIN55_PORTCLEAR	GPIOD_PCOR
 #define CORE_PIN56_PORTCLEAR	GPIOE_PCOR
 #define CORE_PIN57_PORTCLEAR	GPIOE_PCOR
-#ifdef USE_SDCARD_PINS
 #define CORE_PIN58_PORTCLEAR	GPIOE_PCOR
 #define CORE_PIN59_PORTCLEAR	GPIOE_PCOR
 #define CORE_PIN60_PORTCLEAR	GPIOE_PCOR
 #define CORE_PIN61_PORTCLEAR	GPIOE_PCOR
 #define CORE_PIN62_PORTCLEAR	GPIOE_PCOR
 #define CORE_PIN63_PORTCLEAR	GPIOE_PCOR
-#endif
 
 #define CORE_PIN0_DDRREG	GPIOB_PDDR
 #define CORE_PIN1_DDRREG	GPIOB_PDDR
 #define CORE_PIN55_DDRREG	GPIOD_PDDR
 #define CORE_PIN56_DDRREG	GPIOE_PDDR
 #define CORE_PIN57_DDRREG	GPIOE_PDDR
-#ifdef USE_SDCARD_PINS
 #define CORE_PIN58_DDRREG	GPIOE_PDDR
 #define CORE_PIN59_DDRREG	GPIOE_PDDR
 #define CORE_PIN60_DDRREG	GPIOE_PDDR
 #define CORE_PIN61_DDRREG	GPIOE_PDDR
 #define CORE_PIN62_DDRREG	GPIOE_PDDR
 #define CORE_PIN63_DDRREG	GPIOE_PDDR
-#endif
 
 #define CORE_PIN0_PINREG	GPIOB_PDIR
 #define CORE_PIN1_PINREG	GPIOB_PDIR
 #define CORE_PIN55_PINREG	GPIOD_PDIR
 #define CORE_PIN56_PINREG	GPIOE_PDIR
 #define CORE_PIN57_PINREG	GPIOE_PDIR
-#ifdef USE_SDCARD_PINS
 #define CORE_PIN58_PINREG	GPIOE_PDIR
 #define CORE_PIN59_PINREG	GPIOE_PDIR
 #define CORE_PIN60_PINREG	GPIOE_PDIR
 #define CORE_PIN61_PINREG	GPIOE_PDIR
 #define CORE_PIN62_PINREG	GPIOE_PDIR
 #define CORE_PIN63_PINREG	GPIOE_PDIR
-#endif
 
 #define CORE_PIN0_CONFIG	PORTB_PCR16
 #define CORE_PIN1_CONFIG	PORTB_PCR17
 #define CORE_PIN55_CONFIG	PORTD_PCR11
 #define CORE_PIN56_CONFIG	PORTE_PCR10
 #define CORE_PIN57_CONFIG	PORTE_PCR11
-#ifdef USE_SDCARD_PINS
 #define CORE_PIN58_CONFIG	PORTE_PCR0
 #define CORE_PIN59_CONFIG	PORTE_PCR1
 #define CORE_PIN60_CONFIG	PORTE_PCR2
 #define CORE_PIN61_CONFIG	PORTE_PCR3
 #define CORE_PIN62_CONFIG	PORTE_PCR4
 #define CORE_PIN63_CONFIG	PORTE_PCR5
-#endif
 
 #define CORE_ADC0_PIN		14
 #define CORE_ADC1_PIN		15
 #define CORE_INT55_PIN		55
 #define CORE_INT56_PIN		56
 #define CORE_INT57_PIN		57
-#ifdef USE_SDCARD_PINS
 #define CORE_INT58_PIN		58
 #define CORE_INT59_PIN		59
 #define CORE_INT60_PIN		60
 #define CORE_INT61_PIN		61
 #define CORE_INT62_PIN		62
 #define CORE_INT63_PIN		63
-#endif
 #define CORE_INT_EVERY_PIN	1
 
 #endif
 				CORE_PIN56_PORTSET = CORE_PIN56_BITMASK;
 			} else if (pin == 57) {
 				CORE_PIN57_PORTSET = CORE_PIN57_BITMASK;
-			#ifdef USE_SDCARD_PINS
 			} else if (pin == 58) {
 				CORE_PIN58_PORTSET = CORE_PIN58_BITMASK;
 			} else if (pin == 59) {
 				CORE_PIN62_PORTSET = CORE_PIN62_BITMASK;
 			} else if (pin == 63) {
 				CORE_PIN63_PORTSET = CORE_PIN63_BITMASK;
-
-			#endif
 			}
 			#endif
 		} else {
 				CORE_PIN56_PORTCLEAR = CORE_PIN56_BITMASK;
 			} else if (pin == 57) {
 				CORE_PIN57_PORTCLEAR = CORE_PIN57_BITMASK;
-			#ifdef USE_SDCARD_PINS
 			} else if (pin == 58) {
 				CORE_PIN58_PORTCLEAR = CORE_PIN58_BITMASK;
 			} else if (pin == 59) {
 				CORE_PIN62_PORTCLEAR = CORE_PIN62_BITMASK;
 			} else if (pin == 63) {
 				CORE_PIN63_PORTCLEAR = CORE_PIN63_BITMASK;
-
-			#endif
 			}
 			#endif
 		}
 			return (CORE_PIN56_PINREG & CORE_PIN56_BITMASK) ? 1 : 0;
 		} else if (pin == 57) {
 			return (CORE_PIN57_PINREG & CORE_PIN57_BITMASK) ? 1 : 0;
-		#ifdef USE_SDCARD_PINS
 		} else if (pin == 58) {
 			return (CORE_PIN58_PINREG & CORE_PIN58_BITMASK) ? 1 : 0;
 		} else if (pin == 59) {
 			return (CORE_PIN62_PINREG & CORE_PIN62_BITMASK) ? 1 : 0;
 		} else if (pin == 63) {
 			return (CORE_PIN63_PINREG & CORE_PIN63_BITMASK) ? 1 : 0;
-
-		#endif
 		}
 		#endif
 		  else {

teensy3/pins_teensy.c

 	{GPIO_BITBAND_PTR(CORE_PIN55_PORTREG, CORE_PIN55_BIT), &CORE_PIN55_CONFIG},
 	{GPIO_BITBAND_PTR(CORE_PIN56_PORTREG, CORE_PIN56_BIT), &CORE_PIN56_CONFIG},
 	{GPIO_BITBAND_PTR(CORE_PIN57_PORTREG, CORE_PIN57_BIT), &CORE_PIN57_CONFIG},
-#ifdef USE_SDCARD_PINS
 	{GPIO_BITBAND_PTR(CORE_PIN58_PORTREG, CORE_PIN58_BIT), &CORE_PIN58_CONFIG},
 	{GPIO_BITBAND_PTR(CORE_PIN59_PORTREG, CORE_PIN59_BIT), &CORE_PIN59_CONFIG},
 	{GPIO_BITBAND_PTR(CORE_PIN60_PORTREG, CORE_PIN60_BIT), &CORE_PIN60_CONFIG},
 	{GPIO_BITBAND_PTR(CORE_PIN62_PORTREG, CORE_PIN62_BIT), &CORE_PIN62_CONFIG},
 	{GPIO_BITBAND_PTR(CORE_PIN63_PORTREG, CORE_PIN63_BIT), &CORE_PIN63_CONFIG},
 #endif
-#endif
 };
 
 #elif defined(KINETISL)
 	if ((isfr & CORE_PIN34_BITMASK) && intFunc[34]) intFunc[34]();
 	if ((isfr & CORE_PIN56_BITMASK) && intFunc[56]) intFunc[56]();
 	if ((isfr & CORE_PIN57_BITMASK) && intFunc[57]) intFunc[57]();
-#ifdef USE_SDCARD_PINS
 	if ((isfr & CORE_PIN58_BITMASK) && intFunc[58]) intFunc[58]();
 	if ((isfr & CORE_PIN59_BITMASK) && intFunc[59]) intFunc[59]();
 	if ((isfr & CORE_PIN60_BITMASK) && intFunc[60]) intFunc[60]();
 	if ((isfr & CORE_PIN61_BITMASK) && intFunc[61]) intFunc[61]();
 	if ((isfr & CORE_PIN62_BITMASK) && intFunc[62]) intFunc[62]();
 	if ((isfr & CORE_PIN63_BITMASK) && intFunc[63]) intFunc[63]();
-#endif
 }
 
 #endif

teensy3/serial2.c

 	switch (rx_pin_num) {
 		case 9: CORE_PIN9_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
 		case 26: CORE_PIN26_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
-		#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__))  // on T3.5 or T3.6
+		#if defined(__MK64FX512__) || defined(__MK66FX1M0__)  // on T3.5 or T3.6
 		case 59: CORE_PIN59_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
 		#endif
 	}
 	switch (tx_pin_num) {
 		case 10: CORE_PIN10_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
 		case 31: CORE_PIN31_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
-		#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__))  // on T3.5 or T3.6
+		#if defined(__MK64FX512__) || defined(__MK66FX1M0__)  // on T3.5 or T3.6
 		case 58: CORE_PIN58_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
 		#endif
 	}
 #if defined(KINETISK)
 	switch (rx_pin_num) {
 		case 9: CORE_PIN9_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break; // PTC3
-		#if !(defined(__MK64FX512__) || defined(__MK66FX1M0__))  // not on T3.5 or T3.6
+		#if defined(__MK20DX128__) || defined(__MK20DX256__)  // T3.0, T3.1, T3.2
 		case 26: CORE_PIN26_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break; // PTE1
-		#endif
-		#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__))  // on T3.5 or T3.6
+		#elif defined(__MK64FX512__) || defined(__MK66FX1M0__) // T3.5, T3.6
 		case 59: CORE_PIN59_CONFIG = 0; break;
 		#endif
 	}
 	switch (tx_pin_num & 127) {
 		case 10: CORE_PIN10_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break; // PTC4
-		#if !(defined(__MK64FX512__) || defined(__MK66FX1M0__))  // not on T3.5 or T3.6
+		#if defined(__MK20DX128__) || defined(__MK20DX256__)  // T3.0, T3.1, T3.2
 		case 31: CORE_PIN31_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break; // PTE0
-		#endif
-		#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__))  // on T3.5 or T3.6
+		#elif defined(__MK64FX512__) || defined(__MK66FX1M0__) // T3.5, T3.6
 		case 58: CORE_PIN58_CONFIG = 0; break;
 		#endif
 	}
 	if ((SIM_SCGC4 & SIM_SCGC4_UART1)) {
 		switch (tx_pin_num & 127) {
 			case 10: CORE_PIN10_CONFIG = 0; break; // PTC4
-			#if !(defined(__MK64FX512__) || defined(__MK66FX1M0__))  // not on T3.5 or T3.6
+			#if defined(__MK20DX128__) || defined(__MK20DX256__)  // T3.0, T3.1, T3.2
 			case 31: CORE_PIN31_CONFIG = 0; break; // PTE0
-			#endif
-			#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__))  // on T3.5 or T3.6
+			#elif defined(__MK64FX512__) || defined(__MK66FX1M0__) // T3.5, T3.6
 			case 58: CORE_PIN58_CONFIG = 0; break;
 			#endif
 		}
 		}
 		switch (pin & 127) {
 			case 10: CORE_PIN10_CONFIG = cfg | PORT_PCR_MUX(3); break;
-			#if !(defined(__MK64FX512__) || defined(__MK66FX1M0__))  // not on T3.5 or T3.6
+			#if defined(__MK20DX128__) || defined(__MK20DX256__)  // T3.0, T3.1, T3.2
 			case 31: CORE_PIN31_CONFIG = cfg | PORT_PCR_MUX(3); break;
-			#endif
-			#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__))  // on T3.5 or T3.6
+			#elif defined(__MK64FX512__) || defined(__MK66FX1M0__) // T3.5, T3.6
 			case 58: CORE_PIN58_CONFIG = cfg | PORT_PCR_MUX(3); break;
 			#endif
 		}
 	if ((SIM_SCGC4 & SIM_SCGC4_UART1)) {
 		switch (rx_pin_num) {
 			case 9: CORE_PIN9_CONFIG = 0; break; // PTC3
-			#if !(defined(__MK64FX512__) || defined(__MK66FX1M0__))  // not on T3.5 or T3.6
+			#if defined(__MK20DX128__) || defined(__MK20DX256__)  // T3.0, T3.1, T3.2
 			case 26: CORE_PIN26_CONFIG = 0; break; // PTE1
-			#endif
-			#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__))  // on T3.5 or T3.6
+			#elif defined(__MK64FX512__) || defined(__MK66FX1M0__) // T3.5, T3.6
 			case 59: CORE_PIN59_CONFIG = 0; break;
 			#endif
 		}
 		switch (pin) {
 			case 9: CORE_PIN9_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
-			#if !(defined(__MK64FX512__) || defined(__MK66FX1M0__))  // not on T3.5 or T3.6
+			#if defined(__MK20DX128__) || defined(__MK20DX256__)  // T3.0, T3.1, T3.2
 			case 26: CORE_PIN26_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
-			#endif
-			#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__))  // on T3.5 or T3.6
+			#elif defined(__MK64FX512__) || defined(__MK66FX1M0__) // T3.5, T3.6
 			case 59: CORE_PIN59_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
 			#endif
 		}
 	if (!(SIM_SCGC4 & SIM_SCGC4_UART1)) return 0;
 	if (pin == 23) {
 		CORE_PIN23_CONFIG = PORT_PCR_MUX(3) | PORT_PCR_PE; // weak pulldown
-	#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__))  // on T3.5 or T3.6
+	#if defined(__MK64FX512__) || defined(__MK66FX1M0__)  // on T3.5 or T3.6
 	} else if (pin == 60) {
 		CORE_PIN60_CONFIG = PORT_PCR_MUX(3) | PORT_PCR_PE; // weak pulldown
 	#endif

teensy3/serial4.c

 	transmitting = 0;
 	switch (rx_pin_num) {
 		case 31: CORE_PIN31_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
-		#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__))  // on T3.5 or T3.6
 		case 63: CORE_PIN63_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
-		#endif
 	}
 	switch (tx_pin_num) {
 		case 32: CORE_PIN32_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
-		#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__))  // on T3.5 or T3.6
 		case 62: CORE_PIN62_CONFIG = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); break;
-		#endif
 	}
 	UART3_BDH = (divisor >> 13) & 0x1F;
 	UART3_BDL = (divisor >> 5) & 0xFF;
 	CORE_PIN32_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1);
 	switch (rx_pin_num) {
 		case 31: CORE_PIN31_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break; // PTC3
-		#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__))  // on T3.5 or T3.6
 		case 63: CORE_PIN63_CONFIG = 0; break;
-		#endif
 	}
 	switch (tx_pin_num & 127) {
 		case 32: CORE_PIN32_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_MUX(1); break; // PTC4
-		#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__))  // on T3.5 or T3.6
 		case 62: CORE_PIN62_CONFIG = 0; break;
-		#endif
 	}
 	rx_buffer_head = 0;
 	rx_buffer_tail = 0;
 	if ((SIM_SCGC4 & SIM_SCGC4_UART3)) {
 		switch (tx_pin_num & 127) {
 			case 32:  CORE_PIN32_CONFIG = 0; break; // PTB11
-			#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__))  // on T3.5 or T3.6
 			case 62: CORE_PIN62_CONFIG = 0; break;
-			#endif
 		}
 		if (opendrain) {
 			cfg = PORT_PCR_DSE | PORT_PCR_ODE;
 		}
 		switch (pin & 127) {
 			case 32:  CORE_PIN32_CONFIG = cfg | PORT_PCR_MUX(3); break;
-			#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__))  // on T3.5 or T3.6
 			case 62: CORE_PIN62_CONFIG = cfg | PORT_PCR_MUX(3);; break;
-			#endif
 		}
 	}
 	tx_pin_num = pin;
 	if ((SIM_SCGC4 & SIM_SCGC4_UART3)) {
 		switch (rx_pin_num) {
 			case 31: CORE_PIN31_CONFIG = 0; break; // PTC3
-			#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__))  // on T3.5 or T3.6
 			case 63: CORE_PIN63_CONFIG = 0; break;
-			#endif
 		}
 		switch (pin) {
 			case 31: CORE_PIN31_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
-			#if defined USE_SDCARD_PINS && (defined(__MK64FX512__) || defined(__MK66FX1M0__))  // on T3.5 or T3.6
 			case 63: CORE_PIN63_CONFIG = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); break;
-			#endif
 		}
 	}
 	rx_pin_num = pin;