t4 FLEXIO register masks are 32 bits

The FlexIO registers are 32 bits, the masks were all setup for 16 bits so the high word of registers were not updated

teensy4/imxrt.h

@@ -2945,35 +2945,35 @@ typedef struct {
 #define FLEXIO3_SHIFTBUFNIS1		(IMXRT_FLEXIO3_b.offset384)
 #define FLEXIO3_SHIFTBUFNIS2		(IMXRT_FLEXIO3_b.offset388)
 #define FLEXIO3_SHIFTBUFNIS3		(IMXRT_FLEXIO3_b.offset38C)
-#define FLEXIO_CTRL_DOZEN			((uint16_t)(1<<31))
-#define FLEXIO_CTRL_DBGE			((uint16_t)(1<<30))
-#define FLEXIO_CTRL_FASTACC			((uint16_t)(1<<2))
-#define FLEXIO_CTRL_SWRST			((uint16_t)(1<<1))
-#define FLEXIO_CTRL_FLEXEN			((uint16_t)(1<<0))
-#define FLEXIO_SHIFTCTL_TIMSEL(n)		((uint16_t)(((n) & 0x03) << 24))
-#define FLEXIO_SHIFTCTL_TIMPOL			((uint16_t)(1<<23))
-#define FLEXIO_SHIFTCTL_PINCFG(n)		((uint16_t)(((n) & 0x03) << 16))
-#define FLEXIO_SHIFTCTL_PINSEL(n)		((uint16_t)(((n) & 0x1F) << 8))
-#define FLEXIO_SHIFTCTL_PINPOL			((uint16_t)(1<<7))
-#define FLEXIO_SHIFTCTL_SMOD(n)			((uint16_t)(((n) & 0x07) << 0))
-#define FLEXIO_SHIFTCFG_PWIDTH(n)		((uint16_t)(((n) & 0x1F) << 16))
-#define FLEXIO_SHIFTCFG_INSRC			((uint16_t)(1<<8))
-#define FLEXIO_SHIFTCFG_SSTOP(n)		((uint16_t)(((n) & 0x03) << 4))
-#define FLEXIO_SHIFTCFG_SSTART(n)		((uint16_t)(((n) & 0x03) << 0))
-#define FLEXIO_TIMCTL_TRGSEL(n)			((uint16_t)(((n) & 0x3F) << 24))
-#define FLEXIO_TIMCTL_TRGPOL			((uint16_t)(1<<23))
-#define FLEXIO_TIMCTL_TRGSRC			((uint16_t)(1<<22))
-#define FLEXIO_TIMCTL_PINCFG(n)			((uint16_t)(((n) & 0x03) << 16))
-#define FLEXIO_TIMCTL_PINSEL(n)			((uint16_t)(((n) & 0x1F) << 8))
-#define FLEXIO_TIMCTL_PINPOL			((uint16_t)(1<<7))
-#define FLEXIO_TIMCTL_TIMOD(n)			((uint16_t)(((n) & 0x03) << 0))
-#define FLEXIO_TIMCFG_TIMOUT(n)			((uint16_t)(((n) & 0x03) << 24))
-#define FLEXIO_TIMCFG_TIMDEC(n)			((uint16_t)(((n) & 0x03) << 20))
-#define FLEXIO_TIMCFG_TIMRST(n)			((uint16_t)(((n) & 0x07) << 16))
-#define FLEXIO_TIMCFG_TIMDIS(n)			((uint16_t)(((n) & 0x07) << 12))
-#define FLEXIO_TIMCFG_TIMENA(n)			((uint16_t)(((n) & 0x07) << 8))
-#define FLEXIO_TIMCFG_TSTOP(n)			((uint16_t)(((n) & 0x03) << 4))
-#define FLEXIO_TIMCFG_TSTART			((uint16_t)(1<<1))
+#define FLEXIO_CTRL_DOZEN			((uint32_t)(1<<31))
+#define FLEXIO_CTRL_DBGE			((uint32_t)(1<<30))
+#define FLEXIO_CTRL_FASTACC			((uint32_t)(1<<2))
+#define FLEXIO_CTRL_SWRST			((uint32_t)(1<<1))
+#define FLEXIO_CTRL_FLEXEN			((uint32_t)(1<<0))
+#define FLEXIO_SHIFTCTL_TIMSEL(n)		((uint32_t)(((n) & 0x03) << 24))
+#define FLEXIO_SHIFTCTL_TIMPOL			((uint32_t)(1<<23))
+#define FLEXIO_SHIFTCTL_PINCFG(n)		((uint32_t)(((n) & 0x03) << 16))
+#define FLEXIO_SHIFTCTL_PINSEL(n)		((uint32_t)(((n) & 0x1F) << 8))
+#define FLEXIO_SHIFTCTL_PINPOL			((uint32_t)(1<<7))
+#define FLEXIO_SHIFTCTL_SMOD(n)			((uint32_t)(((n) & 0x07) << 0))
+#define FLEXIO_SHIFTCFG_PWIDTH(n)		((uint32_t)(((n) & 0x1F) << 16))
+#define FLEXIO_SHIFTCFG_INSRC			((uint32_t)(1<<8))
+#define FLEXIO_SHIFTCFG_SSTOP(n)		((uint32_t)(((n) & 0x03) << 4))
+#define FLEXIO_SHIFTCFG_SSTART(n)		((uint32_t)(((n) & 0x03) << 0))
+#define FLEXIO_TIMCTL_TRGSEL(n)			((uint32_t)(((n) & 0x3F) << 24))
+#define FLEXIO_TIMCTL_TRGPOL			((uint32_t)(1<<23))
+#define FLEXIO_TIMCTL_TRGSRC			((uint32_t)(1<<22))
+#define FLEXIO_TIMCTL_PINCFG(n)			((uint32_t)(((n) & 0x03) << 16))
+#define FLEXIO_TIMCTL_PINSEL(n)			((uint32_t)(((n) & 0x1F) << 8))
+#define FLEXIO_TIMCTL_PINPOL			((uint32_t)(1<<7))
+#define FLEXIO_TIMCTL_TIMOD(n)			((uint32_t)(((n) & 0x03) << 0))
+#define FLEXIO_TIMCFG_TIMOUT(n)			((uint32_t)(((n) & 0x03) << 24))
+#define FLEXIO_TIMCFG_TIMDEC(n)			((uint32_t)(((n) & 0x03) << 20))
+#define FLEXIO_TIMCFG_TIMRST(n)			((uint32_t)(((n) & 0x07) << 16))
+#define FLEXIO_TIMCFG_TIMDIS(n)			((uint32_t)(((n) & 0x07) << 12))
+#define FLEXIO_TIMCFG_TIMENA(n)			((uint32_t)(((n) & 0x07) << 8))
+#define FLEXIO_TIMCFG_TSTOP(n)			((uint32_t)(((n) & 0x03) << 4))
+#define FLEXIO_TIMCFG_TSTART			((uint32_t)(1<<1))
 
 // 28.4.1: page 1354
 typedef struct {