Merge pull request #404 from KurtE/t4_avr_registers

T4 avr registers

teensy3/avr_emulation.h

@@ -602,7 +602,7 @@ public:
 		int ret = 0;
 		if (digitalReadFast(14)) ret |= (1<<0);
 		if (digitalReadFast(15)) ret |= (1<<1);
-		if (digitalReadFast(15)) ret |= (1<<2);
+		if (digitalReadFast(16)) ret |= (1<<2);
 		if (digitalReadFast(17)) ret |= (1<<3);
 		if (digitalReadFast(18)) ret |= (1<<4);
 		if (digitalReadFast(19)) ret |= (1<<5);

teensy4/HardwareSerial3.cpp

@@ -58,7 +58,7 @@ static HardwareSerial::hardware_t UART2_Hardware = {
 	CCM_CCGR0, CCM_CCGR0_LPUART2(CCM_CCGR_ON),
 	{{15,2, &IOMUXC_LPUART2_RX_SELECT_INPUT, 1}, {0xff, 0xff, nullptr, 0}},
 	{{14,2, nullptr, 0}, {0xff, 0xff, nullptr, 0}},
-	18, //IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01, // 18
+	19, //IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00, // 19
 	2, // page 473 
 	IRQ_PRIORITY, 38, 24, // IRQ, rts_low_watermark, rts_high_watermark
 };

teensy4/analog.c

@@ -19,17 +19,10 @@ const uint8_t pin_to_channel[] = { // pg 482
 	0,	// 7/A7  AD_B1_11
 	13,	// 8/A8  AD_B1_08
 	14,	// 9/A9  AD_B1_09
-#if 0
-	128,	// 10
-	128,	// 11
-	128,	// 12
-	128,	// 13
-#else
 	1,	// 24/A10 AD_B0_12 
 	2,	// 25/A11 AD_B0_13
 	128+3,	// 26/A12 AD_B1_14 - only on ADC2, 3
 	128+4,	// 27/A13 AD_B1_15 - only on ADC2, 4
-#endif	
 	7,	// 14/A0  AD_B1_02
 	8,	// 15/A1  AD_B1_03
 	12,	// 16/A2  AD_B1_07
@@ -51,6 +44,7 @@ static void wait_for_cal(void)
 {
 	//printf("wait_for_cal\n");
 	while (ADC1_GC & ADC_GC_CAL) ;
+	while (ADC2_GC & ADC_GC_CAL) ;
 	// TODO: check CALF, but what do to about CAL failure?
 	calibrating = 0;
 	//printf("cal complete\n");
@@ -140,8 +134,8 @@ void analogReadAveraging(unsigned int num)
       mode1 |= 0;
     }
 
-  ADC1_CFG |= mode;
-  ADC2_CFG |= mode1;
+  ADC1_CFG = mode;
+  ADC2_CFG = mode1;
   
   if(num >= 4){
       ADC1_GC |= ADC_GC_AVGE;// turns on averaging
@@ -206,7 +200,7 @@ FLASHMEM void analog_init(void)
 	ADC2_CFG = mode | ADC_HC_AIEN | ADC_CFG_ADHSC;
 	ADC2_GC = avg | ADC_GC_CAL;		// begin cal
 	calibrating = 1;
-	while (ADC1_GC & ADC_GC_CAL) ;
+	while (ADC2_GC & ADC_GC_CAL) ;
 	calibrating = 0;
 }
 

teensy4/avr_emulation.h

@@ -38,6 +38,22 @@
 #ifdef __cplusplus
 
 
+// bitband addressing for atomic access to data direction register
+static inline void GPIO_SETBIT_ATOMIC(volatile uint32_t *reg, uint32_t mask) {
+	__disable_irq();
+	*reg |= mask;
+	__enable_irq();
+}
+
+static inline void GPIO_CLRBIT_ATOMIC(volatile uint32_t *reg, uint32_t mask) {
+	__disable_irq();
+	*reg &= ~mask;
+	__enable_irq();
+}
+
+#define CONFIG_PULLUP ( IOMUXC_PAD_DSE(7) | IOMUXC_PAD_PKE | IOMUXC_PAD_PUE | IOMUXC_PAD_PUS(3) | IOMUXC_PAD_HYS )
+#define CONFIG_NOPULLUP ( IOMUXC_PAD_DSE(7))
+
 
 // SPI Control Register ­ SPCR
 #define SPIE	7	// SPI Interrupt Enable - not supported
@@ -392,6 +408,766 @@ public:
 };
 extern SPDRemulation SPDR;
 
+class PORTDemulation
+{
+public:
+	inline PORTDemulation & operator = (int val) __attribute__((always_inline)) {
+		digitalWriteFast(0, (val & (1<<0)));
+		if (!(CORE_PIN0_DDRREG & CORE_PIN0_BITMASK))
+			CORE_PIN0_PADCONFIG = ((val & (1<<0)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		digitalWriteFast(1, (val & (1<<1)));
+		if (!(CORE_PIN1_DDRREG & CORE_PIN1_BITMASK))
+			CORE_PIN1_PADCONFIG = ((val & (1<<1)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		digitalWriteFast(2, (val & (1<<2)));
+		if (!(CORE_PIN2_DDRREG & CORE_PIN2_BITMASK))
+			CORE_PIN2_PADCONFIG = ((val & (1<<2)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		digitalWriteFast(3, (val & (1<<3)));
+		if (!(CORE_PIN3_DDRREG & CORE_PIN3_BITMASK))
+			CORE_PIN3_PADCONFIG = ((val & (1<<3)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		digitalWriteFast(4, (val & (1<<4)));
+		if (!(CORE_PIN4_DDRREG & CORE_PIN4_BITMASK))
+			CORE_PIN4_PADCONFIG = ((val & (1<<4)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		digitalWriteFast(5, (val & (1<<5)));
+		if (!(CORE_PIN5_DDRREG & CORE_PIN5_BITMASK))
+			CORE_PIN5_PADCONFIG = ((val & (1<<5)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		digitalWriteFast(6, (val & (1<<6)));
+		if (!(CORE_PIN6_DDRREG & CORE_PIN6_BITMASK))
+			CORE_PIN6_PADCONFIG = ((val & (1<<6)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		digitalWriteFast(7, (val & (1<<7)));
+		if (!(CORE_PIN7_DDRREG & CORE_PIN7_BITMASK))
+			CORE_PIN7_PADCONFIG = ((val & (1<<7)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		return *this;
+	}
+	inline PORTDemulation & operator |= (int val) __attribute__((always_inline)) {
+		if (val & (1<<0)) {
+			digitalWriteFast(0, HIGH);
+			if (!(CORE_PIN0_DDRREG & CORE_PIN0_BITMASK)) CORE_PIN0_CONFIG = CONFIG_PULLUP;
+		}
+		if (val & (1<<1)) {
+			digitalWriteFast(1, HIGH);
+			if (!(CORE_PIN1_DDRREG & CORE_PIN1_BITMASK)) CORE_PIN1_CONFIG = CONFIG_PULLUP;
+		}
+		if (val & (1<<2)) {
+			digitalWriteFast(2, HIGH);
+			if (!(CORE_PIN2_DDRREG & CORE_PIN2_BITMASK)) CORE_PIN2_CONFIG = CONFIG_PULLUP;
+		}
+		if (val & (1<<3)) {
+			digitalWriteFast(3, HIGH);
+			if (!(CORE_PIN3_DDRREG & CORE_PIN3_BITMASK)) CORE_PIN3_CONFIG = CONFIG_PULLUP;
+		}
+		if (val & (1<<4)) {
+			digitalWriteFast(4, HIGH);
+			if (!(CORE_PIN4_DDRREG & CORE_PIN4_BITMASK)) CORE_PIN4_CONFIG = CONFIG_PULLUP;
+		}
+		if (val & (1<<5)) {
+			digitalWriteFast(5, HIGH);
+			if (!(CORE_PIN5_DDRREG & CORE_PIN5_BITMASK)) CORE_PIN5_CONFIG = CONFIG_PULLUP;
+		}
+		if (val & (1<<6)) {
+			digitalWriteFast(6, HIGH);
+			if (!(CORE_PIN6_DDRREG & CORE_PIN6_BITMASK)) CORE_PIN6_CONFIG = CONFIG_PULLUP;
+		}
+		if (val & (1<<7)) {
+			digitalWriteFast(7, HIGH);
+			if (!(CORE_PIN7_DDRREG & CORE_PIN7_BITMASK)) CORE_PIN7_CONFIG = CONFIG_PULLUP;
+		}
+		return *this;
+	}
+	inline PORTDemulation & operator &= (int val) __attribute__((always_inline)) {
+		if (!(val & (1<<0))) {
+			digitalWriteFast(0, LOW);
+			if (!(CORE_PIN0_DDRREG & CORE_PIN0_BITMASK)) CORE_PIN0_CONFIG = CONFIG_NOPULLUP;
+		}
+		if (!(val & (1<<1))) {
+			digitalWriteFast(1, LOW);
+			if (!(CORE_PIN1_DDRREG & CORE_PIN1_BITMASK)) CORE_PIN1_CONFIG = CONFIG_NOPULLUP;
+		}
+		if (!(val & (1<<2))) {
+			digitalWriteFast(2, LOW);
+			if (!(CORE_PIN2_DDRREG & CORE_PIN2_BITMASK)) CORE_PIN2_CONFIG = CONFIG_NOPULLUP;
+		}
+		if (!(val & (1<<3))) {
+			digitalWriteFast(3, LOW);
+			if (!(CORE_PIN3_DDRREG & CORE_PIN3_BITMASK)) CORE_PIN3_CONFIG = CONFIG_NOPULLUP;
+		}
+		if (!(val & (1<<4))) {
+			digitalWriteFast(4, LOW);
+			if (!(CORE_PIN4_DDRREG & CORE_PIN4_BITMASK)) CORE_PIN4_CONFIG = CONFIG_NOPULLUP;
+		}
+		if (!(val & (1<<5))) {
+			digitalWriteFast(5, LOW);
+			if (!(CORE_PIN5_DDRREG & CORE_PIN5_BITMASK)) CORE_PIN5_CONFIG = CONFIG_NOPULLUP;
+		}
+		if (!(val & (1<<6))) {
+			digitalWriteFast(6, LOW);
+			if (!(CORE_PIN6_DDRREG & CORE_PIN6_BITMASK)) CORE_PIN6_CONFIG = CONFIG_NOPULLUP;
+		}
+		if (!(val & (1<<7))) {
+			digitalWriteFast(7, LOW);
+			if (!(CORE_PIN7_DDRREG & CORE_PIN7_BITMASK)) CORE_PIN7_CONFIG = CONFIG_NOPULLUP;
+		}
+		return *this;
+	}
+};
+extern PORTDemulation PORTD;
+
+class PINDemulation
+{
+public:
+	inline int operator & (int val) const __attribute__((always_inline)) {
+		int ret = 0;
+		if ((val & (1<<0)) && digitalReadFast(0)) ret |= (1<<0);
+		if ((val & (1<<1)) && digitalReadFast(1)) ret |= (1<<1);
+		if ((val & (1<<2)) && digitalReadFast(2)) ret |= (1<<2);
+		if ((val & (1<<3)) && digitalReadFast(3)) ret |= (1<<3);
+		if ((val & (1<<4)) && digitalReadFast(4)) ret |= (1<<4);
+		if ((val & (1<<5)) && digitalReadFast(5)) ret |= (1<<5);
+		if ((val & (1<<6)) && digitalReadFast(6)) ret |= (1<<6);
+		if ((val & (1<<7)) && digitalReadFast(7)) ret |= (1<<7);
+		return ret;
+	}
+	operator int () const __attribute__((always_inline)) {
+		int ret = 0;
+		if (digitalReadFast(0)) ret |= (1<<0);
+		if (digitalReadFast(1)) ret |= (1<<1);
+		if (digitalReadFast(2)) ret |= (1<<2);
+		if (digitalReadFast(3)) ret |= (1<<3);
+		if (digitalReadFast(4)) ret |= (1<<4);
+		if (digitalReadFast(5)) ret |= (1<<5);
+		if (digitalReadFast(6)) ret |= (1<<6);
+		if (digitalReadFast(7)) ret |= (1<<7);
+		return ret;
+	}
+};
+extern PINDemulation PIND;
+
+class DDRDemulation
+{
+public:
+	inline DDRDemulation & operator = (int val) __attribute__((always_inline)) {
+		if (val & (1<<0)) set0(); else clr0();
+		if (val & (1<<1)) set1(); else clr1();
+		if (val & (1<<2)) set2(); else clr2();
+		if (val & (1<<3)) set3(); else clr3();
+		if (val & (1<<4)) set4(); else clr4();
+		if (val & (1<<5)) set5(); else clr5();
+		if (val & (1<<6)) set6(); else clr6();
+		if (val & (1<<7)) set7(); else clr7();
+		return *this;
+	}
+	inline DDRDemulation & operator |= (int val) __attribute__((always_inline)) {
+		if (val & (1<<0)) set0();
+		if (val & (1<<1)) set1();
+		if (val & (1<<2)) set2();
+		if (val & (1<<3)) set3();
+		if (val & (1<<4)) set4();
+		if (val & (1<<5)) set5();
+		if (val & (1<<6)) set6();
+		if (val & (1<<7)) set7();
+		return *this;
+	}
+	inline DDRDemulation & operator &= (int val) __attribute__((always_inline)) {
+		if (!(val & (1<<0))) clr0();
+		if (!(val & (1<<1))) clr1();
+		if (!(val & (1<<2))) clr2();
+		if (!(val & (1<<3))) clr3();
+		if (!(val & (1<<4))) clr4();
+		if (!(val & (1<<5))) clr5();
+		if (!(val & (1<<6))) clr6();
+		if (!(val & (1<<7))) clr7();
+		return *this;
+	}
+private:
+	inline void set0() __attribute__((always_inline)) {
+		GPIO_SETBIT_ATOMIC(&CORE_PIN0_DDRREG, CORE_PIN0_BITMASK);
+		CORE_PIN0_CONFIG = 5 | 0x10;
+		CORE_PIN0_PADCONFIG = CONFIG_PULLUP;
+	}
+	inline void set1() __attribute__((always_inline)) {
+		GPIO_SETBIT_ATOMIC(&CORE_PIN1_DDRREG, CORE_PIN1_BITMASK);
+		CORE_PIN1_CONFIG = 5 | 0x10;
+		CORE_PIN1_PADCONFIG = CONFIG_PULLUP;
+	}
+	inline void set2() __attribute__((always_inline)) {
+		GPIO_SETBIT_ATOMIC(&CORE_PIN2_DDRREG, CORE_PIN2_BITMASK);
+		CORE_PIN2_CONFIG = 5 | 0x10;
+		CORE_PIN2_PADCONFIG = CONFIG_PULLUP;
+	}
+	inline void set3() __attribute__((always_inline)) {
+		GPIO_SETBIT_ATOMIC(&CORE_PIN3_DDRREG, CORE_PIN3_BITMASK);
+		CORE_PIN3_CONFIG = 5 | 0x10;
+		CORE_PIN3_PADCONFIG = CONFIG_PULLUP;
+	}
+	inline void set4() __attribute__((always_inline)) {
+		GPIO_SETBIT_ATOMIC(&CORE_PIN4_DDRREG, CORE_PIN4_BITMASK);
+		CORE_PIN4_CONFIG = 5 | 0x10;
+		CORE_PIN4_PADCONFIG = CONFIG_PULLUP;
+	}
+	inline void set5() __attribute__((always_inline)) {
+		GPIO_SETBIT_ATOMIC(&CORE_PIN5_DDRREG, CORE_PIN5_BITMASK);
+		CORE_PIN5_CONFIG = 5 | 0x10;
+		CORE_PIN5_PADCONFIG = CONFIG_PULLUP;
+	}
+	inline void set6() __attribute__((always_inline)) {
+		GPIO_SETBIT_ATOMIC(&CORE_PIN6_DDRREG, CORE_PIN6_BITMASK);
+		CORE_PIN6_CONFIG = 5 | 0x10;
+		CORE_PIN6_PADCONFIG = CONFIG_PULLUP;
+	}
+	inline void set7() __attribute__((always_inline)) {
+		GPIO_SETBIT_ATOMIC(&CORE_PIN7_DDRREG, CORE_PIN7_BITMASK);
+		CORE_PIN7_CONFIG = 5 | 0x10;
+		CORE_PIN7_PADCONFIG = CONFIG_PULLUP;
+	}
+	inline void clr0() __attribute__((always_inline)) {
+		CORE_PIN0_CONFIG = 5 | 0x10;
+		CORE_PIN0_PADCONFIG = ((CORE_PIN0_PORTREG & CORE_PIN0_BITMASK)
+		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		GPIO_CLRBIT_ATOMIC(&CORE_PIN0_DDRREG, CORE_PIN0_BITMASK);
+	}
+	inline void clr1() __attribute__((always_inline)) {
+		CORE_PIN1_CONFIG = 5 | 0x10;
+		CORE_PIN1_PADCONFIG = ((CORE_PIN1_PORTREG & CORE_PIN1_BITMASK)
+		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		GPIO_CLRBIT_ATOMIC(&CORE_PIN1_DDRREG, CORE_PIN1_BITMASK);
+	}
+	inline void clr2() __attribute__((always_inline)) {
+		CORE_PIN2_CONFIG = 5 | 0x10;
+		CORE_PIN2_PADCONFIG = ((CORE_PIN2_PORTREG & CORE_PIN2_BITMASK)
+		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		GPIO_CLRBIT_ATOMIC(&CORE_PIN2_DDRREG, CORE_PIN2_BITMASK);
+	}
+	inline void clr3() __attribute__((always_inline)) {
+		CORE_PIN3_CONFIG = 5 | 0x10;
+		CORE_PIN3_PADCONFIG = ((CORE_PIN3_PORTREG & CORE_PIN3_BITMASK)
+		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		GPIO_CLRBIT_ATOMIC(&CORE_PIN3_DDRREG, CORE_PIN3_BITMASK);
+	}
+	inline void clr4() __attribute__((always_inline)) {
+		CORE_PIN4_CONFIG = 5 | 0x10;
+		CORE_PIN4_PADCONFIG = ((CORE_PIN4_PORTREG & CORE_PIN4_BITMASK)
+		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		GPIO_CLRBIT_ATOMIC(&CORE_PIN4_DDRREG, CORE_PIN4_BITMASK);
+	}
+	inline void clr5() __attribute__((always_inline)) {
+		CORE_PIN5_CONFIG = 5 | 0x10;
+		CORE_PIN5_PADCONFIG = ((CORE_PIN5_PORTREG & CORE_PIN5_BITMASK)
+		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		GPIO_CLRBIT_ATOMIC(&CORE_PIN5_DDRREG, CORE_PIN5_BITMASK);
+	}
+	inline void clr6() __attribute__((always_inline)) {
+		CORE_PIN6_CONFIG = 5 | 0x10;
+		CORE_PIN6_PADCONFIG = ((CORE_PIN6_PORTREG & CORE_PIN6_BITMASK)
+		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		GPIO_CLRBIT_ATOMIC(&CORE_PIN6_DDRREG, CORE_PIN6_BITMASK);
+	}
+	inline void clr7() __attribute__((always_inline)) {
+		CORE_PIN7_CONFIG = 5 | 0x10;
+		CORE_PIN7_PADCONFIG = ((CORE_PIN7_PORTREG & CORE_PIN7_BITMASK)
+		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		GPIO_CLRBIT_ATOMIC(&CORE_PIN7_DDRREG, CORE_PIN7_BITMASK);
+	}
+};
+
+extern DDRDemulation DDRD;
+
+
+
+
+
+
+class PORTBemulation
+{
+public:
+	inline PORTBemulation & operator = (int val) __attribute__((always_inline)) {
+		digitalWriteFast(8, (val & (1<<0)));
+		if (!(CORE_PIN8_DDRREG & CORE_PIN8_BITMASK))
+			CORE_PIN8_PADCONFIG = ((val & (1<<0)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		digitalWriteFast(9, (val & (1<<1)));
+		if (!(CORE_PIN9_DDRREG & CORE_PIN9_BITMASK))
+			CORE_PIN9_PADCONFIG = ((val & (1<<1)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		digitalWriteFast(10, (val & (1<<2)));
+		if (!(CORE_PIN10_DDRREG & CORE_PIN10_BITMASK))
+			CORE_PIN10_PADCONFIG = ((val & (1<<2)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		digitalWriteFast(11, (val & (1<<3)));
+		if (!(CORE_PIN11_DDRREG & CORE_PIN11_BITMASK))
+			CORE_PIN11_PADCONFIG = ((val & (1<<3)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		digitalWriteFast(12, (val & (1<<4)));
+		if (!(CORE_PIN12_DDRREG & CORE_PIN12_BITMASK))
+			CORE_PIN12_PADCONFIG = ((val & (1<<4)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		digitalWriteFast(13, (val & (1<<5)));
+		if (!(CORE_PIN13_DDRREG & CORE_PIN13_BITMASK))
+			CORE_PIN13_PADCONFIG = ((val & (1<<5)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		return *this;
+	}
+	inline PORTBemulation & operator |= (int val) __attribute__((always_inline)) {
+		if (val & (1<<0)) {
+			digitalWriteFast(8, HIGH);
+			if (!(CORE_PIN7_DDRREG & CORE_PIN7_BITMASK)) CORE_PIN8_CONFIG = CONFIG_PULLUP;
+		}
+		if (val & (1<<1)) {
+			digitalWriteFast(9, HIGH);
+			if (!(CORE_PIN7_DDRREG & CORE_PIN7_BITMASK)) CORE_PIN9_CONFIG = CONFIG_PULLUP;
+		}
+		if (val & (1<<2)) {
+			digitalWriteFast(10, HIGH);
+			if (!(CORE_PIN10_DDRREG & CORE_PIN10_BITMASK)) CORE_PIN10_CONFIG = CONFIG_PULLUP;
+		}
+		if (val & (1<<3)) {
+			digitalWriteFast(11, HIGH);
+			if (!(CORE_PIN11_DDRREG & CORE_PIN11_BITMASK)) CORE_PIN11_CONFIG = CONFIG_PULLUP;
+		}
+		if (val & (1<<4)) {
+			digitalWriteFast(12, HIGH);
+			if (!(CORE_PIN12_DDRREG & CORE_PIN12_BITMASK)) CORE_PIN12_CONFIG = CONFIG_PULLUP;
+		}
+		if (val & (1<<5)) {
+			digitalWriteFast(13, HIGH);
+			if (!(CORE_PIN13_DDRREG & CORE_PIN13_BITMASK)) CORE_PIN13_CONFIG = CONFIG_PULLUP;
+		}
+		return *this;
+	}
+	inline PORTBemulation & operator &= (int val) __attribute__((always_inline)) {
+		if (!(val & (1<<0))) {
+			digitalWriteFast(8, LOW);
+			if (!(CORE_PIN8_DDRREG & CORE_PIN8_BITMASK)) CORE_PIN8_CONFIG = CONFIG_NOPULLUP;
+		}
+		if (!(val & (1<<1))) {
+			digitalWriteFast(9, LOW);
+			if (!(CORE_PIN9_DDRREG & CORE_PIN9_BITMASK)) CORE_PIN9_CONFIG = CONFIG_NOPULLUP;
+		}
+		if (!(val & (1<<2))) {
+			digitalWriteFast(10, LOW);
+			if (!(CORE_PIN10_DDRREG & CORE_PIN10_BITMASK)) CORE_PIN10_CONFIG = CONFIG_NOPULLUP;
+		}
+		if (!(val & (1<<3))) {
+			digitalWriteFast(11, LOW);
+			if (!(CORE_PIN11_DDRREG & CORE_PIN11_BITMASK)) CORE_PIN11_CONFIG = CONFIG_NOPULLUP;
+		}
+		if (!(val & (1<<4))) {
+			digitalWriteFast(12, LOW);
+			if (!(CORE_PIN12_DDRREG & CORE_PIN12_BITMASK)) CORE_PIN12_CONFIG = CONFIG_NOPULLUP;
+		}
+		if (!(val & (1<<5))) {
+			digitalWriteFast(13, LOW);
+			if (!(CORE_PIN13_DDRREG & CORE_PIN13_BITMASK)) CORE_PIN13_CONFIG = CONFIG_NOPULLUP;
+		}
+		return *this;
+	}
+};
+extern PORTBemulation PORTB;
+
+class PINBemulation
+{
+public:
+	inline int operator & (int val) const __attribute__((always_inline)) {
+		int ret = 0;
+		if ((val & (1<<0)) && digitalReadFast(8)) ret |= (1<<0);
+		if ((val & (1<<1)) && digitalReadFast(9)) ret |= (1<<1);
+		if ((val & (1<<2)) && digitalReadFast(10)) ret |= (1<<2);
+		if ((val & (1<<3)) && digitalReadFast(11)) ret |= (1<<3);
+		if ((val & (1<<4)) && digitalReadFast(12)) ret |= (1<<4);
+		if ((val & (1<<5)) && digitalReadFast(13)) ret |= (1<<5);
+		return ret;
+	}
+	operator int () const __attribute__((always_inline)) {
+		int ret = 0;
+		if (digitalReadFast(8)) ret |= (1<<0);
+		if (digitalReadFast(9)) ret |= (1<<1);
+		if (digitalReadFast(10)) ret |= (1<<2);
+		if (digitalReadFast(11)) ret |= (1<<3);
+		if (digitalReadFast(12)) ret |= (1<<4);
+		if (digitalReadFast(13)) ret |= (1<<5);
+		return ret;
+	}
+};
+extern PINBemulation PINB;
+
+class DDRBemulation
+{
+public:
+	inline DDRBemulation & operator = (int val) __attribute__((always_inline)) {
+		if (val & (1<<0)) set0(); else clr0();
+		if (val & (1<<1)) set1(); else clr1();
+		if (val & (1<<2)) set2(); else clr2();
+		if (val & (1<<3)) set3(); else clr3();
+		if (val & (1<<4)) set4(); else clr4();
+		if (val & (1<<5)) set5(); else clr5();
+		return *this;
+	}
+	inline DDRBemulation & operator |= (int val) __attribute__((always_inline)) {
+		if (val & (1<<0)) set0();
+		if (val & (1<<1)) set1();
+		if (val & (1<<2)) set2();
+		if (val & (1<<3)) set3();
+		if (val & (1<<4)) set4();
+		if (val & (1<<5)) set5();
+		return *this;
+	}
+	inline DDRBemulation & operator &= (int val) __attribute__((always_inline)) {
+		if (!(val & (1<<0))) clr0();
+		if (!(val & (1<<1))) clr1();
+		if (!(val & (1<<2))) clr2();
+		if (!(val & (1<<3))) clr3();
+		if (!(val & (1<<4))) clr4();
+		if (!(val & (1<<5))) clr5();
+		return *this;
+	}
+private:
+	inline void set0() __attribute__((always_inline)) {
+		GPIO_SETBIT_ATOMIC(&CORE_PIN8_DDRREG, CORE_PIN8_BITMASK);
+		CORE_PIN8_CONFIG = 5 | 0x10;
+		CORE_PIN8_PADCONFIG = CONFIG_PULLUP;
+	}
+	inline void set1() __attribute__((always_inline)) {
+		GPIO_SETBIT_ATOMIC(&CORE_PIN9_DDRREG, CORE_PIN9_BITMASK);
+		CORE_PIN9_CONFIG = 5 | 0x10;
+		CORE_PIN9_PADCONFIG = CONFIG_PULLUP;
+	}
+	inline void set2() __attribute__((always_inline)) {
+		GPIO_SETBIT_ATOMIC(&CORE_PIN10_DDRREG, CORE_PIN10_BITMASK);
+		CORE_PIN10_CONFIG = 5 | 0x10;
+		CORE_PIN10_PADCONFIG = CONFIG_PULLUP;
+	}
+	inline void set3() __attribute__((always_inline)) {
+		GPIO_SETBIT_ATOMIC(&CORE_PIN11_DDRREG, CORE_PIN11_BITMASK);
+		CORE_PIN11_CONFIG = 5 | 0x10;
+		CORE_PIN11_PADCONFIG = CONFIG_PULLUP;
+	}
+	inline void set4() __attribute__((always_inline)) {
+		GPIO_SETBIT_ATOMIC(&CORE_PIN12_DDRREG, CORE_PIN12_BITMASK);
+		CORE_PIN12_CONFIG = 5 | 0x10;
+		CORE_PIN12_PADCONFIG = CONFIG_PULLUP;
+	}
+	inline void set5() __attribute__((always_inline)) {
+		GPIO_SETBIT_ATOMIC(&CORE_PIN13_DDRREG, CORE_PIN13_BITMASK);
+		CORE_PIN13_CONFIG = 5 | 0x10;
+		CORE_PIN13_PADCONFIG = CONFIG_PULLUP;
+	}
+	inline void clr0() __attribute__((always_inline)) {
+		CORE_PIN8_CONFIG = 5 | 0x10;
+		CORE_PIN8_PADCONFIG = ((CORE_PIN8_PORTREG & CORE_PIN8_BITMASK)
+		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		GPIO_CLRBIT_ATOMIC(&CORE_PIN8_DDRREG, CORE_PIN8_BITMASK);
+	}
+	inline void clr1() __attribute__((always_inline)) {
+		CORE_PIN9_CONFIG = 5 | 0x10;
+		CORE_PIN9_PADCONFIG = ((CORE_PIN9_PORTREG & CORE_PIN9_BITMASK)
+		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		GPIO_CLRBIT_ATOMIC(&CORE_PIN9_DDRREG, CORE_PIN9_BITMASK);
+	}
+	inline void clr2() __attribute__((always_inline)) {
+		CORE_PIN10_CONFIG = 5 | 0x10;
+		CORE_PIN10_PADCONFIG = ((CORE_PIN10_PORTREG & CORE_PIN10_BITMASK)
+		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		GPIO_CLRBIT_ATOMIC(&CORE_PIN10_DDRREG, CORE_PIN10_BITMASK);
+	}
+	inline void clr3() __attribute__((always_inline)) {
+		CORE_PIN11_CONFIG = 5 | 0x10;
+		CORE_PIN11_PADCONFIG = ((CORE_PIN11_PORTREG & CORE_PIN11_BITMASK)
+		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		GPIO_CLRBIT_ATOMIC(&CORE_PIN11_DDRREG, CORE_PIN11_BITMASK);
+	}
+	inline void clr4() __attribute__((always_inline)) {
+		CORE_PIN12_CONFIG = 5 | 0x10;
+		CORE_PIN12_PADCONFIG = ((CORE_PIN12_PORTREG & CORE_PIN12_BITMASK)
+		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		GPIO_CLRBIT_ATOMIC(&CORE_PIN12_DDRREG, CORE_PIN12_BITMASK);
+	}
+	inline void clr5() __attribute__((always_inline)) {
+		CORE_PIN13_CONFIG = 5 | 0x10;
+		CORE_PIN13_PADCONFIG = ((CORE_PIN13_PORTREG & CORE_PIN13_BITMASK)
+		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		GPIO_CLRBIT_ATOMIC(&CORE_PIN13_DDRREG, CORE_PIN13_BITMASK);
+	}
+};
+
+extern DDRBemulation DDRB;
+
+
+
+
+
+
+class PORTCemulation
+{
+public:
+	inline PORTCemulation & operator = (int val) __attribute__((always_inline)) {
+		digitalWriteFast(14, (val & (1<<0)));
+		if (!(CORE_PIN14_DDRREG & CORE_PIN14_BITMASK))
+			CORE_PIN14_PADCONFIG = ((val & (1<<0)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		digitalWriteFast(15, (val & (1<<1)));
+		if (!(CORE_PIN15_DDRREG & CORE_PIN15_BITMASK))
+			CORE_PIN15_PADCONFIG = ((val & (1<<1)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		digitalWriteFast(16, (val & (1<<2)));
+		if (!(CORE_PIN16_DDRREG & CORE_PIN16_BITMASK))
+			CORE_PIN16_PADCONFIG = ((val & (1<<2)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		digitalWriteFast(17, (val & (1<<3)));
+		if (!(CORE_PIN17_DDRREG & CORE_PIN17_BITMASK))
+			CORE_PIN17_PADCONFIG = ((val & (1<<3)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		digitalWriteFast(18, (val & (1<<4)));
+		if (!(CORE_PIN18_DDRREG & CORE_PIN18_BITMASK))
+			CORE_PIN18_PADCONFIG = ((val & (1<<4)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		digitalWriteFast(19, (val & (1<<5)));
+		if (!(CORE_PIN19_DDRREG & CORE_PIN19_BITMASK))
+			CORE_PIN19_PADCONFIG = ((val & (1<<5)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		return *this;
+	}
+	inline PORTCemulation & operator |= (int val) __attribute__((always_inline)) {
+		if (val & (1<<0)) {
+			digitalWriteFast(14, HIGH);
+			if (!(CORE_PIN14_DDRREG & CORE_PIN14_BITMASK)) CORE_PIN14_CONFIG = CONFIG_PULLUP;
+		}
+		if (val & (1<<1)) {
+			digitalWriteFast(15, HIGH);
+			if (!(CORE_PIN15_DDRREG & CORE_PIN15_BITMASK)) CORE_PIN15_CONFIG = CONFIG_PULLUP;
+		}
+		if (val & (1<<2)) {
+			digitalWriteFast(16, HIGH);
+			if (!(CORE_PIN16_DDRREG & CORE_PIN16_BITMASK)) CORE_PIN16_CONFIG = CONFIG_PULLUP;
+		}
+		if (val & (1<<3)) {
+			digitalWriteFast(17, HIGH);
+			if (!(CORE_PIN17_DDRREG & CORE_PIN17_BITMASK)) CORE_PIN17_CONFIG = CONFIG_PULLUP;
+		}
+		if (val & (1<<4)) {
+			digitalWriteFast(18, HIGH);
+			if (!(CORE_PIN18_DDRREG & CORE_PIN18_BITMASK)) CORE_PIN18_CONFIG = CONFIG_PULLUP;
+		}
+		if (val & (1<<5)) {
+			digitalWriteFast(19, HIGH);
+			if (!(CORE_PIN19_DDRREG & CORE_PIN19_BITMASK)) CORE_PIN19_CONFIG = CONFIG_PULLUP;
+		}
+		return *this;
+	}
+	inline PORTCemulation & operator &= (int val) __attribute__((always_inline)) {
+		if (!(val & (1<<0))) {
+			digitalWriteFast(14, LOW);
+			if (!(CORE_PIN14_DDRREG & CORE_PIN14_BITMASK)) CORE_PIN14_CONFIG = CONFIG_NOPULLUP;
+		}
+		if (!(val & (1<<1))) {
+			digitalWriteFast(15, LOW);
+			if (!(CORE_PIN15_DDRREG & CORE_PIN15_BITMASK)) CORE_PIN15_CONFIG = CONFIG_NOPULLUP;
+		}
+		if (!(val & (1<<2))) {
+			digitalWriteFast(16, LOW);
+			if (!(CORE_PIN16_DDRREG & CORE_PIN16_BITMASK)) CORE_PIN16_CONFIG = CONFIG_NOPULLUP;
+		}
+		if (!(val & (1<<3))) {
+			digitalWriteFast(17, LOW);
+			if (!(CORE_PIN17_DDRREG & CORE_PIN17_BITMASK)) CORE_PIN17_CONFIG = CONFIG_NOPULLUP;
+		}
+		if (!(val & (1<<4))) {
+			digitalWriteFast(18, LOW);
+			if (!(CORE_PIN18_DDRREG & CORE_PIN18_BITMASK)) CORE_PIN18_CONFIG = CONFIG_NOPULLUP;
+		}
+		if (!(val & (1<<5))) {
+			digitalWriteFast(19, LOW);
+			if (!(CORE_PIN19_DDRREG & CORE_PIN19_BITMASK)) CORE_PIN19_CONFIG = CONFIG_NOPULLUP;
+		}
+		return *this;
+	}
+};
+extern PORTCemulation PORTC;
+
+class PINCemulation
+{
+public:
+	inline int operator & (int val) const __attribute__((always_inline)) {
+		int ret = 0;
+		if ((val & (1<<0)) && digitalReadFast(14)) ret |= (1<<0);
+		if ((val & (1<<1)) && digitalReadFast(15)) ret |= (1<<1);
+		if ((val & (1<<2)) && digitalReadFast(16)) ret |= (1<<2);
+		if ((val & (1<<3)) && digitalReadFast(17)) ret |= (1<<3);
+		if ((val & (1<<4)) && digitalReadFast(18)) ret |= (1<<4);
+		if ((val & (1<<5)) && digitalReadFast(19)) ret |= (1<<5);
+		return ret;
+	}
+	operator int () const __attribute__((always_inline)) {
+		int ret = 0;
+		if (digitalReadFast(14)) ret |= (1<<0);
+		if (digitalReadFast(15)) ret |= (1<<1);
+		if (digitalReadFast(16)) ret |= (1<<2);
+		if (digitalReadFast(17)) ret |= (1<<3);
+		if (digitalReadFast(18)) ret |= (1<<4);
+		if (digitalReadFast(19)) ret |= (1<<5);
+		return ret;
+	}
+};
+extern PINCemulation PINC;
+
+class DDRCemulation
+{
+public:
+	inline DDRCemulation & operator = (int val) __attribute__((always_inline)) {
+		if (val & (1<<0)) set0(); else clr0();
+		if (val & (1<<1)) set1(); else clr1();
+		if (val & (1<<2)) set2(); else clr2();
+		if (val & (1<<3)) set3(); else clr3();
+		if (val & (1<<4)) set4(); else clr4();
+		if (val & (1<<5)) set5(); else clr5();
+		return *this;
+	}
+	inline DDRCemulation & operator |= (int val) __attribute__((always_inline)) {
+		if (val & (1<<0)) set0();
+		if (val & (1<<1)) set1();
+		if (val & (1<<2)) set2();
+		if (val & (1<<3)) set3();
+		if (val & (1<<4)) set4();
+		if (val & (1<<5)) set5();
+		return *this;
+	}
+	inline DDRCemulation & operator &= (int val) __attribute__((always_inline)) {
+		if (!(val & (1<<0))) clr0();
+		if (!(val & (1<<1))) clr1();
+		if (!(val & (1<<2))) clr2();
+		if (!(val & (1<<3))) clr3();
+		if (!(val & (1<<4))) clr4();
+		if (!(val & (1<<5))) clr5();
+		return *this;
+	}
+private:
+	inline void set0() __attribute__((always_inline)) {
+		GPIO_SETBIT_ATOMIC(&CORE_PIN14_DDRREG, CORE_PIN14_BITMASK);
+		CORE_PIN14_CONFIG = 5 | 0x10;
+		CORE_PIN14_PADCONFIG = CONFIG_PULLUP;
+	}
+	inline void set1() __attribute__((always_inline)) {
+		GPIO_SETBIT_ATOMIC(&CORE_PIN15_DDRREG, CORE_PIN15_BITMASK);
+		CORE_PIN15_CONFIG = 5 | 0x10;
+		CORE_PIN15_PADCONFIG = CONFIG_PULLUP;
+	}
+	inline void set2() __attribute__((always_inline)) {
+		GPIO_SETBIT_ATOMIC(&CORE_PIN16_DDRREG, CORE_PIN16_BITMASK);
+		CORE_PIN16_CONFIG = 5 | 0x10;
+		CORE_PIN16_PADCONFIG = CONFIG_PULLUP;
+	}
+	inline void set3() __attribute__((always_inline)) {
+		GPIO_SETBIT_ATOMIC(&CORE_PIN17_DDRREG, CORE_PIN17_BITMASK);
+		CORE_PIN17_CONFIG = 5 | 0x10;
+		CORE_PIN17_PADCONFIG = CONFIG_PULLUP;
+	}
+	inline void set4() __attribute__((always_inline)) {
+		GPIO_SETBIT_ATOMIC(&CORE_PIN18_DDRREG, CORE_PIN18_BITMASK);
+		CORE_PIN18_CONFIG = 5 | 0x10;
+		CORE_PIN18_PADCONFIG = CONFIG_PULLUP;
+	}
+	inline void set5() __attribute__((always_inline)) {
+		GPIO_SETBIT_ATOMIC(&CORE_PIN19_DDRREG, CORE_PIN19_BITMASK);
+		CORE_PIN19_CONFIG = 5 | 0x10;
+		CORE_PIN19_PADCONFIG = CONFIG_PULLUP;
+	}
+	inline void clr0() __attribute__((always_inline)) {
+		CORE_PIN14_CONFIG = 5 | 0x10;
+		CORE_PIN14_PADCONFIG = ((CORE_PIN14_PORTREG & CORE_PIN14_BITMASK)
+		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		GPIO_CLRBIT_ATOMIC(&CORE_PIN14_DDRREG, CORE_PIN14_BITMASK);
+	}
+	inline void clr1() __attribute__((always_inline)) {
+		CORE_PIN15_CONFIG = 5 | 0x10;
+		CORE_PIN15_PADCONFIG = ((CORE_PIN15_PORTREG & CORE_PIN15_BITMASK)
+		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		GPIO_CLRBIT_ATOMIC(&CORE_PIN15_DDRREG, CORE_PIN15_BITMASK);
+	}
+	inline void clr2() __attribute__((always_inline)) {
+		CORE_PIN16_CONFIG = 5 | 0x10;
+		CORE_PIN16_PADCONFIG = ((CORE_PIN16_PORTREG & CORE_PIN16_BITMASK)
+		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		GPIO_CLRBIT_ATOMIC(&CORE_PIN16_DDRREG, CORE_PIN16_BITMASK);
+	}
+	inline void clr3() __attribute__((always_inline)) {
+		CORE_PIN17_CONFIG = 5 | 0x10;
+		CORE_PIN17_PADCONFIG = ((CORE_PIN17_PORTREG & CORE_PIN17_BITMASK)
+		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		GPIO_CLRBIT_ATOMIC(&CORE_PIN17_DDRREG, CORE_PIN17_BITMASK);
+	}
+	inline void clr4() __attribute__((always_inline)) {
+		CORE_PIN18_CONFIG = 5 | 0x10;
+		CORE_PIN18_PADCONFIG = ((CORE_PIN18_PORTREG & CORE_PIN18_BITMASK)
+		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		GPIO_CLRBIT_ATOMIC(&CORE_PIN18_DDRREG, CORE_PIN18_BITMASK);
+	}
+	inline void clr5() __attribute__((always_inline)) {
+		CORE_PIN19_CONFIG = 5 | 0x10;
+		CORE_PIN19_PADCONFIG = ((CORE_PIN19_PORTREG & CORE_PIN19_BITMASK)
+		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);
+		GPIO_CLRBIT_ATOMIC(&CORE_PIN19_DDRREG, CORE_PIN19_BITMASK);
+	}
+};
+
+extern DDRCemulation DDRC;
+
+
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+#define PINB4 4
+#define PINB5 5
+#define PINB6 6
+#define PINB7 7
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+#define DDB4 4
+#define DDB5 5
+#define DDB6 6
+#define DDB7 7
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+#define PORTB4 4
+#define PORTB5 5
+#define PORTB6 6
+#define PORTB7 7
+#define PINC0 0
+#define PINC1 1
+#define PINC2 2
+#define PINC3 3
+#define PINC4 4
+#define PINC5 5
+#define PINC6 6
+#define DDC0 0
+#define DDC1 1
+#define DDC2 2
+#define DDC3 3
+#define DDC4 4
+#define DDC5 5
+#define DDC6 6
+#define PORTC0 0
+#define PORTC1 1
+#define PORTC2 2
+#define PORTC3 3
+#define PORTC4 4
+#define PORTC5 5
+#define PORTC6 6
+#define PIND0 0
+#define PIND1 1
+#define PIND2 2
+#define PIND3 3
+#define PIND4 4
+#define PIND5 5
+#define PIND6 6
+#define PIND7 7
+#define DDD0 0
+#define DDD1 1
+#define DDD2 2
+#define DDD3 3
+#define DDD4 4
+#define DDD5 5
+#define DDD6 6
+#define DDD7 7
+#define PORTD0 0
+#define PORTD1 1
+#define PORTD2 2
+#define PORTD3 3
+#define PORTD4 4
+#define PORTD5 5
+#define PORTD6 6
+#define PORTD7 7
+
+
 
 #endif // __cplusplus
 

teensy4/imxrt.h

@@ -185,14 +185,14 @@ static inline void attachInterruptVector(enum IRQ_NUMBER_t irq, void (*function)
 #define DMAMUX_SOURCE_FLEXIO1_REQUEST1		0
 #define DMAMUX_SOURCE_FLEXIO2_REQUEST0		1
 #define DMAMUX_SOURCE_FLEXIO2_REQUEST1		1
-#define DMAMUX_SOURCE_LPUART1_RX		2
-#define DMAMUX_SOURCE_LPUART1_TX		3
-#define DMAMUX_SOURCE_LPUART3_RX		4
-#define DMAMUX_SOURCE_LPUART3_TX		5
-#define DMAMUX_SOURCE_LPUART5_RX		6
-#define DMAMUX_SOURCE_LPUART5_TX		7
-#define DMAMUX_SOURCE_LPUART7_RX		8
-#define DMAMUX_SOURCE_LPUART7_TX		9
+#define DMAMUX_SOURCE_LPUART1_TX		2
+#define DMAMUX_SOURCE_LPUART1_RX		3
+#define DMAMUX_SOURCE_LPUART3_TX		4
+#define DMAMUX_SOURCE_LPUART3_RX		5
+#define DMAMUX_SOURCE_LPUART5_TX		6
+#define DMAMUX_SOURCE_LPUART5_RX		7
+#define DMAMUX_SOURCE_LPUART7_TX		8
+#define DMAMUX_SOURCE_LPUART7_RX		9
 #define DMAMUX_SOURCE_FLEXCAN3			11
 #define DMAMUX_SOURCE_CSI			12
 #define DMAMUX_SOURCE_LPSPI1_RX			13
@@ -259,14 +259,14 @@ static inline void attachInterruptVector(enum IRQ_NUMBER_t irq, void (*function)
 #define DMAMUX_SOURCE_FLEXIO1_REQUEST3		64
 #define DMAMUX_SOURCE_FLEXIO2_REQUEST2		65
 #define DMAMUX_SOURCE_FLEXIO2_REQUEST3		65
-#define DMAMUX_SOURCE_LPUART2_RX		66
-#define DMAMUX_SOURCE_LPUART2_TX		67
-#define DMAMUX_SOURCE_LPUART4_RX		68
-#define DMAMUX_SOURCE_LPUART4_TX		69
-#define DMAMUX_SOURCE_LPUART6_RX		70
-#define DMAMUX_SOURCE_LPUART6_TX		71
-#define DMAMUX_SOURCE_LPUART8_RX		72
-#define DMAMUX_SOURCE_LPUART8_TX		73
+#define DMAMUX_SOURCE_LPUART2_TX		66
+#define DMAMUX_SOURCE_LPUART2_RX		67
+#define DMAMUX_SOURCE_LPUART4_TX		68
+#define DMAMUX_SOURCE_LPUART4_RX		69
+#define DMAMUX_SOURCE_LPUART6_TX                70
+#define DMAMUX_SOURCE_LPUART6_RX		71
+#define DMAMUX_SOURCE_LPUART8_TX		72
+#define DMAMUX_SOURCE_LPUART8_RX		73
 #define DMAMUX_SOURCE_PXP			75
 #define DMAMUX_SOURCE_LCDIF			76
 #define DMAMUX_SOURCE_LPSPI2_RX			77