teensy-core-4.1

ツリー: 0ac84cfcbf

作成者	SHA1	メッセージ	日付
PaulStoffregen	3ad57aacac	Revert "teensy3: usb_serial: Extract core usb_serial_port" This reverts commit `6fb4c61b45`.	4年前
Geert Uytterhoeven	6fb4c61b45	teensy3: usb_serial: Extract core usb_serial_port Extract core USB serial functionality in a new usb_serial_port C class, to allow creating multiple USB serial instances without duplicating all code. The original API is retained by creating static inline functions and preprocessor macros using the old names, which are wrappers around the new usb_serial_port functions and data members. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	4年前
Frank Bösing	11bd76352d	FCPU 256MHz	6年前
PaulStoffregen	7099935c0e	Update open source license info	7年前
Frank	9febfa653b	Fix: write returns zero (#202 ) https://forum.pjrc.com/threads/40893-Incorrect-return-for-Serial-write()-on-Teensy-3-6?p=127732#post127732 I'm not sure if this fix has some side-effects - how will other functions react when it does not return zero anymore ?	8年前
PaulStoffregen	6040145aac	More K66 overclocking options	8年前
PaulStoffregen	c364608480	Even more defs	9年前
PaulStoffregen	1225f43fd0	Report Serial bool operator true only after 25 ms Sometimes the PC or Mac drivers are not actually ready to begin receiving data immediately after they cause DTR or RTS to assert. This delay allows the PC to become ready before we tell sketches the Serial device is true (ready).	9年前
PaulStoffregen	caa5312fbc	Opps, fix compile for slow speeds	10年前
PaulStoffregen	8bdc442fdf	Add TODO comment in USB Serial	10年前
PaulStoffregen	9c1e41e70e	Change room() to writeBufferFree() https://groups.google.com/a/arduino.cc/d/msg/developers/ls3hkviFYM4/XWT2LbfzNcgJ	10年前
PaulStoffregen	71160e91c2	Add Serial.room()	10年前
PaulStoffregen	d783be33c1	Clean up trailing whitespace	10年前
PaulStoffregen	7bee55654c	Support more CPU and bus frequencies	10年前
Frank Bösing	6942a12ff4	Stripped to overclock add. 144MHz only for Paul	10年前
Frank Bösing	bbd726f690	Update to 168MHz, 42 MHZ Bus, 28MHz Flash	10年前
Frank Bösing	856a79b321	Modified for additional 120MHz Core-Clock	10年前
PaulStoffregen	5cecdee933	Initial commit, version 1.17-rc1	11年前

18 コミット (0ac84cfcbf9935b32987b30ab1fc335a5e733338)