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teensy-core-4.1
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16 Commits (351efa83c4af85eacb731b15e4103847e3e3ef09)

Author SHA1 Message Date
  PaulStoffregen 351efa83c4 Add support for more clocks: 72, 120, & 168 MHz 10 years ago
  PaulStoffregen 486b200f22 Add missing DMA channel bits 10 years ago
  PaulStoffregen 979e5197fe Add VREF register bit definitions 10 years ago
  Frank Bösing 6942a12ff4 Stripped to overclock add. 144MHz only for Paul 10 years ago
  Frank Bösing bbd726f690 Update to 168MHz, 42 MHZ Bus, 28MHz Flash 10 years ago
  Frank Bösing 856a79b321 Modified for additional 120MHz Core-Clock 10 years ago
  PaulStoffregen 8b69691619 Add extra defs for I2S port on Teensy 3.1 11 years ago
  PaulStoffregen 5861f1b7f6 Add I2C defs for 2nd I2C port on Teensy 3.1 11 years ago
  PaulStoffregen eac28569be Add programmable gain amplifier register defs 11 years ago
  PaulStoffregen 655aa7d1bc Add DMA channels 4-15 definitions 11 years ago
  PaulStoffregen 842a096ced Add register definitions for Teensy 3.1 11 years ago
  PaulStoffregen 729c211500 Support for Teensy 3.1 11 years ago
  PaulStoffregen 4647e9e0c1 SPIFIFO support for any CS pins 11 years ago
  PaulStoffregen 7ba1cbccc6 Add NVIC priority handling in Serial2 & Serial3 11 years ago
  PaulStoffregen a9c632ed6d Add SPI_RSER bit definitions 11 years ago
  PaulStoffregen 5cecdee933 Initial commit, version 1.17-rc1 11 years ago