teensy-core-4.1

作成者	SHA1	メッセージ	日付
PaulStoffregen	938be5eaf7	Clear past transfer state when USB host does new enumeration	5年前
PaulStoffregen	a554067ee0	Add USB transmit timeout	5年前
PaulStoffregen	b062b68308	Add USB Serial flush	5年前
PaulStoffregen	533a0c2c00	Improve USB serial transfers	5年前
PaulStoffregen	f5201cfe1d	Fix USB schedule_transfer()	5年前
PaulStoffregen	ee5c5e4131	Fix USB serial receive when transfer is multiple of packet size	5年前
PaulStoffregen	57bc3456ba	Use ATDTW when polling dTD status, and other USB improvements	5年前
PaulStoffregen	7e959d4a14	USB serial receive on IMXRT	5年前
PaulStoffregen	aee29bc892	Fix compiler warnings	5年前
Frank	2a8b5d066e	rmv warning "implicit declaration of function 'delay'"	5年前
PaulStoffregen	a1ff3e9256	Fix USB serial issues printing before device ready	5年前
PaulStoffregen	7153086e77	Don't disturb pin 13 (leftover debugging code)	5年前
PaulStoffregen	addd88d076	basic usb serial on imxrt	5年前
PaulStoffregen	e687673ddf	First commit, Teensy4 work-in-progress	5年前
Frank Bösing	11bd76352d	FCPU 256MHz	6年前
PaulStoffregen	7099935c0e	Update open source license info	7年前
Frank	9febfa653b	Fix: write returns zero (#202 ) https://forum.pjrc.com/threads/40893-Incorrect-return-for-Serial-write()-on-Teensy-3-6?p=127732#post127732 I'm not sure if this fix has some side-effects - how will other functions react when it does not return zero anymore ?	7年前
PaulStoffregen	6040145aac	More K66 overclocking options	8年前
PaulStoffregen	c364608480	Even more defs	8年前
PaulStoffregen	1225f43fd0	Report Serial bool operator true only after 25 ms Sometimes the PC or Mac drivers are not actually ready to begin receiving data immediately after they cause DTR or RTS to assert. This delay allows the PC to become ready before we tell sketches the Serial device is true (ready).	8年前
PaulStoffregen	caa5312fbc	Opps, fix compile for slow speeds	9年前
PaulStoffregen	8bdc442fdf	Add TODO comment in USB Serial	10年前
PaulStoffregen	9c1e41e70e	Change room() to writeBufferFree() https://groups.google.com/a/arduino.cc/d/msg/developers/ls3hkviFYM4/XWT2LbfzNcgJ	10年前
PaulStoffregen	71160e91c2	Add Serial.room()	10年前
PaulStoffregen	d783be33c1	Clean up trailing whitespace	10年前
PaulStoffregen	7bee55654c	Support more CPU and bus frequencies	10年前
Frank Bösing	6942a12ff4	Stripped to overclock add. 144MHz only for Paul	10年前
Frank Bösing	bbd726f690	Update to 168MHz, 42 MHZ Bus, 28MHz Flash	10年前
Frank Bösing	856a79b321	Modified for additional 120MHz Core-Clock	10年前
PaulStoffregen	5cecdee933	Initial commit, version 1.17-rc1	11年前

14 コミット (5179c6b3ab83faf40b1bbd7f4f2e055c26ff18e8)