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teensy-core-4.1
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5 Commits (6b1873ea140b92f4d85c9482f56654ca56679cd5)

Author SHA1 Message Date
  Frank Bösing bbd726f690 Update to 168MHz, 42 MHZ Bus, 28MHz Flash 10 years ago
  Frank Bösing 856a79b321 Modified for additional 120MHz Core-Clock 10 years ago
  PaulStoffregen a781e92f77 Fix analogRead(39) (Vref) on Teensy 3.1 11 years ago
  PaulStoffregen 729c211500 Support for Teensy 3.1 11 years ago
  PaulStoffregen 5cecdee933 Initial commit, version 1.17-rc1 11 years ago