visus
/
teensy-core-4.1
Suivre 1
Ajouter aux favoris 0
Bifurcation 0
Code Tickets 0 Demandes d'ajout 0 Versions 0 Wiki Activité
Teensy 4.1 core updated for C++20
Vous ne pouvez pas sélectionner plus de 25 sujets Les noms de sujets doivent commencer par une lettre ou un nombre, peuvent contenir des tirets ('-') et peuvent comporter jusqu'à 35 caractères.
374 Révisions
2 Branches
Aborescence: 12c5d4972d
Branches Tags
${ item.name }
Créer la branche ${ searchTerm }
de '12c5d4972d'
${ noResults }
teensy-core-4.1/teensy3/avr_emulation.h

1586 lines
50KB
Brut Annotations Historique 

  1. /* Teensyduino Core Library

  2.  * http://www.pjrc.com/teensy/

  3.  * Copyright (c) 2013 PJRC.COM, LLC.

  4.  *

  5.  * Permission is hereby granted, free of charge, to any person obtaining

  6.  * a copy of this software and associated documentation files (the

  7.  * "Software"), to deal in the Software without restriction, including

  8.  * without limitation the rights to use, copy, modify, merge, publish,

  9.  * distribute, sublicense, and/or sell copies of the Software, and to

  10.  * permit persons to whom the Software is furnished to do so, subject to

  11.  * the following conditions:

  12.  *

  13.  * 1. The above copyright notice and this permission notice shall be

  14.  * included in all copies or substantial portions of the Software.

  15.  *

  16.  * 2. If the Software is incorporated into a build system that allows

  17.  * selection among a list of target devices, then similar target

  18.  * devices manufactured by PJRC.COM must be included in the list of

  19.  * target devices and selectable in the same manner.

  20.  *

  21.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

  22.  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

  23.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

  24.  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS

  25.  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN

  26.  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

  27.  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

  28.  * SOFTWARE.

  29.  */

  30. 

  31. #ifndef _avr_emulation_h_

  32. #define _avr_emulation_h_

  33. 

  34. #include "kinetis.h"

  35. #include "core_pins.h"

  36. #include "pins_arduino.h"

  37. 

  38. #ifdef __cplusplus

  39. 

  40. #define GPIO_BITBAND_ADDR(reg, bit) (((uint32_t)&(reg) - 0x40000000) * 32 + (bit) * 4 + 0x42000000)

  41. #define CONFIG_PULLUP (PORT_PCR_MUX(1) | PORT_PCR_PE | PORT_PCR_PS)

  42. #define CONFIG_NOPULLUP (PORT_PCR_MUX(1))

  43. 

  44. #if defined(KINETISK)

  45. // bitband addressing for atomic access to data direction register

  46. #define GPIO_SETBIT_ATOMIC(reg, bit) (*(uint32_t *)GPIO_BITBAND_ADDR((reg), (bit)) = 1)

  47. #define GPIO_CLRBIT_ATOMIC(reg, bit) (*(uint32_t *)GPIO_BITBAND_ADDR((reg), (bit)) = 0)

  48. #elif defined(KINETISL)

  49. // bit manipulation engine for atomic access to data direction register

  50. #define GPIO_SETBIT_ATOMIC(reg, bit) (*(uint32_t *)(((uint32_t)&(reg) - 0xF8000000) | 0x480FF000) = 1 << (bit))

  51. #define GPIO_CLRBIT_ATOMIC(reg, bit) (*(uint32_t *)(((uint32_t)&(reg) - 0xF8000000) | 0x440FF000) = ~(1 << (bit)))

  52. #endif

  53. 

  54. 

  55. class PORTDemulation

  56. {

  57. public:

  58. 	inline PORTDemulation & operator = (int val) __attribute__((always_inline)) {

  59. 		digitalWriteFast(0, (val & (1<<0)));

  60. 		if (!(CORE_PIN0_DDRREG & CORE_PIN0_BIT))

  61. 			CORE_PIN0_CONFIG = ((val & (1<<0)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  62. 		digitalWriteFast(1, (val & (1<<1)));

  63. 		if (!(CORE_PIN1_DDRREG & CORE_PIN1_BIT))

  64. 			CORE_PIN1_CONFIG = ((val & (1<<1)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  65. 		digitalWriteFast(2, (val & (1<<2)));

  66. 		if (!(CORE_PIN2_DDRREG & CORE_PIN2_BIT))

  67. 			CORE_PIN2_CONFIG = ((val & (1<<2)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  68. 		digitalWriteFast(3, (val & (1<<3)));

  69. 		if (!(CORE_PIN3_DDRREG & CORE_PIN3_BIT))

  70. 			CORE_PIN3_CONFIG = ((val & (1<<3)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  71. 		digitalWriteFast(4, (val & (1<<4)));

  72. 		if (!(CORE_PIN4_DDRREG & CORE_PIN4_BIT))

  73. 			CORE_PIN4_CONFIG = ((val & (1<<4)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  74. 		digitalWriteFast(5, (val & (1<<5)));

  75. 		if (!(CORE_PIN5_DDRREG & CORE_PIN5_BIT))

  76. 			CORE_PIN5_CONFIG = ((val & (1<<5)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  77. 		digitalWriteFast(6, (val & (1<<6)));

  78. 		if (!(CORE_PIN6_DDRREG & CORE_PIN6_BIT))

  79. 			CORE_PIN6_CONFIG = ((val & (1<<6)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  80. 		digitalWriteFast(7, (val & (1<<7)));

  81. 		if (!(CORE_PIN7_DDRREG & CORE_PIN7_BIT))

  82. 			CORE_PIN7_CONFIG = ((val & (1<<7)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  83. 		return *this;

  84. 	}

  85. 	inline PORTDemulation & operator |= (int val) __attribute__((always_inline)) {

  86. 		if (val & (1<<0)) {

  87. 			digitalWriteFast(0, HIGH);

  88. 			if (!(CORE_PIN0_DDRREG & CORE_PIN0_BIT)) CORE_PIN0_CONFIG = CONFIG_PULLUP;

  89. 		}

  90. 		if (val & (1<<1)) {

  91. 			digitalWriteFast(1, HIGH);

  92. 			if (!(CORE_PIN1_DDRREG & CORE_PIN1_BIT)) CORE_PIN1_CONFIG = CONFIG_PULLUP;

  93. 		}

  94. 		if (val & (1<<2)) {

  95. 			digitalWriteFast(2, HIGH);

  96. 			if (!(CORE_PIN2_DDRREG & CORE_PIN2_BIT)) CORE_PIN2_CONFIG = CONFIG_PULLUP;

  97. 		}

  98. 		if (val & (1<<3)) {

  99. 			digitalWriteFast(3, HIGH);

  100. 			if (!(CORE_PIN3_DDRREG & CORE_PIN3_BIT)) CORE_PIN3_CONFIG = CONFIG_PULLUP;

  101. 		}

  102. 		if (val & (1<<4)) {

  103. 			digitalWriteFast(4, HIGH);

  104. 			if (!(CORE_PIN4_DDRREG & CORE_PIN4_BIT)) CORE_PIN4_CONFIG = CONFIG_PULLUP;

  105. 		}

  106. 		if (val & (1<<5)) {

  107. 			digitalWriteFast(5, HIGH);

  108. 			if (!(CORE_PIN5_DDRREG & CORE_PIN5_BIT)) CORE_PIN5_CONFIG = CONFIG_PULLUP;

  109. 		}

  110. 		if (val & (1<<6)) {

  111. 			digitalWriteFast(6, HIGH);

  112. 			if (!(CORE_PIN6_DDRREG & CORE_PIN6_BIT)) CORE_PIN6_CONFIG = CONFIG_PULLUP;

  113. 		}

  114. 		if (val & (1<<7)) {

  115. 			digitalWriteFast(7, HIGH);

  116. 			if (!(CORE_PIN7_DDRREG & CORE_PIN7_BIT)) CORE_PIN7_CONFIG = CONFIG_PULLUP;

  117. 		}

  118. 		return *this;

  119. 	}

  120. 	inline PORTDemulation & operator &= (int val) __attribute__((always_inline)) {

  121. 		if (!(val & (1<<0))) {

  122. 			digitalWriteFast(0, LOW);

  123. 			if (!(CORE_PIN0_DDRREG & CORE_PIN0_BIT)) CORE_PIN0_CONFIG = CONFIG_NOPULLUP;

  124. 		}

  125. 		if (!(val & (1<<1))) {

  126. 			digitalWriteFast(1, LOW);

  127. 			if (!(CORE_PIN1_DDRREG & CORE_PIN1_BIT)) CORE_PIN1_CONFIG = CONFIG_NOPULLUP;

  128. 		}

  129. 		if (!(val & (1<<2))) {

  130. 			digitalWriteFast(2, LOW);

  131. 			if (!(CORE_PIN2_DDRREG & CORE_PIN2_BIT)) CORE_PIN2_CONFIG = CONFIG_NOPULLUP;

  132. 		}

  133. 		if (!(val & (1<<3))) {

  134. 			digitalWriteFast(3, LOW);

  135. 			if (!(CORE_PIN3_DDRREG & CORE_PIN3_BIT)) CORE_PIN3_CONFIG = CONFIG_NOPULLUP;

  136. 		}

  137. 		if (!(val & (1<<4))) {

  138. 			digitalWriteFast(4, LOW);

  139. 			if (!(CORE_PIN4_DDRREG & CORE_PIN4_BIT)) CORE_PIN4_CONFIG = CONFIG_NOPULLUP;

  140. 		}

  141. 		if (!(val & (1<<5))) {

  142. 			digitalWriteFast(5, LOW);

  143. 			if (!(CORE_PIN5_DDRREG & CORE_PIN5_BIT)) CORE_PIN5_CONFIG = CONFIG_NOPULLUP;

  144. 		}

  145. 		if (!(val & (1<<6))) {

  146. 			digitalWriteFast(6, LOW);

  147. 			if (!(CORE_PIN6_DDRREG & CORE_PIN6_BIT)) CORE_PIN6_CONFIG = CONFIG_NOPULLUP;

  148. 		}

  149. 		if (!(val & (1<<7))) {

  150. 			digitalWriteFast(7, LOW);

  151. 			if (!(CORE_PIN7_DDRREG & CORE_PIN7_BIT)) CORE_PIN7_CONFIG = CONFIG_NOPULLUP;

  152. 		}

  153. 		return *this;

  154. 	}

  155. };

  156. extern PORTDemulation PORTD;

  157. 

  158. class PINDemulation

  159. {

  160. public:

  161. 	inline int operator & (int val) const __attribute__((always_inline)) {

  162. 		int ret = 0;

  163. 		if ((val & (1<<0)) && digitalReadFast(0)) ret |= (1<<0);

  164. 		if ((val & (1<<1)) && digitalReadFast(1)) ret |= (1<<1);

  165. 		if ((val & (1<<2)) && digitalReadFast(2)) ret |= (1<<2);

  166. 		if ((val & (1<<3)) && digitalReadFast(3)) ret |= (1<<3);

  167. 		if ((val & (1<<4)) && digitalReadFast(4)) ret |= (1<<4);

  168. 		if ((val & (1<<5)) && digitalReadFast(5)) ret |= (1<<5);

  169. 		if ((val & (1<<6)) && digitalReadFast(6)) ret |= (1<<6);

  170. 		if ((val & (1<<7)) && digitalReadFast(7)) ret |= (1<<7);

  171. 		return ret;

  172. 	}

  173. 	operator int () const __attribute__((always_inline)) {

  174. 		int ret = 0;

  175. 		if (digitalReadFast(0)) ret |= (1<<0);

  176. 		if (digitalReadFast(1)) ret |= (1<<1);

  177. 		if (digitalReadFast(2)) ret |= (1<<2);

  178. 		if (digitalReadFast(3)) ret |= (1<<3);

  179. 		if (digitalReadFast(4)) ret |= (1<<4);

  180. 		if (digitalReadFast(5)) ret |= (1<<5);

  181. 		if (digitalReadFast(6)) ret |= (1<<6);

  182. 		if (digitalReadFast(7)) ret |= (1<<7);

  183. 		return ret;

  184. 	}

  185. };

  186. extern PINDemulation PIND;

  187. 

  188. class DDRDemulation

  189. {

  190. public:

  191. 	inline DDRDemulation & operator = (int val) __attribute__((always_inline)) {

  192. 		if (val & (1<<0)) set0(); else clr0();

  193. 		if (val & (1<<1)) set1(); else clr1();

  194. 		if (val & (1<<2)) set2(); else clr2();

  195. 		if (val & (1<<3)) set3(); else clr3();

  196. 		if (val & (1<<4)) set4(); else clr4();

  197. 		if (val & (1<<5)) set5(); else clr5();

  198. 		if (val & (1<<6)) set6(); else clr6();

  199. 		if (val & (1<<7)) set7(); else clr7();

  200. 		return *this;

  201. 	}

  202. 	inline DDRDemulation & operator |= (int val) __attribute__((always_inline)) {

  203. 		if (val & (1<<0)) set0();

  204. 		if (val & (1<<1)) set1();

  205. 		if (val & (1<<2)) set2();

  206. 		if (val & (1<<3)) set3();

  207. 		if (val & (1<<4)) set4();

  208. 		if (val & (1<<5)) set5();

  209. 		if (val & (1<<6)) set6();

  210. 		if (val & (1<<7)) set7();

  211. 		return *this;

  212. 	}

  213. 	inline DDRDemulation & operator &= (int val) __attribute__((always_inline)) {

  214. 		if (!(val & (1<<0))) clr0();

  215. 		if (!(val & (1<<1))) clr1();

  216. 		if (!(val & (1<<2))) clr2();

  217. 		if (!(val & (1<<3))) clr3();

  218. 		if (!(val & (1<<4))) clr4();

  219. 		if (!(val & (1<<5))) clr5();

  220. 		if (!(val & (1<<6))) clr6();

  221. 		if (!(val & (1<<7))) clr7();

  222. 		return *this;

  223. 	}

  224. private:

  225. 	inline void set0() __attribute__((always_inline)) {

  226. 		GPIO_SETBIT_ATOMIC(CORE_PIN0_DDRREG, CORE_PIN0_BIT);

  227. 		CORE_PIN0_CONFIG = CONFIG_PULLUP;

  228. 	}

  229. 	inline void set1() __attribute__((always_inline)) {

  230. 		GPIO_SETBIT_ATOMIC(CORE_PIN1_DDRREG, CORE_PIN1_BIT);

  231. 		CORE_PIN1_CONFIG = CONFIG_PULLUP;

  232. 	}

  233. 	inline void set2() __attribute__((always_inline)) {

  234. 		GPIO_SETBIT_ATOMIC(CORE_PIN2_DDRREG, CORE_PIN2_BIT);

  235. 		CORE_PIN2_CONFIG = CONFIG_PULLUP;

  236. 	}

  237. 	inline void set3() __attribute__((always_inline)) {

  238. 		GPIO_SETBIT_ATOMIC(CORE_PIN3_DDRREG, CORE_PIN3_BIT);

  239. 		CORE_PIN3_CONFIG = CONFIG_PULLUP;

  240. 	}

  241. 	inline void set4() __attribute__((always_inline)) {

  242. 		GPIO_SETBIT_ATOMIC(CORE_PIN4_DDRREG, CORE_PIN4_BIT);

  243. 		CORE_PIN4_CONFIG = CONFIG_PULLUP;

  244. 	}

  245. 	inline void set5() __attribute__((always_inline)) {

  246. 		GPIO_SETBIT_ATOMIC(CORE_PIN5_DDRREG, CORE_PIN5_BIT);

  247. 		CORE_PIN5_CONFIG = CONFIG_PULLUP;

  248. 	}

  249. 	inline void set6() __attribute__((always_inline)) {

  250. 		GPIO_SETBIT_ATOMIC(CORE_PIN6_DDRREG, CORE_PIN6_BIT);

  251. 		CORE_PIN6_CONFIG = CONFIG_PULLUP;

  252. 	}

  253. 	inline void set7() __attribute__((always_inline)) {

  254. 		GPIO_SETBIT_ATOMIC(CORE_PIN7_DDRREG, CORE_PIN7_BIT);

  255. 		CORE_PIN7_CONFIG = CONFIG_PULLUP;

  256. 	}

  257. 	inline void clr0() __attribute__((always_inline)) {

  258. 		CORE_PIN0_CONFIG = ((CORE_PIN0_PORTREG & CORE_PIN0_BITMASK)

  259. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  260. 		GPIO_CLRBIT_ATOMIC(CORE_PIN0_DDRREG, CORE_PIN0_BIT);

  261. 	}

  262. 	inline void clr1() __attribute__((always_inline)) {

  263. 		CORE_PIN1_CONFIG = ((CORE_PIN1_PORTREG & CORE_PIN1_BITMASK)

  264. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  265. 		GPIO_CLRBIT_ATOMIC(CORE_PIN1_DDRREG, CORE_PIN1_BIT);

  266. 	}

  267. 	inline void clr2() __attribute__((always_inline)) {

  268. 		CORE_PIN2_CONFIG = ((CORE_PIN2_PORTREG & CORE_PIN2_BITMASK)

  269. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  270. 		GPIO_CLRBIT_ATOMIC(CORE_PIN2_DDRREG, CORE_PIN2_BIT);

  271. 	}

  272. 	inline void clr3() __attribute__((always_inline)) {

  273. 		CORE_PIN3_CONFIG = ((CORE_PIN3_PORTREG & CORE_PIN3_BITMASK)

  274. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  275. 		GPIO_CLRBIT_ATOMIC(CORE_PIN3_DDRREG, CORE_PIN3_BIT);

  276. 	}

  277. 	inline void clr4() __attribute__((always_inline)) {

  278. 		CORE_PIN4_CONFIG = ((CORE_PIN4_PORTREG & CORE_PIN4_BITMASK)

  279. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  280. 		GPIO_CLRBIT_ATOMIC(CORE_PIN4_DDRREG, CORE_PIN4_BIT);

  281. 	}

  282. 	inline void clr5() __attribute__((always_inline)) {

  283. 		CORE_PIN5_CONFIG = ((CORE_PIN5_PORTREG & CORE_PIN5_BITMASK)

  284. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  285. 		GPIO_CLRBIT_ATOMIC(CORE_PIN5_DDRREG, CORE_PIN5_BIT);

  286. 	}

  287. 	inline void clr6() __attribute__((always_inline)) {

  288. 		CORE_PIN6_CONFIG = ((CORE_PIN6_PORTREG & CORE_PIN6_BITMASK)

  289. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  290. 		GPIO_CLRBIT_ATOMIC(CORE_PIN6_DDRREG, CORE_PIN6_BIT);

  291. 	}

  292. 	inline void clr7() __attribute__((always_inline)) {

  293. 		CORE_PIN7_CONFIG = ((CORE_PIN7_PORTREG & CORE_PIN7_BITMASK)

  294. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  295. 		GPIO_CLRBIT_ATOMIC(CORE_PIN7_DDRREG, CORE_PIN7_BIT);

  296. 	}

  297. };

  298. 

  299. extern DDRDemulation DDRD;

  300. 

  301. 

  302. 

  303. 

  304. 

  305. 

  306. class PORTBemulation

  307. {

  308. public:

  309. 	inline PORTBemulation & operator = (int val) __attribute__((always_inline)) {

  310. 		digitalWriteFast(8, (val & (1<<0)));

  311. 		if (!(CORE_PIN8_DDRREG & CORE_PIN8_BIT))

  312. 			CORE_PIN8_CONFIG = ((val & (1<<0)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  313. 		digitalWriteFast(9, (val & (1<<1)));

  314. 		if (!(CORE_PIN9_DDRREG & CORE_PIN9_BIT))

  315. 			CORE_PIN9_CONFIG = ((val & (1<<1)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  316. 		digitalWriteFast(10, (val & (1<<2)));

  317. 		if (!(CORE_PIN10_DDRREG & CORE_PIN10_BIT))

  318. 			CORE_PIN10_CONFIG = ((val & (1<<2)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  319. 		digitalWriteFast(11, (val & (1<<3)));

  320. 		if (!(CORE_PIN11_DDRREG & CORE_PIN11_BIT))

  321. 			CORE_PIN11_CONFIG = ((val & (1<<3)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  322. 		digitalWriteFast(12, (val & (1<<4)));

  323. 		if (!(CORE_PIN12_DDRREG & CORE_PIN12_BIT))

  324. 			CORE_PIN12_CONFIG = ((val & (1<<4)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  325. 		digitalWriteFast(13, (val & (1<<5)));

  326. 		if (!(CORE_PIN13_DDRREG & CORE_PIN13_BIT))

  327. 			CORE_PIN13_CONFIG = ((val & (1<<5)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  328. 		return *this;

  329. 	}

  330. 	inline PORTBemulation & operator |= (int val) __attribute__((always_inline)) {

  331. 		if (val & (1<<0)) {

  332. 			digitalWriteFast(8, HIGH);

  333. 			if (!(CORE_PIN7_DDRREG & CORE_PIN7_BIT)) CORE_PIN8_CONFIG = CONFIG_PULLUP;

  334. 		}

  335. 		if (val & (1<<1)) {

  336. 			digitalWriteFast(9, HIGH);

  337. 			if (!(CORE_PIN7_DDRREG & CORE_PIN7_BIT)) CORE_PIN9_CONFIG = CONFIG_PULLUP;

  338. 		}

  339. 		if (val & (1<<2)) {

  340. 			digitalWriteFast(10, HIGH);

  341. 			if (!(CORE_PIN10_DDRREG & CORE_PIN10_BIT)) CORE_PIN10_CONFIG = CONFIG_PULLUP;

  342. 		}

  343. 		if (val & (1<<3)) {

  344. 			digitalWriteFast(11, HIGH);

  345. 			if (!(CORE_PIN11_DDRREG & CORE_PIN11_BIT)) CORE_PIN11_CONFIG = CONFIG_PULLUP;

  346. 		}

  347. 		if (val & (1<<4)) {

  348. 			digitalWriteFast(12, HIGH);

  349. 			if (!(CORE_PIN12_DDRREG & CORE_PIN12_BIT)) CORE_PIN12_CONFIG = CONFIG_PULLUP;

  350. 		}

  351. 		if (val & (1<<5)) {

  352. 			digitalWriteFast(13, HIGH);

  353. 			if (!(CORE_PIN13_DDRREG & CORE_PIN13_BIT)) CORE_PIN13_CONFIG = CONFIG_PULLUP;

  354. 		}

  355. 		return *this;

  356. 	}

  357. 	inline PORTBemulation & operator &= (int val) __attribute__((always_inline)) {

  358. 		if (!(val & (1<<0))) {

  359. 			digitalWriteFast(8, LOW);

  360. 			if (!(CORE_PIN8_DDRREG & CORE_PIN8_BIT)) CORE_PIN8_CONFIG = CONFIG_NOPULLUP;

  361. 		}

  362. 		if (!(val & (1<<1))) {

  363. 			digitalWriteFast(9, LOW);

  364. 			if (!(CORE_PIN9_DDRREG & CORE_PIN9_BIT)) CORE_PIN9_CONFIG = CONFIG_NOPULLUP;

  365. 		}

  366. 		if (!(val & (1<<2))) {

  367. 			digitalWriteFast(10, LOW);

  368. 			if (!(CORE_PIN10_DDRREG & CORE_PIN10_BIT)) CORE_PIN10_CONFIG = CONFIG_NOPULLUP;

  369. 		}

  370. 		if (!(val & (1<<3))) {

  371. 			digitalWriteFast(11, LOW);

  372. 			if (!(CORE_PIN11_DDRREG & CORE_PIN11_BIT)) CORE_PIN11_CONFIG = CONFIG_NOPULLUP;

  373. 		}

  374. 		if (!(val & (1<<4))) {

  375. 			digitalWriteFast(12, LOW);

  376. 			if (!(CORE_PIN12_DDRREG & CORE_PIN12_BIT)) CORE_PIN12_CONFIG = CONFIG_NOPULLUP;

  377. 		}

  378. 		if (!(val & (1<<5))) {

  379. 			digitalWriteFast(13, LOW);

  380. 			if (!(CORE_PIN13_DDRREG & CORE_PIN13_BIT)) CORE_PIN13_CONFIG = CONFIG_NOPULLUP;

  381. 		}

  382. 		return *this;

  383. 	}

  384. };

  385. extern PORTBemulation PORTB;

  386. 

  387. class PINBemulation

  388. {

  389. public:

  390. 	inline int operator & (int val) const __attribute__((always_inline)) {

  391. 		int ret = 0;

  392. 		if ((val & (1<<0)) && digitalReadFast(8)) ret |= (1<<0);

  393. 		if ((val & (1<<1)) && digitalReadFast(9)) ret |= (1<<1);

  394. 		if ((val & (1<<2)) && digitalReadFast(10)) ret |= (1<<2);

  395. 		if ((val & (1<<3)) && digitalReadFast(11)) ret |= (1<<3);

  396. 		if ((val & (1<<4)) && digitalReadFast(12)) ret |= (1<<4);

  397. 		if ((val & (1<<5)) && digitalReadFast(13)) ret |= (1<<5);

  398. 		return ret;

  399. 	}

  400. 	operator int () const __attribute__((always_inline)) {

  401. 		int ret = 0;

  402. 		if (digitalReadFast(8)) ret |= (1<<0);

  403. 		if (digitalReadFast(9)) ret |= (1<<1);

  404. 		if (digitalReadFast(10)) ret |= (1<<2);

  405. 		if (digitalReadFast(11)) ret |= (1<<3);

  406. 		if (digitalReadFast(12)) ret |= (1<<4);

  407. 		if (digitalReadFast(13)) ret |= (1<<5);

  408. 		return ret;

  409. 	}

  410. };

  411. extern PINBemulation PINB;

  412. 

  413. class DDRBemulation

  414. {

  415. public:

  416. 	inline DDRBemulation & operator = (int val) __attribute__((always_inline)) {

  417. 		if (val & (1<<0)) set0(); else clr0();

  418. 		if (val & (1<<1)) set1(); else clr1();

  419. 		if (val & (1<<2)) set2(); else clr2();

  420. 		if (val & (1<<3)) set3(); else clr3();

  421. 		if (val & (1<<4)) set4(); else clr4();

  422. 		if (val & (1<<5)) set5(); else clr5();

  423. 		return *this;

  424. 	}

  425. 	inline DDRBemulation & operator |= (int val) __attribute__((always_inline)) {

  426. 		if (val & (1<<0)) set0();

  427. 		if (val & (1<<1)) set1();

  428. 		if (val & (1<<2)) set2();

  429. 		if (val & (1<<3)) set3();

  430. 		if (val & (1<<4)) set4();

  431. 		if (val & (1<<5)) set5();

  432. 		return *this;

  433. 	}

  434. 	inline DDRBemulation & operator &= (int val) __attribute__((always_inline)) {

  435. 		if (!(val & (1<<0))) clr0();

  436. 		if (!(val & (1<<1))) clr1();

  437. 		if (!(val & (1<<2))) clr2();

  438. 		if (!(val & (1<<3))) clr3();

  439. 		if (!(val & (1<<4))) clr4();

  440. 		if (!(val & (1<<5))) clr5();

  441. 		return *this;

  442. 	}

  443. private:

  444. 	inline void set0() __attribute__((always_inline)) {

  445. 		GPIO_SETBIT_ATOMIC(CORE_PIN8_DDRREG, CORE_PIN8_BIT);

  446. 		CORE_PIN8_CONFIG = CONFIG_PULLUP;

  447. 	}

  448. 	inline void set1() __attribute__((always_inline)) {

  449. 		GPIO_SETBIT_ATOMIC(CORE_PIN9_DDRREG, CORE_PIN9_BIT);

  450. 		CORE_PIN9_CONFIG = CONFIG_PULLUP;

  451. 	}

  452. 	inline void set2() __attribute__((always_inline)) {

  453. 		GPIO_SETBIT_ATOMIC(CORE_PIN10_DDRREG, CORE_PIN10_BIT);

  454. 		CORE_PIN10_CONFIG = CONFIG_PULLUP;

  455. 	}

  456. 	inline void set3() __attribute__((always_inline)) {

  457. 		GPIO_SETBIT_ATOMIC(CORE_PIN11_DDRREG, CORE_PIN11_BIT);

  458. 		CORE_PIN11_CONFIG = CONFIG_PULLUP;

  459. 	}

  460. 	inline void set4() __attribute__((always_inline)) {

  461. 		GPIO_SETBIT_ATOMIC(CORE_PIN12_DDRREG, CORE_PIN12_BIT);

  462. 		CORE_PIN12_CONFIG = CONFIG_PULLUP;

  463. 	}

  464. 	inline void set5() __attribute__((always_inline)) {

  465. 		GPIO_SETBIT_ATOMIC(CORE_PIN13_DDRREG, CORE_PIN13_BIT);

  466. 		CORE_PIN13_CONFIG = CONFIG_PULLUP;

  467. 	}

  468. 	inline void clr0() __attribute__((always_inline)) {

  469. 		CORE_PIN8_CONFIG = ((CORE_PIN8_PORTREG & CORE_PIN8_BITMASK)

  470. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  471. 		GPIO_CLRBIT_ATOMIC(CORE_PIN8_DDRREG, CORE_PIN8_BIT);

  472. 	}

  473. 	inline void clr1() __attribute__((always_inline)) {

  474. 		CORE_PIN9_CONFIG = ((CORE_PIN9_PORTREG & CORE_PIN9_BITMASK)

  475. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  476. 		GPIO_CLRBIT_ATOMIC(CORE_PIN9_DDRREG, CORE_PIN9_BIT);

  477. 	}

  478. 	inline void clr2() __attribute__((always_inline)) {

  479. 		CORE_PIN10_CONFIG = ((CORE_PIN10_PORTREG & CORE_PIN10_BITMASK)

  480. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  481. 		GPIO_CLRBIT_ATOMIC(CORE_PIN10_DDRREG, CORE_PIN10_BIT);

  482. 	}

  483. 	inline void clr3() __attribute__((always_inline)) {

  484. 		CORE_PIN11_CONFIG = ((CORE_PIN11_PORTREG & CORE_PIN11_BITMASK)

  485. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  486. 		GPIO_CLRBIT_ATOMIC(CORE_PIN11_DDRREG, CORE_PIN11_BIT);

  487. 	}

  488. 	inline void clr4() __attribute__((always_inline)) {

  489. 		CORE_PIN12_CONFIG = ((CORE_PIN12_PORTREG & CORE_PIN12_BITMASK)

  490. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  491. 		GPIO_CLRBIT_ATOMIC(CORE_PIN12_DDRREG, CORE_PIN12_BIT);

  492. 	}

  493. 	inline void clr5() __attribute__((always_inline)) {

  494. 		CORE_PIN13_CONFIG = ((CORE_PIN13_PORTREG & CORE_PIN13_BITMASK)

  495. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  496. 		GPIO_CLRBIT_ATOMIC(CORE_PIN13_DDRREG, CORE_PIN13_BIT);

  497. 	}

  498. };

  499. 

  500. extern DDRBemulation DDRB;

  501. 

  502. 

  503. 

  504. 

  505. 

  506. 

  507. class PORTCemulation

  508. {

  509. public:

  510. 	inline PORTCemulation & operator = (int val) __attribute__((always_inline)) {

  511. 		digitalWriteFast(14, (val & (1<<0)));

  512. 		if (!(CORE_PIN14_DDRREG & CORE_PIN14_BIT))

  513. 			CORE_PIN14_CONFIG = ((val & (1<<0)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  514. 		digitalWriteFast(15, (val & (1<<1)));

  515. 		if (!(CORE_PIN15_DDRREG & CORE_PIN15_BIT))

  516. 			CORE_PIN15_CONFIG = ((val & (1<<1)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  517. 		digitalWriteFast(16, (val & (1<<2)));

  518. 		if (!(CORE_PIN16_DDRREG & CORE_PIN16_BIT))

  519. 			CORE_PIN16_CONFIG = ((val & (1<<2)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  520. 		digitalWriteFast(17, (val & (1<<3)));

  521. 		if (!(CORE_PIN17_DDRREG & CORE_PIN17_BIT))

  522. 			CORE_PIN17_CONFIG = ((val & (1<<3)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  523. 		digitalWriteFast(18, (val & (1<<4)));

  524. 		if (!(CORE_PIN18_DDRREG & CORE_PIN18_BIT))

  525. 			CORE_PIN18_CONFIG = ((val & (1<<4)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  526. 		digitalWriteFast(19, (val & (1<<5)));

  527. 		if (!(CORE_PIN19_DDRREG & CORE_PIN19_BIT))

  528. 			CORE_PIN19_CONFIG = ((val & (1<<5)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  529. 		return *this;

  530. 	}

  531. 	inline PORTCemulation & operator |= (int val) __attribute__((always_inline)) {

  532. 		if (val & (1<<0)) {

  533. 			digitalWriteFast(14, HIGH);

  534. 			if (!(CORE_PIN14_DDRREG & CORE_PIN14_BIT)) CORE_PIN14_CONFIG = CONFIG_PULLUP;

  535. 		}

  536. 		if (val & (1<<1)) {

  537. 			digitalWriteFast(15, HIGH);

  538. 			if (!(CORE_PIN15_DDRREG & CORE_PIN15_BIT)) CORE_PIN15_CONFIG = CONFIG_PULLUP;

  539. 		}

  540. 		if (val & (1<<2)) {

  541. 			digitalWriteFast(16, HIGH);

  542. 			if (!(CORE_PIN16_DDRREG & CORE_PIN16_BIT)) CORE_PIN16_CONFIG = CONFIG_PULLUP;

  543. 		}

  544. 		if (val & (1<<3)) {

  545. 			digitalWriteFast(17, HIGH);

  546. 			if (!(CORE_PIN17_DDRREG & CORE_PIN17_BIT)) CORE_PIN17_CONFIG = CONFIG_PULLUP;

  547. 		}

  548. 		if (val & (1<<4)) {

  549. 			digitalWriteFast(18, HIGH);

  550. 			if (!(CORE_PIN18_DDRREG & CORE_PIN18_BIT)) CORE_PIN18_CONFIG = CONFIG_PULLUP;

  551. 		}

  552. 		if (val & (1<<5)) {

  553. 			digitalWriteFast(19, HIGH);

  554. 			if (!(CORE_PIN19_DDRREG & CORE_PIN19_BIT)) CORE_PIN19_CONFIG = CONFIG_PULLUP;

  555. 		}

  556. 		return *this;

  557. 	}

  558. 	inline PORTCemulation & operator &= (int val) __attribute__((always_inline)) {

  559. 		if (!(val & (1<<0))) {

  560. 			digitalWriteFast(14, LOW);

  561. 			if (!(CORE_PIN14_DDRREG & CORE_PIN14_BIT)) CORE_PIN14_CONFIG = CONFIG_NOPULLUP;

  562. 		}

  563. 		if (!(val & (1<<1))) {

  564. 			digitalWriteFast(15, LOW);

  565. 			if (!(CORE_PIN15_DDRREG & CORE_PIN15_BIT)) CORE_PIN15_CONFIG = CONFIG_NOPULLUP;

  566. 		}

  567. 		if (!(val & (1<<2))) {

  568. 			digitalWriteFast(16, LOW);

  569. 			if (!(CORE_PIN16_DDRREG & CORE_PIN16_BIT)) CORE_PIN16_CONFIG = CONFIG_NOPULLUP;

  570. 		}

  571. 		if (!(val & (1<<3))) {

  572. 			digitalWriteFast(17, LOW);

  573. 			if (!(CORE_PIN17_DDRREG & CORE_PIN17_BIT)) CORE_PIN17_CONFIG = CONFIG_NOPULLUP;

  574. 		}

  575. 		if (!(val & (1<<4))) {

  576. 			digitalWriteFast(18, LOW);

  577. 			if (!(CORE_PIN18_DDRREG & CORE_PIN18_BIT)) CORE_PIN18_CONFIG = CONFIG_NOPULLUP;

  578. 		}

  579. 		if (!(val & (1<<5))) {

  580. 			digitalWriteFast(19, LOW);

  581. 			if (!(CORE_PIN19_DDRREG & CORE_PIN19_BIT)) CORE_PIN19_CONFIG = CONFIG_NOPULLUP;

  582. 		}

  583. 		return *this;

  584. 	}

  585. };

  586. extern PORTCemulation PORTC;

  587. 

  588. class PINCemulation

  589. {

  590. public:

  591. 	inline int operator & (int val) const __attribute__((always_inline)) {

  592. 		int ret = 0;

  593. 		if ((val & (1<<0)) && digitalReadFast(8)) ret |= (1<<0);

  594. 		if ((val & (1<<1)) && digitalReadFast(9)) ret |= (1<<1);

  595. 		if ((val & (1<<2)) && digitalReadFast(10)) ret |= (1<<2);

  596. 		if ((val & (1<<3)) && digitalReadFast(11)) ret |= (1<<3);

  597. 		if ((val & (1<<4)) && digitalReadFast(12)) ret |= (1<<4);

  598. 		if ((val & (1<<5)) && digitalReadFast(13)) ret |= (1<<5);

  599. 		return ret;

  600. 	}

  601. 	operator int () const __attribute__((always_inline)) {

  602. 		int ret = 0;

  603. 		if (digitalReadFast(8)) ret |= (1<<0);

  604. 		if (digitalReadFast(9)) ret |= (1<<1);

  605. 		if (digitalReadFast(10)) ret |= (1<<2);

  606. 		if (digitalReadFast(11)) ret |= (1<<3);

  607. 		if (digitalReadFast(12)) ret |= (1<<4);

  608. 		if (digitalReadFast(13)) ret |= (1<<5);

  609. 		return ret;

  610. 	}

  611. };

  612. extern PINCemulation PINC;

  613. 

  614. class DDRCemulation

  615. {

  616. public:

  617. 	inline DDRCemulation & operator = (int val) __attribute__((always_inline)) {

  618. 		if (val & (1<<0)) set0(); else clr0();

  619. 		if (val & (1<<1)) set1(); else clr1();

  620. 		if (val & (1<<2)) set2(); else clr2();

  621. 		if (val & (1<<3)) set3(); else clr3();

  622. 		if (val & (1<<4)) set4(); else clr4();

  623. 		if (val & (1<<5)) set5(); else clr5();

  624. 		return *this;

  625. 	}

  626. 	inline DDRCemulation & operator |= (int val) __attribute__((always_inline)) {

  627. 		if (val & (1<<0)) set0();

  628. 		if (val & (1<<1)) set1();

  629. 		if (val & (1<<2)) set2();

  630. 		if (val & (1<<3)) set3();

  631. 		if (val & (1<<4)) set4();

  632. 		if (val & (1<<5)) set5();

  633. 		return *this;

  634. 	}

  635. 	inline DDRCemulation & operator &= (int val) __attribute__((always_inline)) {

  636. 		if (!(val & (1<<0))) clr0();

  637. 		if (!(val & (1<<1))) clr1();

  638. 		if (!(val & (1<<2))) clr2();

  639. 		if (!(val & (1<<3))) clr3();

  640. 		if (!(val & (1<<4))) clr4();

  641. 		if (!(val & (1<<5))) clr5();

  642. 		return *this;

  643. 	}

  644. private:

  645. 	inline void set0() __attribute__((always_inline)) {

  646. 		GPIO_SETBIT_ATOMIC(CORE_PIN14_DDRREG, CORE_PIN14_BIT);

  647. 		CORE_PIN14_CONFIG = CONFIG_PULLUP;

  648. 	}

  649. 	inline void set1() __attribute__((always_inline)) {

  650. 		GPIO_SETBIT_ATOMIC(CORE_PIN15_DDRREG, CORE_PIN15_BIT);

  651. 		CORE_PIN15_CONFIG = CONFIG_PULLUP;

  652. 	}

  653. 	inline void set2() __attribute__((always_inline)) {

  654. 		GPIO_SETBIT_ATOMIC(CORE_PIN16_DDRREG, CORE_PIN16_BIT);

  655. 		CORE_PIN16_CONFIG = CONFIG_PULLUP;

  656. 	}

  657. 	inline void set3() __attribute__((always_inline)) {

  658. 		GPIO_SETBIT_ATOMIC(CORE_PIN17_DDRREG, CORE_PIN17_BIT);

  659. 		CORE_PIN17_CONFIG = CONFIG_PULLUP;

  660. 	}

  661. 	inline void set4() __attribute__((always_inline)) {

  662. 		GPIO_SETBIT_ATOMIC(CORE_PIN18_DDRREG, CORE_PIN18_BIT);

  663. 		CORE_PIN18_CONFIG = CONFIG_PULLUP;

  664. 	}

  665. 	inline void set5() __attribute__((always_inline)) {

  666. 		GPIO_SETBIT_ATOMIC(CORE_PIN19_DDRREG, CORE_PIN19_BIT);

  667. 		CORE_PIN19_CONFIG = CONFIG_PULLUP;

  668. 	}

  669. 	inline void clr0() __attribute__((always_inline)) {

  670. 		CORE_PIN14_CONFIG = ((CORE_PIN14_PORTREG & CORE_PIN14_BITMASK)

  671. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  672. 		GPIO_CLRBIT_ATOMIC(CORE_PIN14_DDRREG, CORE_PIN14_BIT);

  673. 	}

  674. 	inline void clr1() __attribute__((always_inline)) {

  675. 		CORE_PIN15_CONFIG = ((CORE_PIN15_PORTREG & CORE_PIN15_BITMASK)

  676. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  677. 		GPIO_CLRBIT_ATOMIC(CORE_PIN15_DDRREG, CORE_PIN15_BIT);

  678. 	}

  679. 	inline void clr2() __attribute__((always_inline)) {

  680. 		CORE_PIN16_CONFIG = ((CORE_PIN16_PORTREG & CORE_PIN16_BITMASK)

  681. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  682. 		GPIO_CLRBIT_ATOMIC(CORE_PIN16_DDRREG, CORE_PIN16_BIT);

  683. 	}

  684. 	inline void clr3() __attribute__((always_inline)) {

  685. 		CORE_PIN17_CONFIG = ((CORE_PIN17_PORTREG & CORE_PIN17_BITMASK)

  686. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  687. 		GPIO_CLRBIT_ATOMIC(CORE_PIN17_DDRREG, CORE_PIN17_BIT);

  688. 	}

  689. 	inline void clr4() __attribute__((always_inline)) {

  690. 		CORE_PIN18_CONFIG = ((CORE_PIN18_PORTREG & CORE_PIN18_BITMASK)

  691. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  692. 		GPIO_CLRBIT_ATOMIC(CORE_PIN18_DDRREG, CORE_PIN18_BIT);

  693. 	}

  694. 	inline void clr5() __attribute__((always_inline)) {

  695. 		CORE_PIN19_CONFIG = ((CORE_PIN19_PORTREG & CORE_PIN19_BITMASK)

  696. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  697. 		GPIO_CLRBIT_ATOMIC(CORE_PIN19_DDRREG, CORE_PIN19_BIT);

  698. 	}

  699. };

  700. 

  701. extern DDRCemulation DDRC;

  702. 

  703. 

  704. #define PINB0 0

  705. #define PINB1 1

  706. #define PINB2 2

  707. #define PINB3 3

  708. #define PINB4 4

  709. #define PINB5 5

  710. #define PINB6 6

  711. #define PINB7 7

  712. #define DDB0 0

  713. #define DDB1 1

  714. #define DDB2 2

  715. #define DDB3 3

  716. #define DDB4 4

  717. #define DDB5 5

  718. #define DDB6 6

  719. #define DDB7 7

  720. #define PORTB0 0

  721. #define PORTB1 1

  722. #define PORTB2 2

  723. #define PORTB3 3

  724. #define PORTB4 4

  725. #define PORTB5 5

  726. #define PORTB6 6

  727. #define PORTB7 7

  728. #define PINC0 0

  729. #define PINC1 1

  730. #define PINC2 2

  731. #define PINC3 3

  732. #define PINC4 4

  733. #define PINC5 5

  734. #define PINC6 6

  735. #define DDC0 0

  736. #define DDC1 1

  737. #define DDC2 2

  738. #define DDC3 3

  739. #define DDC4 4

  740. #define DDC5 5

  741. #define DDC6 6

  742. #define PORTC0 0

  743. #define PORTC1 1

  744. #define PORTC2 2

  745. #define PORTC3 3

  746. #define PORTC4 4

  747. #define PORTC5 5

  748. #define PORTC6 6

  749. #define PIND0 0

  750. #define PIND1 1

  751. #define PIND2 2

  752. #define PIND3 3

  753. #define PIND4 4

  754. #define PIND5 5

  755. #define PIND6 6

  756. #define PIND7 7

  757. #define DDD0 0

  758. #define DDD1 1

  759. #define DDD2 2

  760. #define DDD3 3

  761. #define DDD4 4

  762. #define DDD5 5

  763. #define DDD6 6

  764. #define DDD7 7

  765. #define PORTD0 0

  766. #define PORTD1 1

  767. #define PORTD2 2

  768. #define PORTD3 3

  769. #define PORTD4 4

  770. #define PORTD5 5

  771. #define PORTD6 6

  772. #define PORTD7 7

  773. 

  774. 

  775. 

  776. 

  777. 

  778. #if 0

  779. extern "C" {

  780. void serial_print(const char *p);

  781. void serial_phex(uint32_t n);

  782. void serial_phex16(uint32_t n);

  783. void serial_phex32(uint32_t n);

  784. }

  785. #endif

  786. 

  787. 

  788. // SPI Control Register ­ SPCR

  789. #define SPIE	7	// SPI Interrupt Enable - not supported

  790. #define SPE	6	// SPI Enable

  791. #define DORD	5	// DORD: Data Order

  792. #define MSTR	4	// MSTR: Master/Slave Select

  793. #define CPOL	3	// CPOL: Clock Polarity

  794. #define CPHA	2	// CPHA: Clock Phase

  795. #define SPR1	1	// Clock: 3 = 125 kHz, 2 = 250 kHz, 1 = 1 MHz, 0->4 MHz

  796. #define SPR0	0

  797. // SPI Status Register ­ SPSR

  798. #define SPIF	7	// SPIF: SPI Interrupt Flag

  799. #define WCOL	6	// WCOL: Write COLlision Flag - not implemented

  800. #define SPI2X	0	// SPI2X: Double SPI Speed Bit

  801. // SPI Data Register ­ SPDR

  802. 

  803. 

  804. class SPCRemulation;

  805. class SPSRemulation;

  806. class SPDRemulation;

  807. 

  808. #if defined(KINETISK)

  809. 

  810. class SPCRemulation

  811. {

  812. public:

  813. 	inline SPCRemulation & operator = (int val) __attribute__((always_inline)) {

  814. 		uint32_t ctar, mcr, sim6;

  815. 		//serial_print("SPCR=");

  816. 		//serial_phex(val);

  817. 		//serial_print("\n");

  818. 		sim6 = SIM_SCGC6;

  819. 		if (!(sim6 & SIM_SCGC6_SPI0)) {

  820. 			//serial_print("init1\n");

  821. 			SIM_SCGC6 = sim6 | SIM_SCGC6_SPI0;

  822. 			SPI0_CTAR0 = SPI_CTAR_FMSZ(7) | SPI_CTAR_PBR(1) | SPI_CTAR_BR(1) | SPI_CTAR_CSSCK(1);

  823. 		}

  824. 		if (!(val & (1<<SPE))) {

  825. 			SPI0_MCR |= SPI_MCR_MDIS; // TODO: use bitband for atomic access

  826. 		}

  827. 		ctar = SPI_CTAR_FMSZ(7) | SPI_CTAR_PBR(1);

  828. 		if (val & (1<<DORD))  ctar |= SPI_CTAR_LSBFE;

  829. 		if (val & (1<<CPOL))  ctar |= SPI_CTAR_CPOL;

  830. 		if (val & (1<<CPHA)) {

  831. 			ctar |= SPI_CTAR_CPHA;

  832. 			if ((val & 3) == 0) {

  833. 				ctar |= SPI_CTAR_BR(1) | SPI_CTAR_ASC(1);

  834. 			} else if ((val & 3) == 1) {

  835. 				ctar |= SPI_CTAR_BR(4) | SPI_CTAR_ASC(4);

  836. 			} else if ((val & 3) == 2) {

  837. 				ctar |= SPI_CTAR_BR(6) | SPI_CTAR_ASC(6);

  838. 			} else {

  839. 				ctar |= SPI_CTAR_BR(7) | SPI_CTAR_ASC(7);

  840. 			}

  841. 		} else {

  842. 			if ((val & 3) == 0) {

  843. 				ctar |= SPI_CTAR_BR(1) | SPI_CTAR_CSSCK(1);

  844. 			} else if ((val & 3) == 1) {

  845. 				ctar |= SPI_CTAR_BR(4) | SPI_CTAR_CSSCK(4);

  846. 			} else if ((val & 3) == 2) {

  847. 				ctar |= SPI_CTAR_BR(6) | SPI_CTAR_CSSCK(6);

  848. 			} else {

  849. 				ctar |= SPI_CTAR_BR(7) | SPI_CTAR_CSSCK(7);

  850. 			}

  851. 		}

  852. 		ctar |= (SPI0_CTAR0 & SPI_CTAR_DBR);

  853. 		update_ctar(ctar);

  854. 		mcr = SPI_MCR_DCONF(0) | SPI_MCR_PCSIS(0x1F);

  855. 		if (val & (1<<MSTR)) mcr |= SPI_MCR_MSTR;

  856. 		if (val & (1<<SPE)) {

  857. 			mcr &= ~(SPI_MCR_MDIS | SPI_MCR_HALT);

  858. 			SPI0_MCR = mcr;

  859. 			enable_pins();

  860. 		} else {

  861. 			mcr |= (SPI_MCR_MDIS | SPI_MCR_HALT);

  862. 			SPI0_MCR = mcr;

  863. 			disable_pins();

  864. 		}

  865. 		//serial_print("MCR:");

  866. 		//serial_phex32(SPI0_MCR);

  867. 		//serial_print(", CTAR0:");

  868. 		//serial_phex32(SPI0_CTAR0);

  869. 		//serial_print("\n");

  870. 		return *this;

  871. 	}

  872. 	inline SPCRemulation & operator |= (int val) __attribute__((always_inline)) {

  873. 		uint32_t sim6;

  874. 		//serial_print("SPCR |= ");

  875. 		//serial_phex(val);

  876. 		//serial_print("\n");

  877. 		sim6 = SIM_SCGC6;

  878. 		if (!(sim6 & SIM_SCGC6_SPI0)) {

  879. 			//serial_print("init2\n");

  880. 			SIM_SCGC6 = sim6 | SIM_SCGC6_SPI0;

  881. 			SPI0_CTAR0 = SPI_CTAR_FMSZ(7) | SPI_CTAR_PBR(1) | SPI_CTAR_BR(1);

  882. 		}

  883. 		if (val & ((1<<DORD)|(1<<CPOL)|(1<<CPHA)|3)) {

  884. 			uint32_t ctar = SPI0_CTAR0;

  885. 			if (val & (1<<DORD)) ctar |= SPI_CTAR_LSBFE; // TODO: use bitband

  886. 			if (val & (1<<CPOL)) ctar |= SPI_CTAR_CPOL;

  887. 			if ((val & 3) == 1) {

  888. 				// TODO: implement - is this ever really needed

  889. 			} else if ((val & 3) == 2) {

  890. 				// TODO: implement - is this ever really needed

  891. 			} else if ((val & 3) == 3) {

  892. 				// TODO: implement - is this ever really needed

  893. 			}

  894. 			if (val & (1<<CPHA) && !(ctar & SPI_CTAR_CPHA)) {

  895. 				ctar |= SPI_CTAR_CPHA;

  896. 				// TODO: clear SPI_CTAR_CSSCK, set SPI_CTAR_ASC

  897. 			}

  898. 			update_ctar(ctar);

  899. 		}

  900. 		if (val & (1<<MSTR)) SPI0_MCR |= SPI_MCR_MSTR;

  901. 		if (val & (1<<SPE)) {

  902. 			SPI0_MCR &= ~(SPI_MCR_MDIS | SPI_MCR_HALT);

  903. 			enable_pins();

  904. 		}

  905. 		//serial_print("MCR:");

  906. 		//serial_phex32(SPI0_MCR);

  907. 		//serial_print(", CTAR0:");

  908. 		//serial_phex32(SPI0_CTAR0);

  909. 		//serial_print("\n");

  910. 		return *this;

  911. 	}

  912. 	inline SPCRemulation & operator &= (int val) __attribute__((always_inline)) {

  913. 		//serial_print("SPCR &= ");

  914. 		//serial_phex(val);

  915. 		//serial_print("\n");

  916. 		SIM_SCGC6 |= SIM_SCGC6_SPI0;

  917. 		if (!(val & (1<<SPE))) {

  918. 			SPI0_MCR |= (SPI_MCR_MDIS | SPI_MCR_HALT);

  919. 			disable_pins();

  920. 		}

  921. 		if ((val & ((1<<DORD)|(1<<CPOL)|(1<<CPHA)|3)) != ((1<<DORD)|(1<<CPOL)|(1<<CPHA)|3)) {

  922. 			uint32_t ctar = SPI0_CTAR0;

  923. 			if (!(val & (1<<DORD))) ctar &= ~SPI_CTAR_LSBFE; // TODO: use bitband

  924. 			if (!(val & (1<<CPOL))) ctar &= ~SPI_CTAR_CPOL;

  925. 			if ((val & 3) == 0) {

  926. 				// TODO: implement - is this ever really needed

  927. 			} else if ((val & 3) == 1) {

  928. 				// TODO: implement - is this ever really needed

  929. 			} else if ((val & 3) == 2) {

  930. 				// TODO: implement - is this ever really needed

  931. 			}

  932. 			if (!(val & (1<<CPHA)) && (ctar & SPI_CTAR_CPHA)) {

  933. 				ctar &= ~SPI_CTAR_CPHA;

  934. 				// TODO: set SPI_CTAR_ASC, clear SPI_CTAR_CSSCK

  935. 			}

  936. 			update_ctar(ctar);

  937. 		}

  938. 		if (!(val & (1<<MSTR))) SPI0_MCR &= ~SPI_MCR_MSTR;

  939. 		return *this;

  940. 	}

  941. 	inline int operator & (int val) const __attribute__((always_inline)) {

  942. 		int ret = 0;

  943. 		//serial_print("SPCR & ");

  944. 		//serial_phex(val);

  945. 		//serial_print("\n");

  946. 		SIM_SCGC6 |= SIM_SCGC6_SPI0;

  947. 		if ((val & (1<<DORD)) && (SPI0_CTAR0 & SPI_CTAR_LSBFE)) ret |= (1<<DORD);

  948. 		if ((val & (1<<CPOL)) && (SPI0_CTAR0 & SPI_CTAR_CPOL)) ret |= (1<<CPOL);

  949. 		if ((val & (1<<CPHA)) && (SPI0_CTAR0 & SPI_CTAR_CPHA)) ret |= (1<<CPHA);

  950. 		if ((val & 3) == 3) {

  951. 			uint32_t dbr = SPI0_CTAR0 & 15;

  952. 			if (dbr <= 1) {

  953. 			} else if (dbr <= 4) {

  954. 				ret |= (1<<SPR0);

  955. 			} else if (dbr <= 6) {

  956. 				ret |= (1<<SPR1);

  957. 			} else {

  958. 				ret |= (1<<SPR1)|(1<<SPR0);

  959. 			}

  960. 		} else if ((val & 3) == 1) {

  961. 			// TODO: implement - is this ever really needed

  962. 		} else if ((val & 3) == 2) {

  963. 			// TODO: implement - is this ever really needed

  964. 		}

  965. 		if (val & (1<<SPE) && (!(SPI0_MCR & SPI_MCR_MDIS))) ret |= (1<<SPE);

  966. 		if (val & (1<<MSTR) && (SPI0_MCR & SPI_MCR_MSTR)) ret |= (1<<MSTR);

  967. 		//serial_print("ret = ");

  968. 		//serial_phex(ret);

  969. 		//serial_print("\n");

  970. 		return ret;

  971. 	}

  972. 	operator int () const __attribute__((always_inline)) {

  973. 		int ret = 0;

  974. 		if ((SIM_SCGC6 & SIM_SCGC6_SPI0)) {

  975. 			int ctar = SPI0_CTAR0;

  976. 			if (ctar & SPI_CTAR_LSBFE) ret |= (1<<DORD);

  977. 			if (ctar & SPI_CTAR_CPOL) ret |= (1<<CPOL);

  978. 			if (ctar & SPI_CTAR_CPHA) ret |= (1<<CPHA);

  979. 			ctar &= 15;

  980. 			if (ctar <= 1) {

  981. 			} else if (ctar <= 4) {

  982. 				ret |= (1<<SPR0);

  983. 			} else if (ctar <= 6) {

  984. 				ret |= (1<<SPR1);

  985. 			} else {

  986. 				ret |= (1<<SPR1)|(1<<SPR0);

  987. 			}

  988. 			int mcr = SPI0_MCR;

  989. 			if (!(mcr & SPI_MCR_MDIS)) ret |= (1<<SPE);

  990. 			if (mcr & SPI_MCR_MSTR) ret |= (1<<MSTR);

  991. 		}

  992. 		return ret;

  993. 	}

  994. 	inline void setMOSI(uint8_t pin) __attribute__((always_inline)) {

  995. 		if (pin == 11) pinout &= ~1;

  996. 		if (pin == 7) pinout |= 1;

  997. 	}

  998. 	inline void setMISO(uint8_t pin) __attribute__((always_inline)) {

  999. 		if (pin == 12) pinout &= ~2;

  1000. 		if (pin == 8) pinout |= 2;

  1001. 	}

  1002. 	inline void setSCK(uint8_t pin) __attribute__((always_inline)) {

  1003. 		if (pin == 13) pinout &= ~4;

  1004. 		if (pin == 14) pinout |= 4;

  1005. 	}

  1006. 	friend class SPSRemulation;

  1007. 	friend class SPIFIFOclass;

  1008. private:

  1009. 	static inline void update_ctar(uint32_t ctar) __attribute__((always_inline)) {

  1010. 		if (SPI0_CTAR0 == ctar) return;

  1011. 		uint32_t mcr = SPI0_MCR;

  1012. 		if (mcr & SPI_MCR_MDIS) {

  1013. 			SPI0_CTAR0 = ctar;

  1014. 		} else {

  1015. 			SPI0_MCR = mcr | SPI_MCR_MDIS | SPI_MCR_HALT;

  1016. 			SPI0_CTAR0 = ctar;

  1017. 			SPI0_MCR = mcr;

  1018. 		}

  1019. 	}

  1020. 	static uint8_t pinout;

  1021. public:

  1022. 	inline void enable_pins(void) __attribute__((always_inline)) {

  1023. 		//serial_print("enable_pins\n");

  1024. 		if ((pinout & 1) == 0) {

  1025. 			CORE_PIN11_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(2); // DOUT/MOSI = 11 (PTC6)

  1026. 		} else {

  1027. 			CORE_PIN7_CONFIG = PORT_PCR_MUX(2); // DOUT/MOSI = 7 (PTD2)

  1028. 		}

  1029. 		if ((pinout & 2) == 0) {

  1030. 			CORE_PIN12_CONFIG = PORT_PCR_MUX(2);  // DIN/MISO = 12 (PTC7)

  1031. 		} else {

  1032. 			CORE_PIN8_CONFIG = PORT_PCR_MUX(2);  // DIN/MISO = 8 (PTD3)

  1033. 		}

  1034. 		if ((pinout & 4) == 0) {

  1035. 			CORE_PIN13_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(2); // SCK = 13 (PTC5)

  1036. 		} else {

  1037. 			CORE_PIN14_CONFIG = PORT_PCR_MUX(2); // SCK = 14 (PTD1)

  1038. 		}

  1039. 	}

  1040. 	inline void disable_pins(void) __attribute__((always_inline)) {

  1041. 		//serial_print("disable_pins\n");

  1042. 		if ((pinout & 1) == 0) {

  1043. 			CORE_PIN11_CONFIG = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);

  1044. 		} else {

  1045. 			CORE_PIN7_CONFIG = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);

  1046. 		}

  1047. 		if ((pinout & 2) == 0) {

  1048. 			CORE_PIN12_CONFIG = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);

  1049. 		} else {

  1050. 			CORE_PIN8_CONFIG = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);

  1051. 		}

  1052. 		if ((pinout & 4) == 0) {

  1053. 			CORE_PIN13_CONFIG = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);

  1054. 		} else {

  1055. 			CORE_PIN14_CONFIG = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);

  1056. 		}

  1057. 	}

  1058. };

  1059. extern SPCRemulation SPCR;

  1060. 

  1061. class SPSRemulation

  1062. {

  1063. public:

  1064. 	inline SPSRemulation & operator = (int val) __attribute__((always_inline)) {

  1065. 		//serial_print("SPSR=");

  1066. 		//serial_phex(val);

  1067. 		//serial_print("\n");

  1068. 		uint32_t ctar = SPI0_CTAR0;

  1069. 		if (val & (1<<SPI2X)) {

  1070. 			ctar |= SPI_CTAR_DBR;

  1071. 		} else {

  1072. 			ctar &= ~SPI_CTAR_DBR;

  1073. 		}

  1074. 		SPCRemulation::update_ctar(ctar);

  1075. 		//serial_print("MCR:");

  1076. 		//serial_phex32(SPI0_MCR);

  1077. 		//serial_print(", CTAR0:");

  1078. 		//serial_phex32(SPI0_CTAR0);

  1079. 		//serial_print("\n");

  1080. 		return *this;

  1081. 	}

  1082. 	inline SPSRemulation & operator |= (int val) __attribute__((always_inline)) {

  1083. 		//serial_print("SPSR |= ");

  1084. 		//serial_phex(val);

  1085. 		//serial_print("\n");

  1086. 		if (val & (1<<SPI2X)) SPCRemulation::update_ctar(SPI0_CTAR0 |= SPI_CTAR_DBR);

  1087. 		return *this;

  1088. 	}

  1089. 	inline SPSRemulation & operator &= (int val) __attribute__((always_inline)) {

  1090. 		//serial_print("SPSR &= ");

  1091. 		//serial_phex(val);

  1092. 		//serial_print("\n");

  1093. 		if (!(val & (1<<SPI2X))) SPCRemulation::update_ctar(SPI0_CTAR0 &= ~SPI_CTAR_DBR);

  1094. 		return *this;

  1095. 	}

  1096. 	inline int operator & (int val) const __attribute__((always_inline)) {

  1097. 		int ret = 0;

  1098. 		//serial_print("SPSR & ");

  1099. 		//serial_phex(val);

  1100. 		//serial_print("\n");

  1101. 		// TODO: using SPI_SR_TCF isn't quite right.  Control returns to the

  1102. 		// caller after the final edge that captures data, which is 1/2 cycle

  1103. 		// sooner than AVR returns.  At 500 kHz and slower SPI, this can make

  1104. 		// a difference when digitalWrite is used to manually control the CS

  1105. 		// pin, and perhaps it could matter at high clocks if faster register

  1106. 		// access is used?  But does it really matter?  Do any SPI chips in

  1107. 		// practice really perform differently if CS negates early, after the

  1108. 		// final bit is clocked, but before the end of the whole clock cycle?

  1109. 		if ((val & (1<<SPIF)) && (SPI0_SR & SPI_SR_TCF)) ret = (1<<SPIF);

  1110. 		if ((val & (1<<SPI2X)) && (SPI0_CTAR0 & SPI_CTAR_DBR)) ret |= (1<<SPI2X);

  1111. 		//delayMicroseconds(50000);

  1112. 		return ret;

  1113. 	}

  1114. 	operator int () const __attribute__((always_inline)) {

  1115. 		int ret = 0;

  1116. 		//serial_print("SPSR (int)\n");

  1117. 		if (SPI0_SR & SPI_SR_TCF) ret = (1<<SPIF);

  1118. 		if (SPI0_CTAR0 & SPI_CTAR_DBR) ret |= (1<<SPI2X);

  1119. 		return ret;

  1120. 	}

  1121. };

  1122. extern SPSRemulation SPSR;

  1123. 

  1124. class SPDRemulation

  1125. {

  1126. public:

  1127. 	inline SPDRemulation & operator = (int val) __attribute__((always_inline)) {

  1128. 		//serial_print("SPDR = ");

  1129. 		//serial_phex(val);

  1130. 		//serial_print("\n");

  1131. 		SPI0_MCR |= SPI_MCR_CLR_RXF; // discard any received data

  1132. 		SPI0_SR = SPI_SR_TCF;

  1133. 		//SPI0_SR = SPI_SR_EOQF;

  1134. 		//SPI0_PUSHR = (val & 255) | SPI0_PUSHR_EOQ;

  1135. 		SPI0_PUSHR = (val & 255);

  1136. 		return *this;

  1137. 	}

  1138. 	operator int () const __attribute__((always_inline)) {

  1139. 		uint32_t val;

  1140. 		val = SPI0_POPR & 255;

  1141. 		//serial_print("SPDR (int) ");

  1142. 		//serial_phex(val);

  1143. 		//serial_print("\n");

  1144. 		return val;

  1145. 	}

  1146. };

  1147. extern SPDRemulation SPDR;

  1148. 

  1149. 

  1150. 

  1151. 

  1152. 

  1153. #elif defined(KINETISL)

  1154. 

  1155. // SPI Control Register ­ SPCR

  1156. //#define SPIE	7	// SPI Interrupt Enable - not supported

  1157. //#define SPE	6	// SPI Enable

  1158. //#define DORD	5	// DORD: Data Order

  1159. //#define MSTR	4	// MSTR: Master/Slave Select

  1160. //#define CPOL	3	// CPOL: Clock Polarity

  1161. //#define CPHA	2	// CPHA: Clock Phase

  1162. //#define SPR1	1	// Clock: 3 = 125 kHz, 2 = 250 kHz, 1 = 1 MHz, 0->4 MHz

  1163. //#define SPR0	0

  1164. // SPI Status Register ­ SPSR

  1165. //#define SPIF	7	// SPIF: SPI Interrupt Flag

  1166. //#define WCOL	6	// WCOL: Write COLlision Flag - not implemented

  1167. //#define SPI2X	0	// SPI2X: Double SPI Speed Bit

  1168. // SPI Data Register ­ SPDR

  1169. 

  1170. 

  1171. class SPCRemulation

  1172. {

  1173. public:

  1174. 	inline SPCRemulation & operator = (int val) __attribute__((always_inline)) {

  1175. 		uint32_t sim4 = SIM_SCGC4;

  1176. 		if (!(sim4 & SIM_SCGC4_SPI0)) {

  1177. 			SIM_SCGC4 = sim4 | SIM_SCGC4_SPI0;

  1178. 			SPI0_BR = SPI_BR_SPR(0) | SPI_BR_SPPR(1);

  1179. 		}

  1180. 		uint32_t c1 = 0;

  1181. 		if (val & (1<<DORD))  c1 |= SPI_C1_LSBFE;

  1182. 		if (val & (1<<CPOL))  c1 |= SPI_C1_CPOL;

  1183. 		if (val & (1<<CPHA))  c1 |= SPI_C1_CPHA;

  1184. 		if (val & (1<<MSTR))  c1 |= SPI_C1_MSTR;

  1185. 		if (val & (1<<SPE))   c1 |= SPI_C1_SPE;

  1186. 		SPI0_C1 = c1;

  1187. 		SPI0_C2 = 0;

  1188. 		uint32_t br = SPI0_BR & 0x10;

  1189. 		switch (val & 3) {

  1190. 		  case 0:  SPI0_BR = br | SPI_BR_SPR(0); break;

  1191. 		  case 1:  SPI0_BR = br | SPI_BR_SPR(2); break;

  1192. 		  case 2:  SPI0_BR = br | SPI_BR_SPR(4); break;

  1193. 		  default: SPI0_BR = br | SPI_BR_SPR(5); break;

  1194. 		}

  1195. 		if (val & (1<<SPE)) enable_pins();

  1196. 		else disable_pins();

  1197. 		return *this;

  1198. 	}

  1199. 	inline SPCRemulation & operator |= (int val) __attribute__((always_inline)) {

  1200. 		uint32_t sim4 = SIM_SCGC4;

  1201. 		if (!(sim4 & SIM_SCGC4_SPI0)) {

  1202. 			SIM_SCGC4 = sim4 | SIM_SCGC4_SPI0;

  1203. 			SPI0_BR = SPI_BR_SPR(0) | SPI_BR_SPPR(1);

  1204. 		}

  1205. 		uint32_t c1 = SPI0_C1;

  1206. 		if (val & (1<<DORD))  c1 |= SPI_C1_LSBFE;

  1207. 		if (val & (1<<CPOL))  c1 |= SPI_C1_CPOL;

  1208. 		if (val & (1<<CPHA))  c1 |= SPI_C1_CPHA;

  1209. 		if (val & (1<<MSTR))  c1 |= SPI_C1_MSTR;

  1210. 		if (val & (1<<SPE)) {

  1211. 			enable_pins();

  1212. 			c1 |= SPI_C1_SPE;

  1213. 		}

  1214. 		SPI0_C1 = c1;

  1215. 		SPI0_C2 = 0;

  1216. 		val &= 3;

  1217. 		if (val) {

  1218. 			uint32_t br = SPI0_BR;

  1219. 			uint32_t bits = baud2avr(br) | val;

  1220. 			br &= 0x10;

  1221. 			switch (bits) {

  1222. 			  case 0:  SPI0_BR = br | SPI_BR_SPR(0); break;

  1223. 			  case 1:  SPI0_BR = br | SPI_BR_SPR(2); break;

  1224. 			  case 2:  SPI0_BR = br | SPI_BR_SPR(4); break;

  1225. 			  default: SPI0_BR = br | SPI_BR_SPR(5); break;

  1226. 			}

  1227. 		}

  1228. 		return *this;

  1229. 	}

  1230. 	inline SPCRemulation & operator &= (int val) __attribute__((always_inline)) {

  1231. 		uint32_t sim4 = SIM_SCGC4;

  1232. 		if (!(sim4 & SIM_SCGC4_SPI0)) {

  1233. 			SIM_SCGC4 = sim4 | SIM_SCGC4_SPI0;

  1234. 			SPI0_BR = SPI_BR_SPR(0) | SPI_BR_SPPR(1);

  1235. 		}

  1236. 		uint32_t c1 = SPI0_C1;

  1237. 		if (!(val & (1<<DORD)))  c1 &= ~SPI_C1_LSBFE;

  1238. 		if (!(val & (1<<CPOL)))  c1 &= ~SPI_C1_CPOL;

  1239. 		if (!(val & (1<<CPHA)))  c1 &= ~SPI_C1_CPHA;

  1240. 		if (!(val & (1<<MSTR)))  c1 &= ~SPI_C1_MSTR;

  1241. 		if (!(val & (1<<SPE))) {

  1242. 			disable_pins();

  1243. 			c1 &= ~SPI_C1_SPE;

  1244. 		}

  1245. 		SPI0_C1 = c1;

  1246. 		SPI0_C2 = 0;

  1247. 		val &= 3;

  1248. 		if (val < 3) {

  1249. 			uint32_t br = SPI0_BR;

  1250. 			uint32_t bits = baud2avr(br) & val;

  1251. 			br &= 0x10;

  1252. 			switch (bits) {

  1253. 			  case 0:  SPI0_BR = br | SPI_BR_SPR(0); break;

  1254. 			  case 1:  SPI0_BR = br | SPI_BR_SPR(2); break;

  1255. 			  case 2:  SPI0_BR = br | SPI_BR_SPR(4); break;

  1256. 			  default: SPI0_BR = br | SPI_BR_SPR(5); break;

  1257. 			}

  1258. 		}

  1259. 		return *this;

  1260. 	}

  1261. 	inline int operator & (int val) const __attribute__((always_inline)) {

  1262. 		int ret = 0;

  1263. 		uint32_t sim4 = SIM_SCGC4;

  1264. 		if (!(sim4 & SIM_SCGC4_SPI0)) {

  1265. 			SIM_SCGC4 = sim4 | SIM_SCGC4_SPI0;

  1266. 			SPI0_BR = SPI_BR_SPR(0) | SPI_BR_SPPR(1);

  1267. 		}

  1268. 		uint32_t c1 = SPI0_C1;

  1269. 		if ((val & (1<<DORD)) && (c1 & SPI_C1_LSBFE)) ret |= (1<<DORD);

  1270. 		if ((val & (1<<CPOL)) && (c1 & SPI_C1_CPOL))  ret |= (1<<CPOL);

  1271. 		if ((val & (1<<CPHA)) && (c1 & SPI_C1_CPHA))  ret |= (1<<CPHA);

  1272. 		if ((val & (1<<MSTR)) && (c1 & SPI_C1_MSTR))  ret |= (1<<MSTR);

  1273. 		if ((val & (1<<SPE))  && (c1 & SPI_C1_SPE))   ret |= (1<<SPE);

  1274. 		uint32_t bits = baud2avr(SPI0_BR);

  1275. 		if ((val & (1<<SPR1)) && (bits & (1<<SPR1)))  ret |= (1<<SPR1);

  1276. 		if ((val & (1<<SPR0)) && (bits & (1<<SPR0)))  ret |= (1<<SPR0);

  1277. 		return ret;

  1278. 	}

  1279. 	operator int () const __attribute__((always_inline)) {

  1280. 		int ret = 0;

  1281. 		uint32_t sim4 = SIM_SCGC4;

  1282. 		if (!(sim4 & SIM_SCGC4_SPI0)) {

  1283. 			SIM_SCGC4 = sim4 | SIM_SCGC4_SPI0;

  1284. 			SPI0_BR = SPI_BR_SPR(0) | SPI_BR_SPPR(1);

  1285. 		}

  1286. 		uint32_t c1 = SPI0_C1;

  1287. 		if ((c1 & SPI_C1_LSBFE)) ret |= (1<<DORD);

  1288. 		if ((c1 & SPI_C1_CPOL))  ret |= (1<<CPOL);

  1289. 		if ((c1 & SPI_C1_CPHA))  ret |= (1<<CPHA);

  1290. 		if ((c1 & SPI_C1_MSTR))  ret |= (1<<MSTR);

  1291. 		if ((c1 & SPI_C1_SPE))   ret |= (1<<SPE);

  1292. 		ret |= baud2avr(SPI0_BR);

  1293. 		return ret;

  1294. 	}

  1295. 	inline void setMOSI(uint8_t pin) __attribute__((always_inline)) {

  1296. 		if (pin == 11) pinout &= ~1;

  1297. 		if (pin == 7) pinout |= 1;

  1298. 	}

  1299. 	inline void setMISO(uint8_t pin) __attribute__((always_inline)) {

  1300. 		if (pin == 12) pinout &= ~2;

  1301. 		if (pin == 8) pinout |= 2;

  1302. 	}

  1303. 	inline void setSCK(uint8_t pin) __attribute__((always_inline)) {

  1304. 		if (pin == 13) pinout &= ~4;

  1305. 		if (pin == 14) pinout |= 4;

  1306. 	}

  1307. 	friend class SPSRemulation;

  1308. 	friend class SPIFIFOclass;

  1309. private:

  1310. 	static inline uint32_t baud2avr(uint32_t br) __attribute__((always_inline)) {

  1311. 		br &= 15;

  1312. 		if (br == 0) return 0;

  1313. 		if (br <= 2) return 1;

  1314. 		if (br <= 4) return 2;

  1315. 		return 3;

  1316. 	}

  1317. 	static uint8_t pinout;

  1318. public:

  1319. 	inline void enable_pins(void) __attribute__((always_inline)) {

  1320. 		//serial_print("enable_pins\n");

  1321. 		if ((pinout & 1) == 0) {

  1322. 			CORE_PIN11_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(2); // MOSI0 = 11 (PTC6)

  1323. 		} else {

  1324. 			CORE_PIN7_CONFIG = PORT_PCR_MUX(2); // MOSI0 = 7 (PTD2)

  1325. 		}

  1326. 		if ((pinout & 2) == 0) {

  1327. 			CORE_PIN12_CONFIG = PORT_PCR_MUX(2);  // MISO0 = 12 (PTC7)

  1328. 		} else {

  1329. 			CORE_PIN8_CONFIG = PORT_PCR_MUX(2);  // MISO0 = 8 (PTD3)

  1330. 		}

  1331. 		if ((pinout & 4) == 0) {

  1332. 			CORE_PIN13_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(2); // SCK0 = 13 (PTC5)

  1333. 		} else {

  1334. 			CORE_PIN14_CONFIG = PORT_PCR_MUX(2); // SCK0 = 14 (PTD1)

  1335. 		}

  1336. 	}

  1337. 	inline void disable_pins(void) __attribute__((always_inline)) {

  1338. 		//serial_print("disable_pins\n");

  1339. 		if ((pinout & 1) == 0) {

  1340. 			CORE_PIN11_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1);

  1341. 		} else {

  1342. 			CORE_PIN7_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1);

  1343. 		}

  1344. 		if ((pinout & 2) == 0) {

  1345. 			CORE_PIN12_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1);

  1346. 		} else {

  1347. 			CORE_PIN8_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1);

  1348. 		}

  1349. 		if ((pinout & 4) == 0) {

  1350. 			CORE_PIN13_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1);

  1351. 		} else {

  1352. 			CORE_PIN14_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1);

  1353. 		}

  1354. 	}

  1355. };

  1356. extern SPCRemulation SPCR;

  1357. 

  1358. 

  1359. class SPCR1emulation

  1360. {

  1361. public:

  1362. 	inline void setMOSI(uint8_t pin) __attribute__((always_inline)) {

  1363. 		if (pin == 0) pinout &= ~1; // MOSI1 = 0  (PTB16)

  1364. 		if (pin == 21) pinout |= 1; // MOSI1 = 21 (PTD6)

  1365. 	}

  1366. 	inline void setMISO(uint8_t pin) __attribute__((always_inline)) {

  1367. 		if (pin == 1) pinout &= ~2; // MISO1 = 1  (PTB17)

  1368. 		if (pin == 5) pinout |= 2;  // MISO1 = 5  (PTD7)

  1369. 	}

  1370. 	inline void setSCK(uint8_t pin) __attribute__((always_inline)) {

  1371. 		// SCK1 = 20 (PTD5) - no alternative pin

  1372. 	}

  1373. 	inline void enable_pins(void) __attribute__((always_inline)) {

  1374. 		//serial_print("enable_pins\n");

  1375. 		if ((pinout & 1) == 0) {

  1376. 			CORE_PIN0_CONFIG = PORT_PCR_MUX(2);  // MOSI1 = 0  (PTB16)

  1377. 		} else {

  1378. 			CORE_PIN21_CONFIG = PORT_PCR_MUX(2); // MOSI1 = 21 (PTD6)

  1379. 		}

  1380. 		if ((pinout & 2) == 0) {

  1381. 			CORE_PIN1_CONFIG = PORT_PCR_MUX(2);  // MISO1 = 1  (PTB17)

  1382. 		} else {

  1383. 			CORE_PIN5_CONFIG = PORT_PCR_MUX(2);  // MISO1 = 5  (PTD7)

  1384. 		}

  1385. 		CORE_PIN20_CONFIG = PORT_PCR_MUX(2); // SCK1 = 20 (PTD5)

  1386. 	}

  1387. 	inline void disable_pins(void) __attribute__((always_inline)) {

  1388. 		//serial_print("disable_pins\n");

  1389. 		if ((pinout & 1) == 0) {

  1390. 			CORE_PIN0_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1);

  1391. 		} else {

  1392. 			CORE_PIN21_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1);

  1393. 		}

  1394. 		if ((pinout & 2) == 0) {

  1395. 			CORE_PIN1_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1);

  1396. 		} else {

  1397. 			CORE_PIN5_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1);

  1398. 		}

  1399. 		CORE_PIN20_CONFIG = PORT_PCR_SRE | PORT_PCR_MUX(1);

  1400. 	}

  1401. 	friend class SPIFIFO1class;

  1402. private:

  1403. 	static uint8_t pinout;

  1404. };

  1405. extern SPCR1emulation SPCR1;

  1406. 

  1407. 

  1408. class SPSRemulation

  1409. {

  1410. public:

  1411. 	inline SPSRemulation & operator = (int val) __attribute__((always_inline)) {

  1412. 		if (val & (1<<SPI2X)) {

  1413. 			SPI0_BR &= ~0x10;

  1414. 		} else {

  1415. 			SPI0_BR |= 0x10;

  1416. 		}

  1417. 		return *this;

  1418. 	}

  1419. 	inline SPSRemulation & operator |= (int val) __attribute__((always_inline)) {

  1420. 		if (val & (1<<SPI2X)) SPI0_BR &= ~0x10;

  1421. 		return *this;

  1422. 	}

  1423. 	inline SPSRemulation & operator &= (int val) __attribute__((always_inline)) {

  1424. 		if (!(val & (1<<SPI2X))) SPI0_BR |= 0x10;

  1425. 		return *this;

  1426. 	}

  1427. 	inline int operator & (int val) const __attribute__((always_inline)) {

  1428. 		int ret = 0;

  1429. 		if ((val & (1<<SPIF)) && (SPI0_S & SPI_S_SPRF)) ret = (1<<SPIF);

  1430. 		if ((val & (1<<SPI2X)) && (!(SPI0_BR & 0x10))) ret |= (1<<SPI2X);

  1431. 		return ret;

  1432. 	}

  1433. 	operator int () const __attribute__((always_inline)) {

  1434. 		int ret = 0;

  1435. 		if ((SPI0_S & SPI_S_SPRF)) ret = (1<<SPIF);

  1436. 		if (!(SPI0_BR & 0x10)) ret |= (1<<SPI2X);

  1437. 		return ret;

  1438. 	}

  1439. };

  1440. extern SPSRemulation SPSR;

  1441. 

  1442. 

  1443. class SPDRemulation

  1444. {

  1445. public:

  1446. 	inline SPDRemulation & operator = (int val) __attribute__((always_inline)) {

  1447. 		if ((SPI0_S & SPI_S_SPTEF)) {

  1448. 			uint32_t tmp __attribute__((unused)) = SPI0_DL;

  1449. 		}

  1450. 		SPI0_DL = val;

  1451. 		return *this;

  1452. 	}

  1453. 	operator int () const __attribute__((always_inline)) {

  1454. 		return SPI0_DL & 255;

  1455. 	}

  1456. };

  1457. extern SPDRemulation SPDR;

  1458. 

  1459. 

  1460. #endif // KINETISK

  1461. 

  1462. 

  1463. 

  1464. 

  1465. 

  1466. 

  1467. 

  1468. 

  1469. class SREGemulation

  1470. {

  1471. public:

  1472. 	operator int () const __attribute__((always_inline)) {

  1473. 		uint32_t primask;

  1474. 		asm volatile("mrs %0, primask\n" : "=r" (primask)::);

  1475. 		if (primask) return 0;

  1476. 		return (1<<7);

  1477. 	}

  1478. 	inline SREGemulation & operator = (int val) __attribute__((always_inline)) {

  1479. 		if (val & (1<<7)) {

  1480. 			__enable_irq();

  1481. 		} else {

  1482. 			__disable_irq();

  1483. 		}

  1484. 		return *this;

  1485. 	}

  1486. };

  1487. extern SREGemulation SREG;

  1488. 

  1489. 

  1490. 		// 22211  

  1491. 		// 84062840

  1492. 		// 322111 

  1493. 		// 17395173

  1494. #if defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__)

  1495. 

  1496. #if defined(__MK20DX128__) || defined(__MK20DX256__)

  1497. #define EIMSK_pA 0x01000018 // pins 3, 4, 24

  1498. #define EIMSK_pB 0x020F0003 // pins 0, 1, 16-19, 25

  1499. #define EIMSK_pC 0x78C0BE00 // pins 9-13, 15, 22, 23, 27-30

  1500. #define EIMSK_pD 0x003041E4 // pins 2, 5-8, 14, 20, 21

  1501. #define EIMSK_pE 0x84000000 // pins 26, 31

  1502. #elif defined(__MK64FX512__) || defined(__MK66FX1M0__)

  1503. #define EIMSK_pA 0x1E000018 // pins 3, 4, 25-28

  1504. #define EIMSK_pB 0xE00F0003 // pins 0, 1, 16-19, 29-31

  1505. #define EIMSK_pC 0x00C0BE00 // pins 9-13, 15, 22, 23

  1506. #define EIMSK_pD 0x003041E4 // pins 2, 5-8, 14, 20, 21

  1507. #define EIMSK_pE 0x01000000 // pins 24

  1508. #endif

  1509. 

  1510. class EIMSKemulation  // used by Adafruit_nRF8001 (only supports INT for pins 0 to 31)

  1511. {

  1512. public:

  1513. 	operator int () const __attribute__((always_inline)) {

  1514. 		int mask = 0;

  1515. 		volatile const uint32_t *icer = &NVIC_ICER0;

  1516. 		if (icer[IRQ_PORTA >> 5] & (1 << (IRQ_PORTA & 31))) mask |= EIMSK_pA;

  1517. 		if (icer[IRQ_PORTB >> 5] & (1 << (IRQ_PORTB & 31))) mask |= EIMSK_pB;

  1518. 		if (icer[IRQ_PORTC >> 5] & (1 << (IRQ_PORTC & 31))) mask |= EIMSK_pC;

  1519. 		if (icer[IRQ_PORTD >> 5] & (1 << (IRQ_PORTD & 31))) mask |= EIMSK_pD;

  1520. 		if (icer[IRQ_PORTE >> 5] & (1 << (IRQ_PORTE & 31))) mask |= EIMSK_pE;

  1521. 		return mask;

  1522. 	}

  1523. 	inline EIMSKemulation & operator |= (int val) __attribute__((always_inline)) {

  1524. 		if (val & EIMSK_pA) NVIC_ENABLE_IRQ(IRQ_PORTA);

  1525. 		if (val & EIMSK_pB) NVIC_ENABLE_IRQ(IRQ_PORTB);

  1526. 		if (val & EIMSK_pC) NVIC_ENABLE_IRQ(IRQ_PORTC);

  1527. 		if (val & EIMSK_pD) NVIC_ENABLE_IRQ(IRQ_PORTD);

  1528. 		if (val & EIMSK_pE) NVIC_ENABLE_IRQ(IRQ_PORTE);

  1529. 		return *this;

  1530. 	}

  1531. 	inline EIMSKemulation & operator &= (int val) __attribute__((always_inline)) {

  1532. 		uint32_t n = val;

  1533. 		if ((n | ~EIMSK_pA) != 0xFFFFFFFF) NVIC_DISABLE_IRQ(IRQ_PORTA);

  1534. 		if ((n | ~EIMSK_pB) != 0xFFFFFFFF) NVIC_DISABLE_IRQ(IRQ_PORTB);

  1535. 		if ((n | ~EIMSK_pC) != 0xFFFFFFFF) NVIC_DISABLE_IRQ(IRQ_PORTC);

  1536. 		if ((n | ~EIMSK_pD) != 0xFFFFFFFF) NVIC_DISABLE_IRQ(IRQ_PORTD);

  1537. 		if ((n | ~EIMSK_pE) != 0xFFFFFFFF) NVIC_DISABLE_IRQ(IRQ_PORTE);

  1538. 		return *this;

  1539. 	}

  1540. };

  1541. extern EIMSKemulation EIMSK;

  1542. 

  1543. #elif defined(__MKL26Z64__)

  1544. 

  1545. #define EIMSK_pA 0x00000018 // pins 3, 4, 24

  1546. #define EIMSK_pC 0x00C0BE00 // pins 9-13, 15, 22, 23

  1547. #define EIMSK_pD 0x003041E4 // pins 2, 5-8, 14, 20, 21

  1548. 

  1549. class EIMSKemulation  // used by Adafruit_nRF8001

  1550. {

  1551. public:

  1552. 	operator int () const __attribute__((always_inline)) {

  1553. 		int mask = 0;

  1554. 		volatile const uint32_t *icer = &NVIC_ICER0;

  1555. 		if (icer[IRQ_PORTA >> 5] & (1 << (IRQ_PORTA & 31))) mask |= EIMSK_pA;

  1556. 		if (icer[IRQ_PORTCD >> 5] & (1 << (IRQ_PORTCD & 31))) mask |= (EIMSK_pC | EIMSK_pD);

  1557. 		return mask;

  1558. 	}

  1559. 	inline EIMSKemulation & operator |= (int val) __attribute__((always_inline)) {

  1560. 		if (val & EIMSK_pA) NVIC_ENABLE_IRQ(IRQ_PORTA);

  1561. 		if (val & (EIMSK_pC | EIMSK_pD)) NVIC_ENABLE_IRQ(IRQ_PORTCD);

  1562. 		return *this;

  1563. 	}

  1564. 	inline EIMSKemulation & operator &= (int val) __attribute__((always_inline)) {

  1565. 		uint32_t n = val;

  1566. 		if ((n | ~EIMSK_pA) != 0xFFFFFFFF) NVIC_DISABLE_IRQ(IRQ_PORTA);

  1567. 		if ((n | ~(EIMSK_pC | EIMSK_pD)) != 0xFFFFFFFF) NVIC_DISABLE_IRQ(IRQ_PORTCD);

  1568. 		return *this;

  1569. 	}

  1570. };

  1571. extern EIMSKemulation EIMSK;

  1572. 

  1573. #endif

  1574. 

  1575. 

  1576. // these are not intended for public consumption...

  1577. #undef GPIO_BITBAND_ADDR

  1578. #undef CONFIG_PULLUP

  1579. #undef CONFIG_NOPULLUP

  1580. #undef GPIO_SETBIT_ATOMIC

  1581. #undef GPIO_CLRBIT_ATOMIC

  1582. 

  1583. #endif // __cplusplus

  1584. 

  1585. #endif