Teensy 4.1 core updated for C++20
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  1. /* Teensyduino Core Library
  2. * http://www.pjrc.com/teensy/
  3. * Copyright (c) 2019 PJRC.COM, LLC.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * 1. The above copyright notice and this permission notice shall be
  14. * included in all copies or substantial portions of the Software.
  15. *
  16. * 2. If the Software is incorporated into a build system that allows
  17. * selection among a list of target devices, then similar target
  18. * devices manufactured by PJRC.COM must be included in the list of
  19. * target devices and selectable in the same manner.
  20. *
  21. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  24. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  25. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  26. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  27. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  28. * SOFTWARE.
  29. */
  30. // To configure the EEPROM size, edit E2END in avr/eeprom.h.
  31. //
  32. // Generally you should avoid editing this code, unless you really
  33. // know what you're doing.
  34. #include "imxrt.h"
  35. #include <avr/eeprom.h>
  36. #include <string.h>
  37. #include "debug/printf.h"
  38. #define FLASH_BASEADDR 0x601F0000
  39. #define FLASH_SECTORS 15
  40. #if E2END > (255*FLASH_SECTORS-1)
  41. #error "E2END is set larger than the maximum possible EEPROM size"
  42. #endif
  43. // Conversation about how this code works & what the upper limits are
  44. // https://forum.pjrc.com/threads/57377?p=214566&viewfull=1#post214566
  45. static void flash_write(void *addr, const void *data, uint32_t len);
  46. static void flash_erase_sector(void *addr);
  47. static uint8_t initialized=0;
  48. static uint16_t sector_index[FLASH_SECTORS];
  49. void eeprom_initialize(void)
  50. {
  51. uint32_t sector;
  52. //printf("eeprom init\n");
  53. for (sector=0; sector < FLASH_SECTORS; sector++) {
  54. const uint16_t *p = (uint16_t *)(FLASH_BASEADDR + sector * 4096);
  55. const uint16_t *end = (uint16_t *)(FLASH_BASEADDR + (sector + 1) * 4096);
  56. uint16_t index = 0;
  57. do {
  58. if (*p++ == 0xFFFF) break;
  59. index++;
  60. } while (p < end);
  61. sector_index[sector] = index;
  62. }
  63. initialized = 1;
  64. }
  65. uint8_t eeprom_read_byte(const uint8_t *addr_ptr)
  66. {
  67. uint32_t addr = (uint32_t)addr_ptr;
  68. uint32_t sector, offset;
  69. const uint16_t *p, *end;
  70. uint8_t data=0xFF;
  71. if (addr > E2END) return 0xFF;
  72. if (!initialized) eeprom_initialize();
  73. sector = (addr >> 2) % FLASH_SECTORS;
  74. offset = (addr & 3) | (((addr >> 2) / FLASH_SECTORS) << 2);
  75. //printf("ee_rd, addr=%u, sector=%u, offset=%u, len=%u\n",
  76. //addr, sector, offset, sector_index[sector]);
  77. p = (uint16_t *)(FLASH_BASEADDR + sector * 4096);
  78. end = p + sector_index[sector];
  79. while (p < end) {
  80. uint32_t val = *p++;
  81. if ((val & 255) == offset) data = val >> 8;
  82. }
  83. return data;
  84. }
  85. void eeprom_write_byte(uint8_t *addr_ptr, uint8_t data)
  86. {
  87. uint32_t addr = (uint32_t)addr_ptr;
  88. uint32_t sector, offset, index, i;
  89. uint16_t *p, *end;
  90. uint8_t olddata=0xFF;
  91. uint8_t buf[256];
  92. if (addr > E2END) return;
  93. if (!initialized) eeprom_initialize();
  94. sector = (addr >> 2) % FLASH_SECTORS;
  95. offset = (addr & 3) | (((addr >> 2) / FLASH_SECTORS) << 2);
  96. //printf("ee_wr, addr=%u, sector=%u, offset=%u, len=%u\n",
  97. //addr, sector, offset, sector_index[sector]);
  98. p = (uint16_t *)(FLASH_BASEADDR + sector * 4096);
  99. end = p + sector_index[sector];
  100. while (p < end) {
  101. uint16_t val = *p++;
  102. if ((val & 255) == offset) olddata = val >> 8;
  103. }
  104. if (data == olddata) return;
  105. if (sector_index[sector] < 2048) {
  106. //printf("ee_wr, writing\n");
  107. uint16_t newdata = offset | (data << 8);
  108. flash_write(end, &newdata, 2);
  109. sector_index[sector] = sector_index[sector] + 1;
  110. } else {
  111. //printf("ee_wr, erase then write\n");
  112. memset(buf, 0xFF, sizeof(buf));
  113. p = (uint16_t *)(FLASH_BASEADDR + sector * 4096);
  114. end = p + 2048;
  115. while (p < end) {
  116. uint16_t val = *p++;
  117. buf[val & 255] = val >> 8;
  118. }
  119. buf[offset] = data;
  120. p = (uint16_t *)(FLASH_BASEADDR + sector * 4096);
  121. flash_erase_sector(p);
  122. index = 0;
  123. for (i=0; i < 256; i++) {
  124. if (buf[i] != 0xFF) {
  125. // TODO: combining these to larger write
  126. // would (probably) be more efficient
  127. uint16_t newval = i | (buf[i] << 8);
  128. flash_write(p + index, &newval, 2);
  129. index = index + 1;
  130. }
  131. }
  132. sector_index[sector] = index;
  133. }
  134. }
  135. uint16_t eeprom_read_word(const uint16_t *addr)
  136. {
  137. const uint8_t *p = (const uint8_t *)addr;
  138. return eeprom_read_byte(p) | (eeprom_read_byte(p+1) << 8);
  139. }
  140. uint32_t eeprom_read_dword(const uint32_t *addr)
  141. {
  142. const uint8_t *p = (const uint8_t *)addr;
  143. return eeprom_read_byte(p) | (eeprom_read_byte(p+1) << 8)
  144. | (eeprom_read_byte(p+2) << 16) | (eeprom_read_byte(p+3) << 24);
  145. }
  146. void eeprom_read_block(void *buf, const void *addr, uint32_t len)
  147. {
  148. const uint8_t *p = (const uint8_t *)addr;
  149. uint8_t *dest = (uint8_t *)buf;
  150. while (len--) {
  151. *dest++ = eeprom_read_byte(p++);
  152. }
  153. }
  154. int eeprom_is_ready(void)
  155. {
  156. return 1;
  157. }
  158. void eeprom_write_word(uint16_t *addr, uint16_t value)
  159. {
  160. uint8_t *p = (uint8_t *)addr;
  161. eeprom_write_byte(p++, value);
  162. eeprom_write_byte(p, value >> 8);
  163. }
  164. void eeprom_write_dword(uint32_t *addr, uint32_t value)
  165. {
  166. uint8_t *p = (uint8_t *)addr;
  167. eeprom_write_byte(p++, value);
  168. eeprom_write_byte(p++, value >> 8);
  169. eeprom_write_byte(p++, value >> 16);
  170. eeprom_write_byte(p, value >> 24);
  171. }
  172. void eeprom_write_block(const void *buf, void *addr, uint32_t len)
  173. {
  174. uint8_t *p = (uint8_t *)addr;
  175. const uint8_t *src = (const uint8_t *)buf;
  176. while (len--) {
  177. eeprom_write_byte(p++, *src++);
  178. }
  179. }
  180. #define LUT0(opcode, pads, operand) (FLEXSPI_LUT_INSTRUCTION((opcode), (pads), (operand)))
  181. #define LUT1(opcode, pads, operand) (FLEXSPI_LUT_INSTRUCTION((opcode), (pads), (operand)) << 16)
  182. #define CMD_SDR FLEXSPI_LUT_OPCODE_CMD_SDR
  183. #define ADDR_SDR FLEXSPI_LUT_OPCODE_RADDR_SDR
  184. #define READ_SDR FLEXSPI_LUT_OPCODE_READ_SDR
  185. #define WRITE_SDR FLEXSPI_LUT_OPCODE_WRITE_SDR
  186. #define PINS1 FLEXSPI_LUT_NUM_PADS_1
  187. #define PINS4 FLEXSPI_LUT_NUM_PADS_4
  188. static void flash_wait()
  189. {
  190. FLEXSPI_LUT60 = LUT0(CMD_SDR, PINS1, 0x05) | LUT1(READ_SDR, PINS1, 1); // 05 = read status
  191. FLEXSPI_LUT61 = 0;
  192. uint8_t status;
  193. do {
  194. FLEXSPI_IPRXFCR = FLEXSPI_IPRXFCR_CLRIPRXF; // clear rx fifo
  195. FLEXSPI_IPCR0 = 0;
  196. FLEXSPI_IPCR1 = FLEXSPI_IPCR1_ISEQID(15) | FLEXSPI_IPCR1_IDATSZ(1);
  197. FLEXSPI_IPCMD = FLEXSPI_IPCMD_TRG;
  198. while (!(FLEXSPI_INTR & FLEXSPI_INTR_IPCMDDONE)) {
  199. asm("nop");
  200. }
  201. FLEXSPI_INTR = FLEXSPI_INTR_IPCMDDONE;
  202. status = *(uint8_t *)&FLEXSPI_RFDR0;
  203. } while (status & 1);
  204. FLEXSPI_MCR0 |= FLEXSPI_MCR0_SWRESET; // purge stale data from FlexSPI's AHB FIFO
  205. while (FLEXSPI_MCR0 & FLEXSPI_MCR0_SWRESET) ; // wait
  206. __enable_irq();
  207. }
  208. // write bytes into flash memory (which is already erased to 0xFF)
  209. static void flash_write(void *addr, const void *data, uint32_t len)
  210. {
  211. __disable_irq();
  212. FLEXSPI_LUTKEY = FLEXSPI_LUTKEY_VALUE;
  213. FLEXSPI_LUTCR = FLEXSPI_LUTCR_UNLOCK;
  214. FLEXSPI_IPCR0 = 0;
  215. FLEXSPI_LUT60 = LUT0(CMD_SDR, PINS1, 0x06); // 06 = write enable
  216. FLEXSPI_LUT61 = 0;
  217. FLEXSPI_LUT62 = 0;
  218. FLEXSPI_LUT63 = 0;
  219. FLEXSPI_IPCR1 = FLEXSPI_IPCR1_ISEQID(15);
  220. FLEXSPI_IPCMD = FLEXSPI_IPCMD_TRG;
  221. arm_dcache_delete(addr, len); // purge old data from ARM's cache
  222. while (!(FLEXSPI_INTR & FLEXSPI_INTR_IPCMDDONE)) ; // wait
  223. FLEXSPI_INTR = FLEXSPI_INTR_IPCMDDONE;
  224. FLEXSPI_LUT60 = LUT0(CMD_SDR, PINS1, 0x32) | LUT1(ADDR_SDR, PINS1, 24); // 32 = quad write
  225. FLEXSPI_LUT61 = LUT0(WRITE_SDR, PINS4, 1);
  226. FLEXSPI_IPTXFCR = FLEXSPI_IPTXFCR_CLRIPTXF; // clear tx fifo
  227. FLEXSPI_IPCR0 = (uint32_t)addr & 0x001FFFFF;
  228. FLEXSPI_IPCR1 = FLEXSPI_IPCR1_ISEQID(15) | FLEXSPI_IPCR1_IDATSZ(len);
  229. FLEXSPI_IPCMD = FLEXSPI_IPCMD_TRG;
  230. const uint8_t *src = (const uint8_t *)data;
  231. uint32_t n;
  232. while (!((n = FLEXSPI_INTR) & FLEXSPI_INTR_IPCMDDONE)) {
  233. if (n & FLEXSPI_INTR_IPTXWE) {
  234. uint32_t wrlen = len;
  235. if (wrlen > 8) wrlen = 8;
  236. if (wrlen > 0) {
  237. memcpy((void *)&FLEXSPI_TFDR0, src, wrlen);
  238. src += wrlen;
  239. len -= wrlen;
  240. }
  241. FLEXSPI_INTR = FLEXSPI_INTR_IPTXWE;
  242. }
  243. }
  244. FLEXSPI_INTR = FLEXSPI_INTR_IPCMDDONE | FLEXSPI_INTR_IPTXWE;
  245. flash_wait();
  246. }
  247. // erase a 4K sector
  248. static void flash_erase_sector(void *addr)
  249. {
  250. __disable_irq();
  251. FLEXSPI_LUTKEY = FLEXSPI_LUTKEY_VALUE;
  252. FLEXSPI_LUTCR = FLEXSPI_LUTCR_UNLOCK;
  253. FLEXSPI_LUT60 = LUT0(CMD_SDR, PINS1, 0x06); // 06 = write enable
  254. FLEXSPI_LUT61 = 0;
  255. FLEXSPI_LUT62 = 0;
  256. FLEXSPI_LUT63 = 0;
  257. FLEXSPI_IPCR0 = 0;
  258. FLEXSPI_IPCR1 = FLEXSPI_IPCR1_ISEQID(15);
  259. FLEXSPI_IPCMD = FLEXSPI_IPCMD_TRG;
  260. arm_dcache_delete((void *)((uint32_t)addr & 0xFFFFF000), 4096); // purge data from cache
  261. while (!(FLEXSPI_INTR & FLEXSPI_INTR_IPCMDDONE)) ; // wait
  262. FLEXSPI_INTR = FLEXSPI_INTR_IPCMDDONE;
  263. FLEXSPI_LUT60 = LUT0(CMD_SDR, PINS1, 0x20) | LUT1(ADDR_SDR, PINS1, 24); // 20 = sector erase
  264. FLEXSPI_IPCR0 = (uint32_t)addr & 0x001FF000;
  265. FLEXSPI_IPCR1 = FLEXSPI_IPCR1_ISEQID(15);
  266. FLEXSPI_IPCMD = FLEXSPI_IPCMD_TRG;
  267. while (!(FLEXSPI_INTR & FLEXSPI_INTR_IPCMDDONE)) ; // wait
  268. FLEXSPI_INTR = FLEXSPI_INTR_IPCMDDONE;
  269. flash_wait();
  270. }