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Teensy 4.1 core updated for C++20
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teensy-core-4.1/teensy3/avr_emulation.h

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  1. /* Teensyduino Core Library

  2.  * http://www.pjrc.com/teensy/

  3.  * Copyright (c) 2013 PJRC.COM, LLC.

  4.  *

  5.  * Permission is hereby granted, free of charge, to any person obtaining

  6.  * a copy of this software and associated documentation files (the

  7.  * "Software"), to deal in the Software without restriction, including

  8.  * without limitation the rights to use, copy, modify, merge, publish,

  9.  * distribute, sublicense, and/or sell copies of the Software, and to

  10.  * permit persons to whom the Software is furnished to do so, subject to

  11.  * the following conditions:

  12.  *

  13.  * 1. The above copyright notice and this permission notice shall be 

  14.  * included in all copies or substantial portions of the Software.

  15.  *

  16.  * 2. If the Software is incorporated into a build system that allows 

  17.  * selection among a list of target devices, then similar target

  18.  * devices manufactured by PJRC.COM must be included in the list of

  19.  * target devices and selectable in the same manner.

  20.  *

  21.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

  22.  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

  23.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

  24.  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS

  25.  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN

  26.  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

  27.  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

  28.  * SOFTWARE.

  29.  */

  30. 

  31. #ifndef _avr_emulation_h_

  32. #define _avr_emulation_h_

  33. 

  34. #include "mk20dx128.h"

  35. #include "core_pins.h"

  36. #include "pins_arduino.h"

  37. 

  38. #ifdef __cplusplus

  39. 

  40. #define GPIO_BITBAND_ADDR(reg, bit) (((uint32_t)&(reg) - 0x40000000) * 32 + (bit) * 4 + 0x42000000)

  41. #define GPIO_BITBAND(reg, bit) (*(uint32_t *)GPIO_BITBAND_ADDR((reg), (bit)))

  42. #define CONFIG_PULLUP (PORT_PCR_MUX(1) | PORT_PCR_PE | PORT_PCR_PS)

  43. #define CONFIG_NOPULLUP (PORT_PCR_MUX(1))

  44. 

  45. class PORTDemulation

  46. {

  47. public:

  48. 	inline PORTDemulation & operator = (int val) __attribute__((always_inline)) {

  49. 		digitalWriteFast(0, (val & (1<<0)));

  50. 		if (!(CORE_PIN0_DDRREG & CORE_PIN0_BIT)) 

  51. 			CORE_PIN0_CONFIG = ((val & (1<<0)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  52. 		digitalWriteFast(1, (val & (1<<1)));

  53. 		if (!(CORE_PIN1_DDRREG & CORE_PIN1_BIT)) 

  54. 			CORE_PIN1_CONFIG = ((val & (1<<1)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  55. 		digitalWriteFast(2, (val & (1<<2)));

  56. 		if (!(CORE_PIN2_DDRREG & CORE_PIN2_BIT)) 

  57. 			CORE_PIN2_CONFIG = ((val & (1<<2)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  58. 		digitalWriteFast(3, (val & (1<<3)));

  59. 		if (!(CORE_PIN3_DDRREG & CORE_PIN3_BIT)) 

  60. 			CORE_PIN3_CONFIG = ((val & (1<<3)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  61. 		digitalWriteFast(4, (val & (1<<4)));

  62. 		if (!(CORE_PIN4_DDRREG & CORE_PIN4_BIT)) 

  63. 			CORE_PIN4_CONFIG = ((val & (1<<4)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  64. 		digitalWriteFast(5, (val & (1<<5)));

  65. 		if (!(CORE_PIN5_DDRREG & CORE_PIN5_BIT)) 

  66. 			CORE_PIN5_CONFIG = ((val & (1<<5)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  67. 		digitalWriteFast(6, (val & (1<<6)));

  68. 		if (!(CORE_PIN6_DDRREG & CORE_PIN6_BIT)) 

  69. 			CORE_PIN6_CONFIG = ((val & (1<<6)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  70. 		digitalWriteFast(7, (val & (1<<7)));

  71. 		if (!(CORE_PIN7_DDRREG & CORE_PIN7_BIT)) 

  72. 			CORE_PIN7_CONFIG = ((val & (1<<7)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  73. 		return *this;

  74. 	}

  75. 	inline PORTDemulation & operator |= (int val) __attribute__((always_inline)) {

  76. 		if (val & (1<<0)) {

  77. 			digitalWriteFast(0, HIGH);

  78. 			if (!(CORE_PIN0_DDRREG & CORE_PIN0_BIT)) CORE_PIN0_CONFIG = CONFIG_PULLUP;

  79. 		}

  80. 		if (val & (1<<1)) {

  81. 			digitalWriteFast(1, HIGH);

  82. 			if (!(CORE_PIN1_DDRREG & CORE_PIN1_BIT)) CORE_PIN1_CONFIG = CONFIG_PULLUP;

  83. 		}

  84. 		if (val & (1<<2)) {

  85. 			digitalWriteFast(2, HIGH);

  86. 			if (!(CORE_PIN2_DDRREG & CORE_PIN2_BIT)) CORE_PIN2_CONFIG = CONFIG_PULLUP;

  87. 		}

  88. 		if (val & (1<<3)) {

  89. 			digitalWriteFast(3, HIGH);

  90. 			if (!(CORE_PIN3_DDRREG & CORE_PIN3_BIT)) CORE_PIN3_CONFIG = CONFIG_PULLUP;

  91. 		}

  92. 		if (val & (1<<4)) {

  93. 			digitalWriteFast(4, HIGH);

  94. 			if (!(CORE_PIN4_DDRREG & CORE_PIN4_BIT)) CORE_PIN4_CONFIG = CONFIG_PULLUP;

  95. 		}

  96. 		if (val & (1<<5)) {

  97. 			digitalWriteFast(5, HIGH);

  98. 			if (!(CORE_PIN5_DDRREG & CORE_PIN5_BIT)) CORE_PIN5_CONFIG = CONFIG_PULLUP;

  99. 		}

  100. 		if (val & (1<<6)) {

  101. 			digitalWriteFast(6, HIGH);

  102. 			if (!(CORE_PIN6_DDRREG & CORE_PIN6_BIT)) CORE_PIN6_CONFIG = CONFIG_PULLUP;

  103. 		}

  104. 		if (val & (1<<7)) {

  105. 			digitalWriteFast(7, HIGH);

  106. 			if (!(CORE_PIN7_DDRREG & CORE_PIN7_BIT)) CORE_PIN7_CONFIG = CONFIG_PULLUP;

  107. 		}

  108. 		return *this;

  109. 	}

  110. 	inline PORTDemulation & operator &= (int val) __attribute__((always_inline)) {

  111. 		if (!(val & (1<<0))) {

  112. 			digitalWriteFast(0, LOW);

  113. 			if (!(CORE_PIN0_DDRREG & CORE_PIN0_BIT)) CORE_PIN0_CONFIG = CONFIG_NOPULLUP;

  114. 		}

  115. 		if (!(val & (1<<1))) {

  116. 			digitalWriteFast(1, LOW);

  117. 			if (!(CORE_PIN1_DDRREG & CORE_PIN1_BIT)) CORE_PIN1_CONFIG = CONFIG_NOPULLUP;

  118. 		}

  119. 		if (!(val & (1<<2))) {

  120. 			digitalWriteFast(2, LOW);

  121. 			if (!(CORE_PIN2_DDRREG & CORE_PIN2_BIT)) CORE_PIN2_CONFIG = CONFIG_NOPULLUP;

  122. 		}

  123. 		if (!(val & (1<<3))) {

  124. 			digitalWriteFast(3, LOW);

  125. 			if (!(CORE_PIN3_DDRREG & CORE_PIN3_BIT)) CORE_PIN3_CONFIG = CONFIG_NOPULLUP;

  126. 		}

  127. 		if (!(val & (1<<4))) {

  128. 			digitalWriteFast(4, LOW);

  129. 			if (!(CORE_PIN4_DDRREG & CORE_PIN4_BIT)) CORE_PIN4_CONFIG = CONFIG_NOPULLUP;

  130. 		}

  131. 		if (!(val & (1<<5))) {

  132. 			digitalWriteFast(5, LOW);

  133. 			if (!(CORE_PIN5_DDRREG & CORE_PIN5_BIT)) CORE_PIN5_CONFIG = CONFIG_NOPULLUP;

  134. 		}

  135. 		if (!(val & (1<<6))) {

  136. 			digitalWriteFast(6, LOW);

  137. 			if (!(CORE_PIN6_DDRREG & CORE_PIN6_BIT)) CORE_PIN6_CONFIG = CONFIG_NOPULLUP;

  138. 		}

  139. 		if (!(val & (1<<7))) {

  140. 			digitalWriteFast(7, LOW);

  141. 			if (!(CORE_PIN7_DDRREG & CORE_PIN7_BIT)) CORE_PIN7_CONFIG = CONFIG_NOPULLUP;

  142. 		}

  143. 		return *this;

  144. 	}

  145. };

  146. extern PORTDemulation PORTD;

  147. 

  148. class PINDemulation

  149. {

  150. public:

  151. 	inline int operator & (int val) const __attribute__((always_inline)) {

  152. 		int ret = 0;

  153. 		if ((val & (1<<0)) && digitalReadFast(0)) ret |= (1<<0);

  154. 		if ((val & (1<<1)) && digitalReadFast(1)) ret |= (1<<1);

  155. 		if ((val & (1<<2)) && digitalReadFast(2)) ret |= (1<<2);

  156. 		if ((val & (1<<3)) && digitalReadFast(3)) ret |= (1<<3);

  157. 		if ((val & (1<<4)) && digitalReadFast(4)) ret |= (1<<4);

  158. 		if ((val & (1<<5)) && digitalReadFast(5)) ret |= (1<<5);

  159. 		if ((val & (1<<6)) && digitalReadFast(6)) ret |= (1<<6);

  160. 		if ((val & (1<<7)) && digitalReadFast(7)) ret |= (1<<7);

  161. 		return ret;

  162. 	}

  163. 	operator int () const __attribute__((always_inline)) {

  164. 		int ret = 0;

  165. 		if (digitalReadFast(0)) ret |= (1<<0);

  166. 		if (digitalReadFast(1)) ret |= (1<<1);

  167. 		if (digitalReadFast(2)) ret |= (1<<2);

  168. 		if (digitalReadFast(3)) ret |= (1<<3);

  169. 		if (digitalReadFast(4)) ret |= (1<<4);

  170. 		if (digitalReadFast(5)) ret |= (1<<5);

  171. 		if (digitalReadFast(6)) ret |= (1<<6);

  172. 		if (digitalReadFast(7)) ret |= (1<<7);

  173. 		return ret;

  174. 	}

  175. };

  176. extern PINDemulation PIND;

  177. 

  178. class DDRDemulation

  179. {

  180. public:

  181. 	inline DDRDemulation & operator = (int val) __attribute__((always_inline)) {

  182. 		if (val & (1<<0)) set0(); else clr0();

  183. 		if (val & (1<<1)) set1(); else clr1();

  184. 		if (val & (1<<2)) set2(); else clr2();

  185. 		if (val & (1<<3)) set3(); else clr3();

  186. 		if (val & (1<<4)) set4(); else clr4();

  187. 		if (val & (1<<5)) set5(); else clr5();

  188. 		if (val & (1<<6)) set6(); else clr6();

  189. 		if (val & (1<<7)) set7(); else clr7();

  190. 		return *this;

  191. 	}

  192. 	inline DDRDemulation & operator |= (int val) __attribute__((always_inline)) {

  193. 		if (val & (1<<0)) set0();

  194. 		if (val & (1<<1)) set1();

  195. 		if (val & (1<<2)) set2();

  196. 		if (val & (1<<3)) set3();

  197. 		if (val & (1<<4)) set4();

  198. 		if (val & (1<<5)) set5();

  199. 		if (val & (1<<6)) set6();

  200. 		if (val & (1<<7)) set7();

  201. 		return *this;

  202. 	}

  203. 	inline DDRDemulation & operator &= (int val) __attribute__((always_inline)) {

  204. 		if (!(val & (1<<0))) clr0();

  205. 		if (!(val & (1<<1))) clr1();

  206. 		if (!(val & (1<<2))) clr2();

  207. 		if (!(val & (1<<3))) clr3();

  208. 		if (!(val & (1<<4))) clr4();

  209. 		if (!(val & (1<<5))) clr5();

  210. 		if (!(val & (1<<6))) clr6();

  211. 		if (!(val & (1<<7))) clr7();

  212. 		return *this;

  213. 	}

  214. private:

  215. 	inline void set0() __attribute__((always_inline)) {

  216. 		GPIO_BITBAND(CORE_PIN0_DDRREG, CORE_PIN0_BIT) = 1;

  217. 		CORE_PIN0_CONFIG = CONFIG_PULLUP;

  218. 	}

  219. 	inline void set1() __attribute__((always_inline)) {

  220. 		GPIO_BITBAND(CORE_PIN1_DDRREG, CORE_PIN1_BIT) = 1;

  221. 		CORE_PIN1_CONFIG = CONFIG_PULLUP;

  222. 	}

  223. 	inline void set2() __attribute__((always_inline)) {

  224. 		GPIO_BITBAND(CORE_PIN2_DDRREG, CORE_PIN2_BIT) = 1;

  225. 		CORE_PIN2_CONFIG = CONFIG_PULLUP;

  226. 	}

  227. 	inline void set3() __attribute__((always_inline)) {

  228. 		GPIO_BITBAND(CORE_PIN3_DDRREG, CORE_PIN3_BIT) = 1;

  229. 		CORE_PIN3_CONFIG = CONFIG_PULLUP;

  230. 	}

  231. 	inline void set4() __attribute__((always_inline)) {

  232. 		GPIO_BITBAND(CORE_PIN4_DDRREG, CORE_PIN4_BIT) = 1;

  233. 		CORE_PIN4_CONFIG = CONFIG_PULLUP;

  234. 	}

  235. 	inline void set5() __attribute__((always_inline)) {

  236. 		GPIO_BITBAND(CORE_PIN5_DDRREG, CORE_PIN5_BIT) = 1;

  237. 		CORE_PIN5_CONFIG = CONFIG_PULLUP;

  238. 	}

  239. 	inline void set6() __attribute__((always_inline)) {

  240. 		GPIO_BITBAND(CORE_PIN6_DDRREG, CORE_PIN6_BIT) = 1;

  241. 		CORE_PIN6_CONFIG = CONFIG_PULLUP;

  242. 	}

  243. 	inline void set7() __attribute__((always_inline)) {

  244. 		GPIO_BITBAND(CORE_PIN7_DDRREG, CORE_PIN7_BIT) = 1;

  245. 		CORE_PIN7_CONFIG = CONFIG_PULLUP;

  246. 	}

  247. 	inline void clr0() __attribute__((always_inline)) {

  248. 		CORE_PIN0_CONFIG = ((CORE_PIN0_PORTREG & CORE_PIN0_BITMASK)

  249. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  250. 		GPIO_BITBAND(CORE_PIN0_DDRREG, CORE_PIN0_BIT) = 0;

  251. 	}

  252. 	inline void clr1() __attribute__((always_inline)) {

  253. 		CORE_PIN1_CONFIG = ((CORE_PIN1_PORTREG & CORE_PIN1_BITMASK)

  254. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  255. 		GPIO_BITBAND(CORE_PIN1_DDRREG, CORE_PIN1_BIT) = 0;

  256. 	}

  257. 	inline void clr2() __attribute__((always_inline)) {

  258. 		CORE_PIN2_CONFIG = ((CORE_PIN2_PORTREG & CORE_PIN2_BITMASK)

  259. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  260. 		GPIO_BITBAND(CORE_PIN2_DDRREG, CORE_PIN2_BIT) = 0;

  261. 	}

  262. 	inline void clr3() __attribute__((always_inline)) {

  263. 		CORE_PIN3_CONFIG = ((CORE_PIN3_PORTREG & CORE_PIN3_BITMASK)

  264. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  265. 		GPIO_BITBAND(CORE_PIN3_DDRREG, CORE_PIN3_BIT) = 0;

  266. 	}

  267. 	inline void clr4() __attribute__((always_inline)) {

  268. 		CORE_PIN4_CONFIG = ((CORE_PIN4_PORTREG & CORE_PIN4_BITMASK)

  269. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  270. 		GPIO_BITBAND(CORE_PIN4_DDRREG, CORE_PIN4_BIT) = 0;

  271. 	}

  272. 	inline void clr5() __attribute__((always_inline)) {

  273. 		CORE_PIN5_CONFIG = ((CORE_PIN5_PORTREG & CORE_PIN5_BITMASK)

  274. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  275. 		GPIO_BITBAND(CORE_PIN5_DDRREG, CORE_PIN5_BIT) = 0;

  276. 	}

  277. 	inline void clr6() __attribute__((always_inline)) {

  278. 		CORE_PIN6_CONFIG = ((CORE_PIN6_PORTREG & CORE_PIN6_BITMASK)

  279. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  280. 		GPIO_BITBAND(CORE_PIN6_DDRREG, CORE_PIN6_BIT) = 0;

  281. 	}

  282. 	inline void clr7() __attribute__((always_inline)) {

  283. 		CORE_PIN7_CONFIG = ((CORE_PIN7_PORTREG & CORE_PIN7_BITMASK)

  284. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  285. 		GPIO_BITBAND(CORE_PIN7_DDRREG, CORE_PIN7_BIT) = 0;

  286. 	}

  287. };

  288. 

  289. extern DDRDemulation DDRD;

  290. 

  291. 

  292. 

  293. 

  294. 

  295. 

  296. class PORTBemulation

  297. {

  298. public:

  299. 	inline PORTBemulation & operator = (int val) __attribute__((always_inline)) {

  300. 		digitalWriteFast(8, (val & (1<<0)));

  301. 		if (!(CORE_PIN8_DDRREG & CORE_PIN8_BIT)) 

  302. 			CORE_PIN8_CONFIG = ((val & (1<<0)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  303. 		digitalWriteFast(9, (val & (1<<1)));

  304. 		if (!(CORE_PIN9_DDRREG & CORE_PIN9_BIT)) 

  305. 			CORE_PIN9_CONFIG = ((val & (1<<1)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  306. 		digitalWriteFast(10, (val & (1<<2)));

  307. 		if (!(CORE_PIN10_DDRREG & CORE_PIN10_BIT)) 

  308. 			CORE_PIN10_CONFIG = ((val & (1<<2)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  309. 		digitalWriteFast(11, (val & (1<<3)));

  310. 		if (!(CORE_PIN11_DDRREG & CORE_PIN11_BIT)) 

  311. 			CORE_PIN11_CONFIG = ((val & (1<<3)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  312. 		digitalWriteFast(12, (val & (1<<4)));

  313. 		if (!(CORE_PIN12_DDRREG & CORE_PIN12_BIT)) 

  314. 			CORE_PIN12_CONFIG = ((val & (1<<4)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  315. 		digitalWriteFast(13, (val & (1<<5)));

  316. 		if (!(CORE_PIN13_DDRREG & CORE_PIN13_BIT)) 

  317. 			CORE_PIN13_CONFIG = ((val & (1<<5)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  318. 		return *this;

  319. 	}

  320. 	inline PORTBemulation & operator |= (int val) __attribute__((always_inline)) {

  321. 		if (val & (1<<0)) {

  322. 			digitalWriteFast(8, HIGH);

  323. 			if (!(CORE_PIN7_DDRREG & CORE_PIN7_BIT)) CORE_PIN8_CONFIG = CONFIG_PULLUP;

  324. 		}

  325. 		if (val & (1<<1)) {

  326. 			digitalWriteFast(9, HIGH);

  327. 			if (!(CORE_PIN7_DDRREG & CORE_PIN7_BIT)) CORE_PIN9_CONFIG = CONFIG_PULLUP;

  328. 		}

  329. 		if (val & (1<<2)) {

  330. 			digitalWriteFast(10, HIGH);

  331. 			if (!(CORE_PIN10_DDRREG & CORE_PIN10_BIT)) CORE_PIN10_CONFIG = CONFIG_PULLUP;

  332. 		}

  333. 		if (val & (1<<3)) {

  334. 			digitalWriteFast(11, HIGH);

  335. 			if (!(CORE_PIN11_DDRREG & CORE_PIN11_BIT)) CORE_PIN11_CONFIG = CONFIG_PULLUP;

  336. 		}

  337. 		if (val & (1<<4)) {

  338. 			digitalWriteFast(12, HIGH);

  339. 			if (!(CORE_PIN12_DDRREG & CORE_PIN12_BIT)) CORE_PIN12_CONFIG = CONFIG_PULLUP;

  340. 		}

  341. 		if (val & (1<<5)) {

  342. 			digitalWriteFast(13, HIGH);

  343. 			if (!(CORE_PIN13_DDRREG & CORE_PIN13_BIT)) CORE_PIN13_CONFIG = CONFIG_PULLUP;

  344. 		}

  345. 		return *this;

  346. 	}

  347. 	inline PORTBemulation & operator &= (int val) __attribute__((always_inline)) {

  348. 		if (!(val & (1<<0))) {

  349. 			digitalWriteFast(8, LOW);

  350. 			if (!(CORE_PIN8_DDRREG & CORE_PIN8_BIT)) CORE_PIN8_CONFIG = CONFIG_NOPULLUP;

  351. 		}

  352. 		if (!(val & (1<<1))) {

  353. 			digitalWriteFast(9, LOW);

  354. 			if (!(CORE_PIN9_DDRREG & CORE_PIN9_BIT)) CORE_PIN9_CONFIG = CONFIG_NOPULLUP;

  355. 		}

  356. 		if (!(val & (1<<2))) {

  357. 			digitalWriteFast(10, LOW);

  358. 			if (!(CORE_PIN10_DDRREG & CORE_PIN10_BIT)) CORE_PIN10_CONFIG = CONFIG_NOPULLUP;

  359. 		}

  360. 		if (!(val & (1<<3))) {

  361. 			digitalWriteFast(11, LOW);

  362. 			if (!(CORE_PIN11_DDRREG & CORE_PIN11_BIT)) CORE_PIN11_CONFIG = CONFIG_NOPULLUP;

  363. 		}

  364. 		if (!(val & (1<<4))) {

  365. 			digitalWriteFast(12, LOW);

  366. 			if (!(CORE_PIN12_DDRREG & CORE_PIN12_BIT)) CORE_PIN12_CONFIG = CONFIG_NOPULLUP;

  367. 		}

  368. 		if (!(val & (1<<5))) {

  369. 			digitalWriteFast(13, LOW);

  370. 			if (!(CORE_PIN13_DDRREG & CORE_PIN13_BIT)) CORE_PIN13_CONFIG = CONFIG_NOPULLUP;

  371. 		}

  372. 		return *this;

  373. 	}

  374. };

  375. extern PORTBemulation PORTB;

  376. 

  377. class PINBemulation

  378. {

  379. public:

  380. 	inline int operator & (int val) const __attribute__((always_inline)) {

  381. 		int ret = 0;

  382. 		if ((val & (1<<0)) && digitalReadFast(8)) ret |= (1<<0);

  383. 		if ((val & (1<<1)) && digitalReadFast(9)) ret |= (1<<1);

  384. 		if ((val & (1<<2)) && digitalReadFast(10)) ret |= (1<<2);

  385. 		if ((val & (1<<3)) && digitalReadFast(11)) ret |= (1<<3);

  386. 		if ((val & (1<<4)) && digitalReadFast(12)) ret |= (1<<4);

  387. 		if ((val & (1<<5)) && digitalReadFast(13)) ret |= (1<<5);

  388. 		return ret;

  389. 	}

  390. 	operator int () const __attribute__((always_inline)) {

  391. 		int ret = 0;

  392. 		if (digitalReadFast(8)) ret |= (1<<0);

  393. 		if (digitalReadFast(9)) ret |= (1<<1);

  394. 		if (digitalReadFast(10)) ret |= (1<<2);

  395. 		if (digitalReadFast(11)) ret |= (1<<3);

  396. 		if (digitalReadFast(12)) ret |= (1<<4);

  397. 		if (digitalReadFast(13)) ret |= (1<<5);

  398. 		return ret;

  399. 	}

  400. };

  401. extern PINBemulation PINB;

  402. 

  403. class DDRBemulation

  404. {

  405. public:

  406. 	inline DDRBemulation & operator = (int val) __attribute__((always_inline)) {

  407. 		if (val & (1<<0)) set0(); else clr0();

  408. 		if (val & (1<<1)) set1(); else clr1();

  409. 		if (val & (1<<2)) set2(); else clr2();

  410. 		if (val & (1<<3)) set3(); else clr3();

  411. 		if (val & (1<<4)) set4(); else clr4();

  412. 		if (val & (1<<5)) set5(); else clr5();

  413. 		return *this;

  414. 	}

  415. 	inline DDRBemulation & operator |= (int val) __attribute__((always_inline)) {

  416. 		if (val & (1<<0)) set0();

  417. 		if (val & (1<<1)) set1();

  418. 		if (val & (1<<2)) set2();

  419. 		if (val & (1<<3)) set3();

  420. 		if (val & (1<<4)) set4();

  421. 		if (val & (1<<5)) set5();

  422. 		return *this;

  423. 	}

  424. 	inline DDRBemulation & operator &= (int val) __attribute__((always_inline)) {

  425. 		if (!(val & (1<<0))) clr0();

  426. 		if (!(val & (1<<1))) clr1();

  427. 		if (!(val & (1<<2))) clr2();

  428. 		if (!(val & (1<<3))) clr3();

  429. 		if (!(val & (1<<4))) clr4();

  430. 		if (!(val & (1<<5))) clr5();

  431. 		return *this;

  432. 	}

  433. private:

  434. 	inline void set0() __attribute__((always_inline)) {

  435. 		GPIO_BITBAND(CORE_PIN8_DDRREG, CORE_PIN8_BIT) = 1;

  436. 		CORE_PIN8_CONFIG = CONFIG_PULLUP;

  437. 	}

  438. 	inline void set1() __attribute__((always_inline)) {

  439. 		GPIO_BITBAND(CORE_PIN9_DDRREG, CORE_PIN9_BIT) = 1;

  440. 		CORE_PIN9_CONFIG = CONFIG_PULLUP;

  441. 	}

  442. 	inline void set2() __attribute__((always_inline)) {

  443. 		GPIO_BITBAND(CORE_PIN10_DDRREG, CORE_PIN10_BIT) = 1;

  444. 		CORE_PIN10_CONFIG = CONFIG_PULLUP;

  445. 	}

  446. 	inline void set3() __attribute__((always_inline)) {

  447. 		GPIO_BITBAND(CORE_PIN11_DDRREG, CORE_PIN11_BIT) = 1;

  448. 		CORE_PIN11_CONFIG = CONFIG_PULLUP;

  449. 	}

  450. 	inline void set4() __attribute__((always_inline)) {

  451. 		GPIO_BITBAND(CORE_PIN12_DDRREG, CORE_PIN12_BIT) = 1;

  452. 		CORE_PIN12_CONFIG = CONFIG_PULLUP;

  453. 	}

  454. 	inline void set5() __attribute__((always_inline)) {

  455. 		GPIO_BITBAND(CORE_PIN13_DDRREG, CORE_PIN13_BIT) = 1;

  456. 		CORE_PIN13_CONFIG = CONFIG_PULLUP;

  457. 	}

  458. 	inline void clr0() __attribute__((always_inline)) {

  459. 		CORE_PIN8_CONFIG = ((CORE_PIN8_PORTREG & CORE_PIN8_BITMASK)

  460. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  461. 		GPIO_BITBAND(CORE_PIN8_DDRREG, CORE_PIN8_BIT) = 0;

  462. 	}

  463. 	inline void clr1() __attribute__((always_inline)) {

  464. 		CORE_PIN9_CONFIG = ((CORE_PIN9_PORTREG & CORE_PIN9_BITMASK)

  465. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  466. 		GPIO_BITBAND(CORE_PIN9_DDRREG, CORE_PIN9_BIT) = 0;

  467. 	}

  468. 	inline void clr2() __attribute__((always_inline)) {

  469. 		CORE_PIN10_CONFIG = ((CORE_PIN10_PORTREG & CORE_PIN10_BITMASK)

  470. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  471. 		GPIO_BITBAND(CORE_PIN10_DDRREG, CORE_PIN10_BIT) = 0;

  472. 	}

  473. 	inline void clr3() __attribute__((always_inline)) {

  474. 		CORE_PIN11_CONFIG = ((CORE_PIN11_PORTREG & CORE_PIN11_BITMASK)

  475. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  476. 		GPIO_BITBAND(CORE_PIN11_DDRREG, CORE_PIN11_BIT) = 0;

  477. 	}

  478. 	inline void clr4() __attribute__((always_inline)) {

  479. 		CORE_PIN12_CONFIG = ((CORE_PIN12_PORTREG & CORE_PIN12_BITMASK)

  480. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  481. 		GPIO_BITBAND(CORE_PIN12_DDRREG, CORE_PIN12_BIT) = 0;

  482. 	}

  483. 	inline void clr5() __attribute__((always_inline)) {

  484. 		CORE_PIN13_CONFIG = ((CORE_PIN13_PORTREG & CORE_PIN13_BITMASK)

  485. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  486. 		GPIO_BITBAND(CORE_PIN13_DDRREG, CORE_PIN13_BIT) = 0;

  487. 	}

  488. };

  489. 

  490. extern DDRBemulation DDRB;

  491. 

  492. 

  493. 

  494. 

  495. 

  496. 

  497. class PORTCemulation

  498. {

  499. public:

  500. 	inline PORTCemulation & operator = (int val) __attribute__((always_inline)) {

  501. 		digitalWriteFast(14, (val & (1<<0)));

  502. 		if (!(CORE_PIN14_DDRREG & CORE_PIN14_BIT)) 

  503. 			CORE_PIN14_CONFIG = ((val & (1<<0)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  504. 		digitalWriteFast(15, (val & (1<<1)));

  505. 		if (!(CORE_PIN15_DDRREG & CORE_PIN15_BIT)) 

  506. 			CORE_PIN15_CONFIG = ((val & (1<<1)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  507. 		digitalWriteFast(16, (val & (1<<2)));

  508. 		if (!(CORE_PIN16_DDRREG & CORE_PIN16_BIT)) 

  509. 			CORE_PIN16_CONFIG = ((val & (1<<2)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  510. 		digitalWriteFast(17, (val & (1<<3)));

  511. 		if (!(CORE_PIN17_DDRREG & CORE_PIN17_BIT)) 

  512. 			CORE_PIN17_CONFIG = ((val & (1<<3)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  513. 		digitalWriteFast(18, (val & (1<<4)));

  514. 		if (!(CORE_PIN18_DDRREG & CORE_PIN18_BIT)) 

  515. 			CORE_PIN18_CONFIG = ((val & (1<<4)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  516. 		digitalWriteFast(19, (val & (1<<5)));

  517. 		if (!(CORE_PIN19_DDRREG & CORE_PIN19_BIT)) 

  518. 			CORE_PIN19_CONFIG = ((val & (1<<5)) ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  519. 		return *this;

  520. 	}

  521. 	inline PORTCemulation & operator |= (int val) __attribute__((always_inline)) {

  522. 		if (val & (1<<0)) {

  523. 			digitalWriteFast(14, HIGH);

  524. 			if (!(CORE_PIN14_DDRREG & CORE_PIN14_BIT)) CORE_PIN14_CONFIG = CONFIG_PULLUP;

  525. 		}

  526. 		if (val & (1<<1)) {

  527. 			digitalWriteFast(15, HIGH);

  528. 			if (!(CORE_PIN15_DDRREG & CORE_PIN15_BIT)) CORE_PIN15_CONFIG = CONFIG_PULLUP;

  529. 		}

  530. 		if (val & (1<<2)) {

  531. 			digitalWriteFast(16, HIGH);

  532. 			if (!(CORE_PIN16_DDRREG & CORE_PIN16_BIT)) CORE_PIN16_CONFIG = CONFIG_PULLUP;

  533. 		}

  534. 		if (val & (1<<3)) {

  535. 			digitalWriteFast(17, HIGH);

  536. 			if (!(CORE_PIN17_DDRREG & CORE_PIN17_BIT)) CORE_PIN17_CONFIG = CONFIG_PULLUP;

  537. 		}

  538. 		if (val & (1<<4)) {

  539. 			digitalWriteFast(18, HIGH);

  540. 			if (!(CORE_PIN18_DDRREG & CORE_PIN18_BIT)) CORE_PIN18_CONFIG = CONFIG_PULLUP;

  541. 		}

  542. 		if (val & (1<<5)) {

  543. 			digitalWriteFast(19, HIGH);

  544. 			if (!(CORE_PIN19_DDRREG & CORE_PIN19_BIT)) CORE_PIN19_CONFIG = CONFIG_PULLUP;

  545. 		}

  546. 		return *this;

  547. 	}

  548. 	inline PORTCemulation & operator &= (int val) __attribute__((always_inline)) {

  549. 		if (!(val & (1<<0))) {

  550. 			digitalWriteFast(14, LOW);

  551. 			if (!(CORE_PIN14_DDRREG & CORE_PIN14_BIT)) CORE_PIN14_CONFIG = CONFIG_NOPULLUP;

  552. 		}

  553. 		if (!(val & (1<<1))) {

  554. 			digitalWriteFast(15, LOW);

  555. 			if (!(CORE_PIN15_DDRREG & CORE_PIN15_BIT)) CORE_PIN15_CONFIG = CONFIG_NOPULLUP;

  556. 		}

  557. 		if (!(val & (1<<2))) {

  558. 			digitalWriteFast(16, LOW);

  559. 			if (!(CORE_PIN16_DDRREG & CORE_PIN16_BIT)) CORE_PIN16_CONFIG = CONFIG_NOPULLUP;

  560. 		}

  561. 		if (!(val & (1<<3))) {

  562. 			digitalWriteFast(17, LOW);

  563. 			if (!(CORE_PIN17_DDRREG & CORE_PIN17_BIT)) CORE_PIN17_CONFIG = CONFIG_NOPULLUP;

  564. 		}

  565. 		if (!(val & (1<<4))) {

  566. 			digitalWriteFast(18, LOW);

  567. 			if (!(CORE_PIN18_DDRREG & CORE_PIN18_BIT)) CORE_PIN18_CONFIG = CONFIG_NOPULLUP;

  568. 		}

  569. 		if (!(val & (1<<5))) {

  570. 			digitalWriteFast(19, LOW);

  571. 			if (!(CORE_PIN19_DDRREG & CORE_PIN19_BIT)) CORE_PIN19_CONFIG = CONFIG_NOPULLUP;

  572. 		}

  573. 		return *this;

  574. 	}

  575. };

  576. extern PORTCemulation PORTC;

  577. 

  578. class PINCemulation

  579. {

  580. public:

  581. 	inline int operator & (int val) const __attribute__((always_inline)) {

  582. 		int ret = 0;

  583. 		if ((val & (1<<0)) && digitalReadFast(8)) ret |= (1<<0);

  584. 		if ((val & (1<<1)) && digitalReadFast(9)) ret |= (1<<1);

  585. 		if ((val & (1<<2)) && digitalReadFast(10)) ret |= (1<<2);

  586. 		if ((val & (1<<3)) && digitalReadFast(11)) ret |= (1<<3);

  587. 		if ((val & (1<<4)) && digitalReadFast(12)) ret |= (1<<4);

  588. 		if ((val & (1<<5)) && digitalReadFast(13)) ret |= (1<<5);

  589. 		return ret;

  590. 	}

  591. 	operator int () const __attribute__((always_inline)) {

  592. 		int ret = 0;

  593. 		if (digitalReadFast(8)) ret |= (1<<0);

  594. 		if (digitalReadFast(9)) ret |= (1<<1);

  595. 		if (digitalReadFast(10)) ret |= (1<<2);

  596. 		if (digitalReadFast(11)) ret |= (1<<3);

  597. 		if (digitalReadFast(12)) ret |= (1<<4);

  598. 		if (digitalReadFast(13)) ret |= (1<<5);

  599. 		return ret;

  600. 	}

  601. };

  602. extern PINCemulation PINC;

  603. 

  604. class DDRCemulation

  605. {

  606. public:

  607. 	inline DDRCemulation & operator = (int val) __attribute__((always_inline)) {

  608. 		if (val & (1<<0)) set0(); else clr0();

  609. 		if (val & (1<<1)) set1(); else clr1();

  610. 		if (val & (1<<2)) set2(); else clr2();

  611. 		if (val & (1<<3)) set3(); else clr3();

  612. 		if (val & (1<<4)) set4(); else clr4();

  613. 		if (val & (1<<5)) set5(); else clr5();

  614. 		return *this;

  615. 	}

  616. 	inline DDRCemulation & operator |= (int val) __attribute__((always_inline)) {

  617. 		if (val & (1<<0)) set0();

  618. 		if (val & (1<<1)) set1();

  619. 		if (val & (1<<2)) set2();

  620. 		if (val & (1<<3)) set3();

  621. 		if (val & (1<<4)) set4();

  622. 		if (val & (1<<5)) set5();

  623. 		return *this;

  624. 	}

  625. 	inline DDRCemulation & operator &= (int val) __attribute__((always_inline)) {

  626. 		if (!(val & (1<<0))) clr0();

  627. 		if (!(val & (1<<1))) clr1();

  628. 		if (!(val & (1<<2))) clr2();

  629. 		if (!(val & (1<<3))) clr3();

  630. 		if (!(val & (1<<4))) clr4();

  631. 		if (!(val & (1<<5))) clr5();

  632. 		return *this;

  633. 	}

  634. private:

  635. 	inline void set0() __attribute__((always_inline)) {

  636. 		GPIO_BITBAND(CORE_PIN14_DDRREG, CORE_PIN14_BIT) = 1;

  637. 		CORE_PIN14_CONFIG = CONFIG_PULLUP;

  638. 	}

  639. 	inline void set1() __attribute__((always_inline)) {

  640. 		GPIO_BITBAND(CORE_PIN15_DDRREG, CORE_PIN15_BIT) = 1;

  641. 		CORE_PIN15_CONFIG = CONFIG_PULLUP;

  642. 	}

  643. 	inline void set2() __attribute__((always_inline)) {

  644. 		GPIO_BITBAND(CORE_PIN16_DDRREG, CORE_PIN16_BIT) = 1;

  645. 		CORE_PIN16_CONFIG = CONFIG_PULLUP;

  646. 	}

  647. 	inline void set3() __attribute__((always_inline)) {

  648. 		GPIO_BITBAND(CORE_PIN17_DDRREG, CORE_PIN17_BIT) = 1;

  649. 		CORE_PIN17_CONFIG = CONFIG_PULLUP;

  650. 	}

  651. 	inline void set4() __attribute__((always_inline)) {

  652. 		GPIO_BITBAND(CORE_PIN18_DDRREG, CORE_PIN18_BIT) = 1;

  653. 		CORE_PIN18_CONFIG = CONFIG_PULLUP;

  654. 	}

  655. 	inline void set5() __attribute__((always_inline)) {

  656. 		GPIO_BITBAND(CORE_PIN19_DDRREG, CORE_PIN19_BIT) = 1;

  657. 		CORE_PIN19_CONFIG = CONFIG_PULLUP;

  658. 	}

  659. 	inline void clr0() __attribute__((always_inline)) {

  660. 		CORE_PIN14_CONFIG = ((CORE_PIN14_PORTREG & CORE_PIN14_BITMASK)

  661. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  662. 		GPIO_BITBAND(CORE_PIN14_DDRREG, CORE_PIN14_BIT) = 0;

  663. 	}

  664. 	inline void clr1() __attribute__((always_inline)) {

  665. 		CORE_PIN15_CONFIG = ((CORE_PIN15_PORTREG & CORE_PIN15_BITMASK)

  666. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  667. 		GPIO_BITBAND(CORE_PIN15_DDRREG, CORE_PIN15_BIT) = 0;

  668. 	}

  669. 	inline void clr2() __attribute__((always_inline)) {

  670. 		CORE_PIN16_CONFIG = ((CORE_PIN16_PORTREG & CORE_PIN16_BITMASK)

  671. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  672. 		GPIO_BITBAND(CORE_PIN16_DDRREG, CORE_PIN16_BIT) = 0;

  673. 	}

  674. 	inline void clr3() __attribute__((always_inline)) {

  675. 		CORE_PIN17_CONFIG = ((CORE_PIN17_PORTREG & CORE_PIN17_BITMASK)

  676. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  677. 		GPIO_BITBAND(CORE_PIN17_DDRREG, CORE_PIN17_BIT) = 0;

  678. 	}

  679. 	inline void clr4() __attribute__((always_inline)) {

  680. 		CORE_PIN18_CONFIG = ((CORE_PIN18_PORTREG & CORE_PIN18_BITMASK)

  681. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  682. 		GPIO_BITBAND(CORE_PIN18_DDRREG, CORE_PIN18_BIT) = 0;

  683. 	}

  684. 	inline void clr5() __attribute__((always_inline)) {

  685. 		CORE_PIN19_CONFIG = ((CORE_PIN19_PORTREG & CORE_PIN19_BITMASK)

  686. 		  ? CONFIG_PULLUP : CONFIG_NOPULLUP);

  687. 		GPIO_BITBAND(CORE_PIN19_DDRREG, CORE_PIN19_BIT) = 0;

  688. 	}

  689. };

  690. 

  691. extern DDRCemulation DDRC;

  692. 

  693. 

  694. #define PINB0 0

  695. #define PINB1 1

  696. #define PINB2 2

  697. #define PINB3 3

  698. #define PINB4 4

  699. #define PINB5 5

  700. #define PINB6 6

  701. #define PINB7 7

  702. #define DDB0 0

  703. #define DDB1 1

  704. #define DDB2 2

  705. #define DDB3 3

  706. #define DDB4 4

  707. #define DDB5 5

  708. #define DDB6 6

  709. #define DDB7 7

  710. #define PORTB0 0

  711. #define PORTB1 1

  712. #define PORTB2 2

  713. #define PORTB3 3

  714. #define PORTB4 4

  715. #define PORTB5 5

  716. #define PORTB6 6

  717. #define PORTB7 7

  718. #define PINC0 0

  719. #define PINC1 1

  720. #define PINC2 2

  721. #define PINC3 3

  722. #define PINC4 4

  723. #define PINC5 5

  724. #define PINC6 6

  725. #define DDC0 0

  726. #define DDC1 1

  727. #define DDC2 2

  728. #define DDC3 3

  729. #define DDC4 4

  730. #define DDC5 5

  731. #define DDC6 6

  732. #define PORTC0 0

  733. #define PORTC1 1

  734. #define PORTC2 2

  735. #define PORTC3 3

  736. #define PORTC4 4

  737. #define PORTC5 5

  738. #define PORTC6 6

  739. #define PIND0 0

  740. #define PIND1 1

  741. #define PIND2 2

  742. #define PIND3 3

  743. #define PIND4 4

  744. #define PIND5 5

  745. #define PIND6 6

  746. #define PIND7 7

  747. #define DDD0 0

  748. #define DDD1 1

  749. #define DDD2 2

  750. #define DDD3 3

  751. #define DDD4 4

  752. #define DDD5 5

  753. #define DDD6 6

  754. #define DDD7 7

  755. #define PORTD0 0

  756. #define PORTD1 1

  757. #define PORTD2 2

  758. #define PORTD3 3

  759. #define PORTD4 4

  760. #define PORTD5 5

  761. #define PORTD6 6

  762. #define PORTD7 7

  763. 

  764. 

  765. 

  766. 

  767. 

  768. #if 0

  769. extern "C" {

  770. void serial_print(const char *p);

  771. void serial_phex(uint32_t n);

  772. void serial_phex16(uint32_t n);

  773. void serial_phex32(uint32_t n);

  774. }

  775. #endif

  776. 

  777. 

  778. // SPI Control Register ­ SPCR

  779. #define SPIE	7	// SPI Interrupt Enable - not supported

  780. #define SPE	6	// SPI Enable

  781. #define DORD	5	// DORD: Data Order

  782. #define MSTR	4	// MSTR: Master/Slave Select

  783. #define CPOL	3	// CPOL: Clock Polarity

  784. #define CPHA	2	// CPHA: Clock Phase

  785. #define SPR1	1	// Clock: 3 = 125 kHz, 2 = 250 kHz, 1 = 1 MHz, 0->4 MHz

  786. #define SPR0	0

  787. // SPI Status Register ­ SPSR

  788. #define SPIF	7	// SPIF: SPI Interrupt Flag

  789. #define WCOL	6	// WCOL: Write COLlision Flag - not implemented

  790. #define SPI2X	0	// SPI2X: Double SPI Speed Bit

  791. // SPI Data Register ­ SPDR

  792. 

  793. class SPCRemulation;

  794. class SPSRemulation;

  795. class SPDRemulation;

  796. 

  797. class SPCRemulation

  798. {

  799. public:

  800. 	inline SPCRemulation & operator = (int val) __attribute__((always_inline)) {

  801. 		uint32_t ctar, mcr, sim6;

  802. 		//serial_print("SPCR=");

  803. 		//serial_phex(val);

  804. 		//serial_print("\n");

  805. 		sim6 = SIM_SCGC6;

  806. 		if (!(sim6 & SIM_SCGC6_SPI0)) {

  807. 			//serial_print("init1\n");

  808. 			SIM_SCGC6 = sim6 | SIM_SCGC6_SPI0;

  809. 			SPI0_CTAR0 = SPI_CTAR_FMSZ(7) | SPI_CTAR_PBR(1) | SPI_CTAR_BR(1) | SPI_CTAR_CSSCK(1);

  810. 		}

  811. 		if (!(val & (1<<SPE))) {

  812. 			SPI0_MCR |= SPI_MCR_MDIS; // TODO: use bitband for atomic access

  813. 		}

  814. 		ctar = SPI_CTAR_FMSZ(7) | SPI_CTAR_PBR(1);

  815. 		if (val & (1<<DORD))  ctar |= SPI_CTAR_LSBFE;

  816. 		if (val & (1<<CPOL))  ctar |= SPI_CTAR_CPOL;

  817. 		if (val & (1<<CPHA)) {

  818. 			ctar |= SPI_CTAR_CPHA;

  819. 			if ((val & 3) == 0) {

  820. 				ctar |= SPI_CTAR_BR(1) | SPI_CTAR_ASC(1);

  821. 			} else if ((val & 3) == 1) {

  822. 				ctar |= SPI_CTAR_BR(4) | SPI_CTAR_ASC(4);

  823. 			} else if ((val & 3) == 2) {

  824. 				ctar |= SPI_CTAR_BR(6) | SPI_CTAR_ASC(6);

  825. 			} else {

  826. 				ctar |= SPI_CTAR_BR(7) | SPI_CTAR_ASC(7);

  827. 			}

  828. 		} else {

  829. 			if ((val & 3) == 0) {

  830. 				ctar |= SPI_CTAR_BR(1) | SPI_CTAR_CSSCK(1);

  831. 			} else if ((val & 3) == 1) {

  832. 				ctar |= SPI_CTAR_BR(4) | SPI_CTAR_CSSCK(4);

  833. 			} else if ((val & 3) == 2) {

  834. 				ctar |= SPI_CTAR_BR(6) | SPI_CTAR_CSSCK(6);

  835. 			} else {

  836. 				ctar |= SPI_CTAR_BR(7) | SPI_CTAR_CSSCK(7);

  837. 			}

  838. 		}

  839. 		ctar |= (SPI0_CTAR0 & SPI_CTAR_DBR);

  840. 		update_ctar(ctar);

  841. 		mcr = SPI_MCR_DCONF(0) | SPI_MCR_PCSIS(0x1F);

  842. 		if (val & (1<<MSTR)) mcr |= SPI_MCR_MSTR;

  843. 		if (val & (1<<SPE)) {

  844. 			mcr &= ~(SPI_MCR_MDIS | SPI_MCR_HALT);

  845. 			SPI0_MCR = mcr;

  846. 			enable_pins();

  847. 		} else {

  848. 			mcr |= (SPI_MCR_MDIS | SPI_MCR_HALT);

  849. 			SPI0_MCR = mcr;

  850. 			disable_pins();

  851. 		}

  852. 		//serial_print("MCR:");

  853. 		//serial_phex32(SPI0_MCR);

  854. 		//serial_print(", CTAR0:");

  855. 		//serial_phex32(SPI0_CTAR0);

  856. 		//serial_print("\n");

  857. 		return *this;

  858. 	}

  859. 	inline SPCRemulation & operator |= (int val) __attribute__((always_inline)) {

  860. 		uint32_t sim6;

  861. 		//serial_print("SPCR |= ");

  862. 		//serial_phex(val);

  863. 		//serial_print("\n");

  864. 		sim6 = SIM_SCGC6;

  865. 		if (!(sim6 & SIM_SCGC6_SPI0)) {

  866. 			//serial_print("init2\n");

  867. 			SIM_SCGC6 = sim6 | SIM_SCGC6_SPI0;

  868. 			SPI0_CTAR0 = SPI_CTAR_FMSZ(7) | SPI_CTAR_PBR(1) | SPI_CTAR_BR(1);

  869. 		}

  870. 		if (val & ((1<<DORD)|(1<<CPOL)|(1<<CPHA)|3)) {

  871. 			uint32_t ctar = SPI0_CTAR0;

  872. 			if (val & (1<<DORD)) ctar |= SPI_CTAR_LSBFE; // TODO: use bitband

  873. 			if (val & (1<<CPOL)) ctar |= SPI_CTAR_CPOL;

  874. 			if ((val & 3) == 1) {

  875. 				// TODO: implement - is this ever really needed

  876. 			} else if ((val & 3) == 2) {

  877. 				// TODO: implement - is this ever really needed

  878. 			} else if ((val & 3) == 3) {

  879. 				// TODO: implement - is this ever really needed

  880. 			}

  881. 			if (val & (1<<CPHA) && !(ctar & SPI_CTAR_CPHA)) {

  882. 				ctar |= SPI_CTAR_CPHA;

  883. 				// TODO: clear SPI_CTAR_CSSCK, set SPI_CTAR_ASC

  884. 			}

  885. 			update_ctar(ctar);

  886. 		}

  887. 		if (val & (1<<MSTR)) SPI0_MCR |= SPI_MCR_MSTR;

  888. 		if (val & (1<<SPE)) {

  889. 			SPI0_MCR &= ~(SPI_MCR_MDIS | SPI_MCR_HALT);

  890. 			enable_pins();

  891. 		}

  892. 		//serial_print("MCR:");

  893. 		//serial_phex32(SPI0_MCR);

  894. 		//serial_print(", CTAR0:");

  895. 		//serial_phex32(SPI0_CTAR0);

  896. 		//serial_print("\n");

  897. 		return *this;

  898. 	}

  899. 	inline SPCRemulation & operator &= (int val) __attribute__((always_inline)) {

  900. 		//serial_print("SPCR &= ");

  901. 		//serial_phex(val);

  902. 		//serial_print("\n");

  903. 		SIM_SCGC6 |= SIM_SCGC6_SPI0;

  904. 		if (!(val & (1<<SPE))) {

  905. 			SPI0_MCR |= (SPI_MCR_MDIS | SPI_MCR_HALT);

  906. 			disable_pins();

  907. 		}

  908. 		if ((val & ((1<<DORD)|(1<<CPOL)|(1<<CPHA)|3)) != ((1<<DORD)|(1<<CPOL)|(1<<CPHA)|3)) {

  909. 			uint32_t ctar = SPI0_CTAR0;

  910. 			if (!(val & (1<<DORD))) ctar &= ~SPI_CTAR_LSBFE; // TODO: use bitband

  911. 			if (!(val & (1<<CPOL))) ctar &= ~SPI_CTAR_CPOL;

  912. 			if ((val & 3) == 0) {

  913. 				// TODO: implement - is this ever really needed

  914. 			} else if ((val & 3) == 1) {

  915. 				// TODO: implement - is this ever really needed

  916. 			} else if ((val & 3) == 2) {

  917. 				// TODO: implement - is this ever really needed

  918. 			}

  919. 			if (!(val & (1<<CPHA)) && (ctar & SPI_CTAR_CPHA)) {

  920. 				ctar &= ~SPI_CTAR_CPHA;

  921. 				// TODO: set SPI_CTAR_ASC, clear SPI_CTAR_CSSCK

  922. 			}

  923. 			update_ctar(ctar);

  924. 		}

  925. 		if (!(val & (1<<MSTR))) SPI0_MCR &= ~SPI_MCR_MSTR;

  926. 		return *this;

  927. 	}

  928. 	inline int operator & (int val) const __attribute__((always_inline)) {

  929. 		int ret = 0;

  930. 		//serial_print("SPCR & ");

  931. 		//serial_phex(val);

  932. 		//serial_print("\n");

  933. 		if ((val & (1<<DORD)) && (SPI0_CTAR0 & SPI_CTAR_LSBFE)) ret |= (1<<DORD);

  934. 		if ((val & (1<<CPOL)) && (SPI0_CTAR0 & SPI_CTAR_CPOL)) ret |= (1<<CPOL);

  935. 		if ((val & (1<<CPHA)) && (SPI0_CTAR0 & SPI_CTAR_CPHA)) ret |= (1<<CPHA);

  936. 		if ((val & 3) == 3) {

  937. 			uint32_t dbr = SPI0_CTAR0 & 15;

  938. 			if (dbr <= 1) {

  939. 			} else if (dbr <= 4) {

  940. 				ret |= (1<<SPR0);

  941. 			} else if (dbr <= 6) {

  942. 				ret |= (1<<SPR1);

  943. 			} else {

  944. 				ret |= (1<<SPR1)|(1<<SPR0);

  945. 			}

  946. 		} else if ((val & 3) == 1) {

  947. 			// TODO: implement - is this ever really needed

  948. 		} else if ((val & 3) == 2) {

  949. 			// TODO: implement - is this ever really needed

  950. 		}

  951. 		if (val & (1<<SPE) && (!(SPI0_MCR & SPI_MCR_MDIS))) ret |= (1<<SPE);

  952. 		if (val & (1<<MSTR) && (SPI0_MCR & SPI_MCR_MSTR)) ret |= (1<<MSTR);

  953. 		//serial_print("ret = ");

  954. 		//serial_phex(ret);

  955. 		//serial_print("\n");

  956. 		return ret;

  957. 	}

  958. 	operator int () const __attribute__((always_inline)) {

  959. 		int ret = 0;

  960. 		if ((SIM_SCGC6 & SIM_SCGC6_SPI0)) {

  961. 			int ctar = SPI0_CTAR0;

  962. 			if (ctar & SPI_CTAR_LSBFE) ret |= (1<<DORD);

  963. 			if (ctar & SPI_CTAR_CPOL) ret |= (1<<CPOL);

  964. 			if (ctar & SPI_CTAR_CPHA) ret |= (1<<CPHA);

  965. 			ctar &= 15;

  966. 			if (ctar <= 1) {

  967. 			} else if (ctar <= 4) {

  968. 				ret |= (1<<SPR0);

  969. 			} else if (ctar <= 6) {

  970. 				ret |= (1<<SPR1);

  971. 			} else {

  972. 				ret |= (1<<SPR1)|(1<<SPR0);

  973. 			}

  974. 			int mcr = SPI0_MCR;

  975. 			if (!(mcr & SPI_MCR_MDIS)) ret |= (1<<SPE);

  976. 			if (mcr & SPI_MCR_MSTR) ret |= (1<<MSTR);

  977. 		}

  978. 		return ret;

  979. 	}

  980. 	inline void setMOSI(uint8_t pin) __attribute__((always_inline)) {

  981. 		if (pin == 11) pinout &= ~1;

  982. 		if (pin == 7) pinout |= 1;

  983. 	}

  984. 	inline void setMISO(uint8_t pin) __attribute__((always_inline)) {

  985. 		if (pin == 12) pinout &= ~2;

  986. 		if (pin == 8) pinout |= 2;

  987. 	}

  988. 	inline void setSCK(uint8_t pin) __attribute__((always_inline)) {

  989. 		if (pin == 13) pinout &= ~4;

  990. 		if (pin == 14) pinout |= 4;

  991. 	}

  992. 	friend class SPSRemulation;

  993. 	friend class SPIFIFOclass;

  994. private:

  995. 	static inline void update_ctar(uint32_t ctar) __attribute__((always_inline)) {

  996. 		if (SPI0_CTAR0 == ctar) return;

  997. 		uint32_t mcr = SPI0_MCR;

  998. 		if (mcr & SPI_MCR_MDIS) {

  999. 			SPI0_CTAR0 = ctar;

  1000. 		} else {

  1001. 			SPI0_MCR = mcr | SPI_MCR_MDIS | SPI_MCR_HALT;

  1002. 			SPI0_CTAR0 = ctar;

  1003. 			SPI0_MCR = mcr;

  1004. 		}

  1005. 	}

  1006. 	static uint8_t pinout;

  1007. public:

  1008. 	inline void enable_pins(void) __attribute__((always_inline)) {

  1009. 		//serial_print("enable_pins\n");

  1010. 		if ((pinout & 1) == 0) {

  1011. 			CORE_PIN11_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(2); // DOUT/MOSI = 11 (PTC6)

  1012. 		} else {

  1013. 			CORE_PIN7_CONFIG = PORT_PCR_MUX(2); // DOUT/MOSI = 7 (PTD2)

  1014. 		}

  1015. 		if ((pinout & 2) == 0) {

  1016. 			CORE_PIN12_CONFIG = PORT_PCR_MUX(2);  // DIN/MISO = 12 (PTC7)

  1017. 		} else {

  1018. 			CORE_PIN8_CONFIG = PORT_PCR_MUX(2);  // DIN/MISO = 8 (PTD3)

  1019. 		}

  1020. 		if ((pinout & 4) == 0) {

  1021. 			CORE_PIN13_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(2); // SCK = 13 (PTC5)

  1022. 		} else {

  1023. 			CORE_PIN14_CONFIG = PORT_PCR_MUX(2); // SCK = 14 (PTD1)

  1024. 		}

  1025. 	}

  1026. 	inline void disable_pins(void) __attribute__((always_inline)) {

  1027. 		//serial_print("disable_pins\n");

  1028. 		CORE_PIN11_CONFIG = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);

  1029. 		CORE_PIN12_CONFIG = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);

  1030. 		CORE_PIN13_CONFIG = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);

  1031. 	}

  1032. };

  1033. extern SPCRemulation SPCR;

  1034. 

  1035. class SPSRemulation

  1036. {

  1037. public:

  1038. 	inline SPSRemulation & operator = (int val) __attribute__((always_inline)) {

  1039. 		//serial_print("SPSR=");

  1040. 		//serial_phex(val);

  1041. 		//serial_print("\n");

  1042. 		uint32_t ctar = SPI0_CTAR0;

  1043. 		if (val & (1<<SPI2X)) {

  1044. 			ctar |= SPI_CTAR_DBR;

  1045. 		} else {

  1046. 			ctar &= ~SPI_CTAR_DBR;

  1047. 		}

  1048. 		SPCRemulation::update_ctar(ctar);

  1049. 		//serial_print("MCR:");

  1050. 		//serial_phex32(SPI0_MCR);

  1051. 		//serial_print(", CTAR0:");

  1052. 		//serial_phex32(SPI0_CTAR0);

  1053. 		//serial_print("\n");

  1054. 		return *this;

  1055. 	}

  1056. 	inline SPSRemulation & operator |= (int val) __attribute__((always_inline)) {

  1057. 		//serial_print("SPSR |= ");

  1058. 		//serial_phex(val);

  1059. 		//serial_print("\n");

  1060. 		if (val & (1<<SPI2X)) SPCRemulation::update_ctar(SPI0_CTAR0 |= SPI_CTAR_DBR);

  1061. 		return *this;

  1062. 	}

  1063. 	inline SPSRemulation & operator &= (int val) __attribute__((always_inline)) {

  1064. 		//serial_print("SPSR &= ");

  1065. 		//serial_phex(val);

  1066. 		//serial_print("\n");

  1067. 		if (!(val & (1<<SPI2X))) SPCRemulation::update_ctar(SPI0_CTAR0 &= ~SPI_CTAR_DBR);

  1068. 		return *this;

  1069. 	}

  1070. 	inline int operator & (int val) const __attribute__((always_inline)) {

  1071. 		int ret = 0;

  1072. 		//serial_print("SPSR & ");

  1073. 		//serial_phex(val);

  1074. 		//serial_print("\n");

  1075. 		// TODO: using SPI_SR_TCF isn't quite right.  Control returns to the

  1076. 		// caller after the final edge that captures data, which is 1/2 cycle

  1077. 		// sooner than AVR returns.  At 500 kHz and slower SPI, this can make

  1078. 		// a difference when digitalWrite is used to manually control the CS

  1079. 		// pin, and perhaps it could matter at high clocks if faster register

  1080. 		// access is used?  But does it really matter?  Do any SPI chips in

  1081. 		// practice really perform differently if CS negates early, after the

  1082. 		// final bit is clocked, but before the end of the whole clock cycle?

  1083. 		if ((val & (1<<SPIF)) && (SPI0_SR & SPI_SR_TCF)) ret = (1<<SPIF);

  1084. 		if ((val & (1<<SPI2X)) && (SPI0_CTAR0 & SPI_CTAR_DBR)) ret |= (1<<SPI2X);

  1085. 		//delayMicroseconds(50000);

  1086. 		return ret;

  1087. 	}

  1088. 	operator int () const __attribute__((always_inline)) {

  1089. 		int ret = 0;

  1090. 		//serial_print("SPSR (int)\n");

  1091. 		if (SPI0_SR & SPI_SR_TCF) ret = (1<<SPIF);

  1092. 		if (SPI0_CTAR0 & SPI_CTAR_DBR) ret |= (1<<SPI2X);

  1093. 		return ret;

  1094. 	}

  1095. };

  1096. extern SPSRemulation SPSR;

  1097. 

  1098. class SPDRemulation

  1099. {

  1100. public:

  1101. 	inline SPDRemulation & operator = (int val) __attribute__((always_inline)) {

  1102. 		//serial_print("SPDR = ");

  1103. 		//serial_phex(val);

  1104. 		//serial_print("\n");

  1105. 		SPI0_MCR |= SPI_MCR_CLR_RXF; // discard any received data

  1106. 		SPI0_SR = SPI_SR_TCF;

  1107. 		//SPI0_SR = SPI_SR_EOQF;

  1108. 		//SPI0_PUSHR = (val & 255) | SPI0_PUSHR_EOQ;

  1109. 		SPI0_PUSHR = (val & 255);

  1110. 		return *this;

  1111. 	}

  1112. 	operator int () const __attribute__((always_inline)) {

  1113. 		uint32_t val;

  1114. 		val = SPI0_POPR & 255;

  1115. 		//serial_print("SPDR (int) ");

  1116. 		//serial_phex(val);

  1117. 		//serial_print("\n");

  1118. 		return val;

  1119. 	}

  1120. };

  1121. extern SPDRemulation SPDR;

  1122. 

  1123. 

  1124. class SREGemulation

  1125. {

  1126. public:

  1127. 	operator int () const __attribute__((always_inline)) {

  1128. 		uint32_t primask;

  1129. 		asm volatile("mrs %0, primask\n" : "=r" (primask)::);

  1130. 		if (primask) return 0;

  1131. 		return (1<<7);

  1132. 	}

  1133. 	inline SREGemulation & operator = (int val) __attribute__((always_inline)) {

  1134. 		if (val & (1<<7)) {

  1135. 			__enable_irq();

  1136. 		} else {

  1137. 			__disable_irq();

  1138. 		}

  1139. 		return *this;

  1140. 	}

  1141. };

  1142. extern SREGemulation SREG;

  1143. 

  1144. 

  1145. extern uint8_t EIMSK;

  1146. 

  1147. // these are not intended for public consumption...

  1148. #undef GPIO_BITBAND_ADDR

  1149. #undef GPIO_BITBAND

  1150. #undef CONFIG_PULLUP

  1151. #undef CONFIG_NOPULLUP

  1152. 

  1153. #endif // __cplusplus

  1154. 

  1155. #endif