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Teensy 4.1 core updated for C++20
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teensy-core-4.1/teensy3/mk20dx128.c

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  1. /* Teensyduino Core Library

  2.  * http://www.pjrc.com/teensy/

  3.  * Copyright (c) 2013 PJRC.COM, LLC.

  4.  *

  5.  * Permission is hereby granted, free of charge, to any person obtaining

  6.  * a copy of this software and associated documentation files (the

  7.  * "Software"), to deal in the Software without restriction, including

  8.  * without limitation the rights to use, copy, modify, merge, publish,

  9.  * distribute, sublicense, and/or sell copies of the Software, and to

  10.  * permit persons to whom the Software is furnished to do so, subject to

  11.  * the following conditions:

  12.  *

  13.  * 1. The above copyright notice and this permission notice shall be 

  14.  * included in all copies or substantial portions of the Software.

  15.  *

  16.  * 2. If the Software is incorporated into a build system that allows 

  17.  * selection among a list of target devices, then similar target

  18.  * devices manufactured by PJRC.COM must be included in the list of

  19.  * target devices and selectable in the same manner.

  20.  *

  21.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

  22.  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

  23.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

  24.  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS

  25.  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN

  26.  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

  27.  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

  28.  * SOFTWARE.

  29.  */

  30. 

  31. #include "mk20dx128.h"

  32. 

  33. 

  34. extern unsigned long _stext;

  35. extern unsigned long _etext;

  36. extern unsigned long _sdata;

  37. extern unsigned long _edata;

  38. extern unsigned long _sbss;

  39. extern unsigned long _ebss;

  40. extern unsigned long _estack;

  41. //extern void __init_array_start(void);

  42. //extern void __init_array_end(void);

  43. 

  44. 

  45. 

  46. extern int main (void);

  47. void ResetHandler(void);

  48. void _init_Teensyduino_internal_(void);

  49. void __libc_init_array(void);

  50. 

  51. 

  52. void fault_isr(void)

  53. {

  54. 	while (1) {

  55. 		// keep polling some communication while in fault

  56. 		// mode, so we don't completely die.

  57. 		if (SIM_SCGC4 & SIM_SCGC4_USBOTG) usb_isr();

  58. 		if (SIM_SCGC4 & SIM_SCGC4_UART0) uart0_status_isr();

  59. 		if (SIM_SCGC4 & SIM_SCGC4_UART1) uart1_status_isr();

  60. 		if (SIM_SCGC4 & SIM_SCGC4_UART2) uart2_status_isr();

  61. 	}

  62. }

  63. 

  64. void unused_isr(void)

  65. {

  66. 	fault_isr();

  67. }

  68. 

  69. extern volatile uint32_t systick_millis_count;

  70. void systick_default_isr(void)

  71. {

  72. 	systick_millis_count++;

  73. }

  74. 

  75. void nmi_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  76. void hard_fault_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  77. void memmanage_fault_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  78. void bus_fault_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  79. void usage_fault_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  80. void svcall_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  81. void debugmonitor_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  82. void pendablesrvreq_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  83. void systick_isr(void)		__attribute__ ((weak, alias("systick_default_isr")));

  84. 

  85. void dma_ch0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  86. void dma_ch1_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  87. void dma_ch2_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  88. void dma_ch3_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  89. void dma_ch4_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  90. void dma_ch5_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  91. void dma_ch6_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  92. void dma_ch7_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  93. void dma_ch8_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  94. void dma_ch9_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  95. void dma_ch10_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  96. void dma_ch11_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  97. void dma_ch12_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  98. void dma_ch13_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  99. void dma_ch14_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  100. void dma_ch15_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  101. void dma_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  102. void mcm_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  103. void flash_cmd_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  104. void flash_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  105. void low_voltage_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  106. void wakeup_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  107. void watchdog_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  108. void i2c0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  109. void i2c1_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  110. void i2c2_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  111. void spi0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  112. void spi1_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  113. void spi2_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  114. void sdhc_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  115. void can0_message_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  116. void can0_bus_off_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  117. void can0_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  118. void can0_tx_warn_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  119. void can0_rx_warn_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  120. void can0_wakeup_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  121. void i2s0_tx_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  122. void i2s0_rx_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  123. void uart0_lon_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  124. void uart0_status_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  125. void uart0_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  126. void uart1_status_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  127. void uart1_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  128. void uart2_status_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  129. void uart2_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  130. void uart3_status_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  131. void uart3_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  132. void uart4_status_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  133. void uart4_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  134. void uart5_status_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  135. void uart5_error_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  136. void adc0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  137. void adc1_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  138. void cmp0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  139. void cmp1_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  140. void cmp2_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  141. void ftm0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  142. void ftm1_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  143. void ftm2_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  144. void ftm3_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  145. void cmt_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  146. void rtc_alarm_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  147. void rtc_seconds_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  148. void pit0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  149. void pit1_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  150. void pit2_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  151. void pit3_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  152. void pdb_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  153. void usb_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  154. void usb_charge_isr(void)	__attribute__ ((weak, alias("unused_isr")));

  155. void dac0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  156. void dac1_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  157. void tsi0_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  158. void mcg_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  159. void lptmr_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  160. void porta_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  161. void portb_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  162. void portc_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  163. void portd_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  164. void porte_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  165. void software_isr(void)		__attribute__ ((weak, alias("unused_isr")));

  166. 

  167. 

  168. // TODO: create AVR-stype ISR() macro, with default linkage to undefined handler

  169. //

  170. __attribute__ ((section(".vectors"), used))

  171. void (* const gVectors[])(void) =

  172. {

  173. 	(void (*)(void))((unsigned long)&_estack),	//  0 ARM: Initial Stack Pointer

  174. 	ResetHandler,					//  1 ARM: Initial Program Counter

  175. 	nmi_isr,					//  2 ARM: Non-maskable Interrupt (NMI)

  176. 	hard_fault_isr,					//  3 ARM: Hard Fault

  177. 	memmanage_fault_isr,				//  4 ARM: MemManage Fault

  178. 	bus_fault_isr,					//  5 ARM: Bus Fault

  179. 	usage_fault_isr,				//  6 ARM: Usage Fault

  180. 	fault_isr,					//  7 --

  181. 	fault_isr,					//  8 --

  182. 	fault_isr,					//  9 --

  183. 	fault_isr,					// 10 --

  184. 	svcall_isr,					// 11 ARM: Supervisor call (SVCall)

  185. 	debugmonitor_isr,				// 12 ARM: Debug Monitor

  186. 	fault_isr,					// 13 --

  187. 	pendablesrvreq_isr,				// 14 ARM: Pendable req serv(PendableSrvReq)

  188. 	systick_isr,					// 15 ARM: System tick timer (SysTick)

  189. #if defined(__MK20DX128__)

  190. 	dma_ch0_isr,					// 16 DMA channel 0 transfer complete

  191. 	dma_ch1_isr,					// 17 DMA channel 1 transfer complete

  192. 	dma_ch2_isr,					// 18 DMA channel 2 transfer complete

  193. 	dma_ch3_isr,					// 19 DMA channel 3 transfer complete

  194. 	dma_error_isr,					// 20 DMA error interrupt channel

  195. 	unused_isr,					// 21 DMA --

  196. 	flash_cmd_isr,					// 22 Flash Memory Command complete

  197. 	flash_error_isr,				// 23 Flash Read collision

  198. 	low_voltage_isr,				// 24 Low-voltage detect/warning

  199. 	wakeup_isr,					// 25 Low Leakage Wakeup

  200. 	watchdog_isr,					// 26 Both EWM and WDOG interrupt

  201. 	i2c0_isr,					// 27 I2C0

  202. 	spi0_isr,					// 28 SPI0

  203. 	i2s0_tx_isr,					// 29 I2S0 Transmit

  204. 	i2s0_rx_isr,					// 30 I2S0 Receive

  205. 	uart0_lon_isr,					// 31 UART0 CEA709.1-B (LON) status

  206. 	uart0_status_isr,				// 32 UART0 status

  207. 	uart0_error_isr,				// 33 UART0 error

  208. 	uart1_status_isr,				// 34 UART1 status

  209. 	uart1_error_isr,				// 35 UART1 error

  210. 	uart2_status_isr,				// 36 UART2 status

  211. 	uart2_error_isr,				// 37 UART2 error

  212. 	adc0_isr,					// 38 ADC0

  213. 	cmp0_isr,					// 39 CMP0

  214. 	cmp1_isr,					// 40 CMP1

  215. 	ftm0_isr,					// 41 FTM0

  216. 	ftm1_isr,					// 42 FTM1

  217. 	cmt_isr,					// 43 CMT

  218. 	rtc_alarm_isr,					// 44 RTC Alarm interrupt

  219. 	rtc_seconds_isr,				// 45 RTC Seconds interrupt

  220. 	pit0_isr,					// 46 PIT Channel 0

  221. 	pit1_isr,					// 47 PIT Channel 1

  222. 	pit2_isr,					// 48 PIT Channel 2

  223. 	pit3_isr,					// 49 PIT Channel 3

  224. 	pdb_isr,					// 50 PDB Programmable Delay Block

  225. 	usb_isr,					// 51 USB OTG

  226. 	usb_charge_isr,					// 52 USB Charger Detect

  227. 	tsi0_isr,					// 53 TSI0

  228. 	mcg_isr,					// 54 MCG

  229. 	lptmr_isr,					// 55 Low Power Timer

  230. 	porta_isr,					// 56 Pin detect (Port A)

  231. 	portb_isr,					// 57 Pin detect (Port B)

  232. 	portc_isr,					// 58 Pin detect (Port C)

  233. 	portd_isr,					// 59 Pin detect (Port D)

  234. 	porte_isr,					// 60 Pin detect (Port E)

  235. 	software_isr,					// 61 Software interrupt

  236. #elif defined(__MK20DX256__)

  237. 	dma_ch0_isr,					// 16 DMA channel 0 transfer complete

  238. 	dma_ch1_isr,					// 17 DMA channel 1 transfer complete

  239. 	dma_ch2_isr,					// 18 DMA channel 2 transfer complete

  240. 	dma_ch3_isr,					// 19 DMA channel 3 transfer complete

  241. 	dma_ch4_isr,					// 20 DMA channel 4 transfer complete

  242. 	dma_ch5_isr,					// 21 DMA channel 5 transfer complete

  243. 	dma_ch6_isr,					// 22 DMA channel 6 transfer complete

  244. 	dma_ch7_isr,					// 23 DMA channel 7 transfer complete

  245. 	dma_ch8_isr,					// 24 DMA channel 8 transfer complete

  246. 	dma_ch9_isr,					// 25 DMA channel 9 transfer complete

  247. 	dma_ch10_isr,					// 26 DMA channel 10 transfer complete

  248. 	dma_ch11_isr,					// 27 DMA channel 10 transfer complete

  249. 	dma_ch12_isr,					// 28 DMA channel 10 transfer complete

  250. 	dma_ch13_isr,					// 29 DMA channel 10 transfer complete

  251. 	dma_ch14_isr,					// 30 DMA channel 10 transfer complete

  252. 	dma_ch15_isr,					// 31 DMA channel 10 transfer complete

  253. 	dma_error_isr,					// 32 DMA error interrupt channel

  254. 	unused_isr,					// 33 --

  255. 	flash_cmd_isr,					// 34 Flash Memory Command complete

  256. 	flash_error_isr,				// 35 Flash Read collision

  257. 	low_voltage_isr,				// 36 Low-voltage detect/warning

  258. 	wakeup_isr,					// 37 Low Leakage Wakeup

  259. 	watchdog_isr,					// 38 Both EWM and WDOG interrupt

  260. 	unused_isr,					// 39 --

  261. 	i2c0_isr,					// 40 I2C0

  262. 	i2c1_isr,					// 41 I2C1

  263. 	spi0_isr,					// 42 SPI0

  264. 	spi1_isr,					// 43 SPI1

  265. 	unused_isr,					// 44 --

  266. 	can0_message_isr,				// 45 CAN OR'ed Message buffer (0-15)

  267. 	can0_bus_off_isr,				// 46 CAN Bus Off

  268. 	can0_error_isr,					// 47 CAN Error

  269. 	can0_tx_warn_isr,				// 48 CAN Transmit Warning

  270. 	can0_rx_warn_isr,				// 49 CAN Receive Warning

  271. 	can0_wakeup_isr,				// 50 CAN Wake Up

  272. 	i2s0_tx_isr,					// 51 I2S0 Transmit

  273. 	i2s0_rx_isr,					// 52 I2S0 Receive

  274. 	unused_isr,					// 53 --

  275. 	unused_isr,					// 54 --

  276. 	unused_isr,					// 55 --

  277. 	unused_isr,					// 56 --

  278. 	unused_isr,					// 57 --

  279. 	unused_isr,					// 58 --

  280. 	unused_isr,					// 59 --

  281. 	uart0_lon_isr,					// 60 UART0 CEA709.1-B (LON) status

  282. 	uart0_status_isr,				// 61 UART0 status

  283. 	uart0_error_isr,				// 62 UART0 error

  284. 	uart1_status_isr,				// 63 UART1 status

  285. 	uart1_error_isr,				// 64 UART1 error

  286. 	uart2_status_isr,				// 65 UART2 status

  287. 	uart2_error_isr,				// 66 UART2 error

  288. 	unused_isr,					// 67 --

  289. 	unused_isr,					// 68 --

  290. 	unused_isr,					// 69 --

  291. 	unused_isr,					// 70 --

  292. 	unused_isr,					// 71 --

  293. 	unused_isr,					// 72 --

  294. 	adc0_isr,					// 73 ADC0

  295. 	adc1_isr,					// 74 ADC1

  296. 	cmp0_isr,					// 75 CMP0

  297. 	cmp1_isr,					// 76 CMP1

  298. 	cmp2_isr,					// 77 CMP2

  299. 	ftm0_isr,					// 78 FTM0

  300. 	ftm1_isr,					// 79 FTM1

  301. 	ftm2_isr,					// 80 FTM2

  302. 	cmt_isr,					// 81 CMT

  303. 	rtc_alarm_isr,					// 82 RTC Alarm interrupt

  304. 	rtc_seconds_isr,				// 83 RTC Seconds interrupt

  305. 	pit0_isr,					// 84 PIT Channel 0

  306. 	pit1_isr,					// 85 PIT Channel 1

  307. 	pit2_isr,					// 86 PIT Channel 2

  308. 	pit3_isr,					// 87 PIT Channel 3

  309. 	pdb_isr,					// 88 PDB Programmable Delay Block

  310. 	usb_isr,					// 89 USB OTG

  311. 	usb_charge_isr,					// 90 USB Charger Detect

  312. 	unused_isr,					// 91 --

  313. 	unused_isr,					// 92 --

  314. 	unused_isr,					// 93 --

  315. 	unused_isr,					// 94 --

  316. 	unused_isr,					// 95 --

  317. 	unused_isr,					// 96 --

  318. 	dac0_isr,					// 97 DAC0

  319. 	unused_isr,					// 98 --

  320. 	tsi0_isr,					// 99 TSI0

  321. 	mcg_isr,					// 100 MCG

  322. 	lptmr_isr,					// 101 Low Power Timer

  323. 	unused_isr,					// 102 --

  324. 	porta_isr,					// 103 Pin detect (Port A)

  325. 	portb_isr,					// 104 Pin detect (Port B)

  326. 	portc_isr,					// 105 Pin detect (Port C)

  327. 	portd_isr,					// 106 Pin detect (Port D)

  328. 	porte_isr,					// 107 Pin detect (Port E)

  329. 	unused_isr,					// 108 --

  330. 	unused_isr,					// 109 --

  331. 	software_isr,					// 110 Software interrupt

  332. #endif

  333. };

  334. 

  335. //void usb_isr(void)

  336. //{

  337. //}

  338. 

  339. __attribute__ ((section(".flashconfig"), used))

  340. const uint8_t flashconfigbytes[16] = {

  341. 	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,

  342. 	0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF

  343. };

  344. 

  345. 

  346. // Automatically initialize the RTC.  When the build defines the compile

  347. // time, and the user has added a crystal, the RTC will automatically

  348. // begin at the time of the first upload.

  349. #ifndef TIME_T

  350. #define TIME_T 1349049600 // default 1 Oct 2012 (never used, Arduino sets this)

  351. #endif

  352. extern void rtc_set(unsigned long t);

  353. 

  354. 

  355. static void startup_default_early_hook(void) { WDOG_STCTRLH = WDOG_STCTRLH_ALLOWUPDATE; }

  356. static void startup_default_late_hook(void) {}

  357. void startup_early_hook(void)		__attribute__ ((weak, alias("startup_default_early_hook")));

  358. void startup_late_hook(void)		__attribute__ ((weak, alias("startup_default_late_hook")));

  359. 

  360. __attribute__ ((section(".startup")))

  361. void ResetHandler(void)

  362. {

  363. 	uint32_t *src = &_etext;

  364. 	uint32_t *dest = &_sdata;

  365. 	unsigned int i;

  366. #if F_CPU <= 2000000

  367. 	volatile int n;

  368. #endif

  369. 

  370. 	WDOG_UNLOCK = WDOG_UNLOCK_SEQ1;

  371. 	WDOG_UNLOCK = WDOG_UNLOCK_SEQ2;

  372. 	__asm__ volatile ("nop");

  373. 	__asm__ volatile ("nop");

  374. 	// programs using the watchdog timer or needing to initialize hardware as

  375. 	// early as possible can implement startup_early_hook()

  376. 	startup_early_hook();

  377. 

  378. 	// enable clocks to always-used peripherals

  379. #if defined(__MK20DX128__)

  380. 	SIM_SCGC5 = 0x00043F82;		// clocks active to all GPIO

  381. 	SIM_SCGC6 = SIM_SCGC6_RTC | SIM_SCGC6_FTM0 | SIM_SCGC6_FTM1 | SIM_SCGC6_ADC0 | SIM_SCGC6_FTFL;

  382. #elif defined(__MK20DX256__)

  383. 	SIM_SCGC3 = SIM_SCGC3_ADC1 | SIM_SCGC3_FTM2;

  384. 	SIM_SCGC5 = 0x00043F82;		// clocks active to all GPIO

  385. 	SIM_SCGC6 = SIM_SCGC6_RTC | SIM_SCGC6_FTM0 | SIM_SCGC6_FTM1 | SIM_SCGC6_ADC0 | SIM_SCGC6_FTFL;

  386. #endif

  387. 	// if the RTC oscillator isn't enabled, get it started early

  388. 	if (!(RTC_CR & RTC_CR_OSCE)) {

  389. 		RTC_SR = 0;

  390. 		RTC_CR = RTC_CR_SC16P | RTC_CR_SC4P | RTC_CR_OSCE;

  391. 	}

  392. 

  393. 	// release I/O pins hold, if we woke up from VLLS mode

  394. 	if (PMC_REGSC & PMC_REGSC_ACKISO) PMC_REGSC |= PMC_REGSC_ACKISO;

  395. 

  396.     // since this is a write once register, make it visible to all F_CPU's

  397.     // so we can into other sleep modes in the future at any speed

  398. 	SMC_PMPROT = SMC_PMPROT_AVLP | SMC_PMPROT_ALLS | SMC_PMPROT_AVLLS;

  399.     

  400. 	// TODO: do this while the PLL is waiting to lock....

  401. 	while (dest < &_edata) *dest++ = *src++;

  402. 	dest = &_sbss;

  403. 	while (dest < &_ebss) *dest++ = 0;

  404. 	SCB_VTOR = 0;	// use vector table in flash

  405. 

  406. 	// default all interrupts to medium priority level

  407. 	for (i=0; i < NVIC_NUM_INTERRUPTS; i++) NVIC_SET_PRIORITY(i, 128);

  408. 

  409. 	// hardware always starts in FEI mode

  410. 	//  C1[CLKS] bits are written to 00

  411. 	//  C1[IREFS] bit is written to 1

  412. 	//  C6[PLLS] bit is written to 0

  413. // MCG_SC[FCDIV] defaults to divide by two for internal ref clock

  414. // I tried changing MSG_SC to divide by 1, it didn't work for me

  415. #if F_CPU <= 2000000

  416. 	// use the internal oscillator

  417. 	MCG_C1 = MCG_C1_CLKS(1) | MCG_C1_IREFS;

  418. 	// wait for MCGOUT to use oscillator

  419. 	while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(1)) ;

  420. 	for (n=0; n<10; n++) ; // TODO: why do we get 2 mA extra without this delay?

  421. 	MCG_C2 = MCG_C2_IRCS;

  422. 	while (!(MCG_S & MCG_S_IRCST)) ;

  423. 	// now in FBI mode:

  424. 	//  C1[CLKS] bits are written to 01

  425. 	//  C1[IREFS] bit is written to 1

  426. 	//  C6[PLLS] is written to 0

  427. 	//  C2[LP] is written to 0

  428. 	MCG_C2 = MCG_C2_IRCS | MCG_C2_LP;

  429. 	// now in BLPI mode:

  430. 	//  C1[CLKS] bits are written to 01

  431. 	//  C1[IREFS] bit is written to 1

  432. 	//  C6[PLLS] bit is written to 0

  433. 	//  C2[LP] bit is written to 1

  434. #else

  435. 	// enable capacitors for crystal

  436. 	OSC0_CR = OSC_SC8P | OSC_SC2P;

  437. 	// enable osc, 8-32 MHz range, low power mode

  438. 	MCG_C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS;

  439. 	// switch to crystal as clock source, FLL input = 16 MHz / 512

  440. 	MCG_C1 =  MCG_C1_CLKS(2) | MCG_C1_FRDIV(4);

  441. 	// wait for crystal oscillator to begin

  442. 	while ((MCG_S & MCG_S_OSCINIT0) == 0) ;

  443. 	// wait for FLL to use oscillator

  444. 	while ((MCG_S & MCG_S_IREFST) != 0) ;

  445. 	// wait for MCGOUT to use oscillator

  446. 	while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2)) ;

  447. 	// now in FBE mode

  448. 	//  C1[CLKS] bits are written to 10

  449. 	//  C1[IREFS] bit is written to 0

  450. 	//  C1[FRDIV] must be written to divide xtal to 31.25-39 kHz

  451. 	//  C6[PLLS] bit is written to 0

  452. 	//  C2[LP] is written to 0

  453.   #if F_CPU <= 16000000

  454. 	// if the crystal is fast enough, use it directly (no FLL or PLL)

  455. 	MCG_C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS | MCG_C2_LP;

  456. 	// BLPE mode:

  457. 	//   C1[CLKS] bits are written to 10

  458. 	//   C1[IREFS] bit is written to 0

  459. 	//   C2[LP] bit is written to 1

  460.   #else

  461. 	// if we need faster than the crystal, turn on the PLL

  462.     #if F_CPU == 72000000

  463. 	MCG_C5 = MCG_C5_PRDIV0(5);		 // config PLL input for 16 MHz Crystal / 6 = 2.667 Hz

  464.     #else

  465. 	MCG_C5 = MCG_C5_PRDIV0(3);		 // config PLL input for 16 MHz Crystal / 4 = 4 MHz

  466.     #endif

  467.     #if F_CPU == 168000000

  468. 	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(18); // config PLL for 168 MHz output

  469.     #elif F_CPU == 144000000

  470. 	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(12); // config PLL for 144 MHz output

  471.     #elif F_CPU == 120000000

  472. 	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(6); // config PLL for 120 MHz output

  473.     #elif F_CPU == 72000000

  474. 	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(3); // config PLL for 72 MHz output

  475.     #else

  476. 	MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0); // config PLL for 96 MHz output

  477.     #endif

  478. 	// wait for PLL to start using xtal as its input

  479. 	while (!(MCG_S & MCG_S_PLLST)) ;

  480. 	// wait for PLL to lock

  481. 	while (!(MCG_S & MCG_S_LOCK0)) ;

  482. 	// now we're in PBE mode

  483.   #endif

  484. #endif

  485. 

  486. 	// now program the clock dividers

  487. #if F_CPU == 168000000

  488. 	// config divisors: 168 MHz core, 56 MHz bus, 33.6 MHz flash, USB = 168 * 2 / 7

  489. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2) |	 SIM_CLKDIV1_OUTDIV4(4);

  490. 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(6) | SIM_CLKDIV2_USBFRAC;

  491. #elif F_CPU == 144000000

  492. 	// config divisors: 144 MHz core, 48 MHz bus, 28.8 MHz flash, USB = 144 / 3

  493. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2) |	 SIM_CLKDIV1_OUTDIV4(4);

  494. 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(2);

  495. #elif F_CPU == 120000000

  496. 	// config divisors: 120 MHz core, 60 MHz bus, 24 MHz flash, USB = 128 * 2 / 5

  497. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) |	 SIM_CLKDIV1_OUTDIV4(4);

  498. 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC;

  499. #elif F_CPU == 96000000

  500. 	// config divisors: 96 MHz core, 48 MHz bus, 24 MHz flash, USB = 96 / 2

  501. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) |	 SIM_CLKDIV1_OUTDIV4(3);

  502. 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1);

  503. #elif F_CPU == 72000000

  504. 	// config divisors: 72 MHz core, 36 MHz bus, 24 MHz flash, USB = 72 * 2 / 3

  505. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) |	 SIM_CLKDIV1_OUTDIV4(2);

  506. 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC;

  507. #elif F_CPU == 48000000

  508. 	// config divisors: 48 MHz core, 48 MHz bus, 24 MHz flash, USB = 96 / 2

  509. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) |	 SIM_CLKDIV1_OUTDIV4(3);

  510. 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1);

  511. #elif F_CPU == 24000000

  512. 	// config divisors: 24 MHz core, 24 MHz bus, 24 MHz flash, USB = 96 / 2

  513. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(3) |	 SIM_CLKDIV1_OUTDIV4(3);

  514. 	SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1);

  515. #elif F_CPU == 16000000

  516. 	// config divisors: 16 MHz core, 16 MHz bus, 16 MHz flash

  517. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |	 SIM_CLKDIV1_OUTDIV4(0);

  518. #elif F_CPU == 8000000

  519. 	// config divisors: 8 MHz core, 8 MHz bus, 8 MHz flash

  520. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) |	 SIM_CLKDIV1_OUTDIV4(1);

  521. #elif F_CPU == 4000000

  522.     // config divisors: 4 MHz core, 4 MHz bus, 2 MHz flash

  523.     // since we are running from external clock 16MHz

  524.     // fix outdiv too -> cpu 16/4, bus 16/4, flash 16/4

  525.     // here we can go into vlpr?

  526. 	// config divisors: 4 MHz core, 4 MHz bus, 4 MHz flash

  527. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(3) |	 SIM_CLKDIV1_OUTDIV4(3);

  528. #elif F_CPU == 2000000

  529.     // since we are running from the fast internal reference clock 4MHz

  530.     // but is divided down by 2 so we actually have a 2MHz, MCG_SC[FCDIV] default is 2

  531.     // fix outdiv -> cpu 2/1, bus 2/1, flash 2/2

  532. 	// config divisors: 2 MHz core, 2 MHz bus, 1 MHz flash

  533. 	SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |	 SIM_CLKDIV1_OUTDIV4(1);

  534. #else

  535. #error "Error, F_CPU must be 168, 144, 120, 96, 72, 48, 24, 16, 8, 4, or 2 MHz"

  536. #endif

  537. 

  538. #if F_CPU > 16000000

  539. 	// switch to PLL as clock source, FLL input = 16 MHz / 512

  540. 	MCG_C1 = MCG_C1_CLKS(0) | MCG_C1_FRDIV(4);

  541. 	// wait for PLL clock to be used

  542. 	while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(3)) ;

  543. 	// now we're in PEE mode

  544. 	// USB uses PLL clock, trace is CPU clock, CLKOUT=OSCERCLK0

  545. 	SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL(6);

  546. #else

  547. 	SIM_SOPT2 = SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL(3);

  548. #endif

  549. 

  550. #if F_CPU <= 2000000

  551.     // since we are not going into "stop mode" i removed it

  552. 	SMC_PMCTRL = SMC_PMCTRL_RUNM(2); // VLPR mode :-)

  553. #endif

  554. 

  555. 	// initialize the SysTick counter

  556. 	SYST_RVR = (F_CPU / 1000) - 1;

  557. 	SYST_CSR = SYST_CSR_CLKSOURCE | SYST_CSR_TICKINT | SYST_CSR_ENABLE;

  558. 

  559. 	//init_pins();

  560. 	__enable_irq();

  561. 

  562. 	_init_Teensyduino_internal_();

  563. 	if (RTC_SR & RTC_SR_TIF) {

  564. 		// TODO: this should probably set the time more agressively, if

  565. 		// we could reliably detect the first reboot after programming.

  566. 		rtc_set(TIME_T);

  567. 	}

  568. 

  569. 	__libc_init_array();

  570. 

  571. 	startup_late_hook();

  572. 	main();

  573. 	while (1) ;

  574. }

  575. 

  576. char *__brkval = (char *)&_ebss;

  577. 

  578. void * _sbrk(int incr)

  579. {

  580. 	char *prev = __brkval;

  581. 	__brkval += incr;

  582. 	return prev;

  583. }

  584. 

  585. __attribute__((weak)) 

  586. int _read(int file, char *ptr, int len)

  587. {

  588. 	return 0;

  589. }

  590. 

  591. __attribute__((weak)) 

  592. int _close(int fd)

  593. {

  594. 	return -1;

  595. }

  596. 

  597. #include <sys/stat.h>

  598. 

  599. __attribute__((weak)) 

  600. int _fstat(int fd, struct stat *st)

  601. {

  602. 	st->st_mode = S_IFCHR;

  603. 	return 0;

  604. }

  605. 

  606. __attribute__((weak)) 

  607. int _isatty(int fd)

  608. {

  609. 	return 1;

  610. }

  611. 

  612. __attribute__((weak)) 

  613. int _lseek(int fd, long long offset, int whence)

  614. {

  615. 	return -1;

  616. }

  617. 

  618. __attribute__((weak)) 

  619. void _exit(int status)

  620. {

  621. 	while (1);

  622. }

  623. 

  624. __attribute__((weak)) 

  625. void __cxa_pure_virtual()

  626. {

  627. 	while (1);

  628. }

  629. 

  630. __attribute__((weak)) 

  631. int __cxa_guard_acquire (char *g) 

  632. {

  633. 	return !(*g);

  634. }

  635. 

  636. __attribute__((weak)) 

  637. void __cxa_guard_release(char *g)

  638. {

  639. 	*g = 1;

  640. }

  641. 

  642. int nvic_execution_priority(void)

  643. {

  644. 	int priority=256;

  645. 	uint32_t primask, faultmask, basepri, ipsr;

  646. 

  647. 	// full algorithm in ARM DDI0403D, page B1-639

  648. 	// this isn't quite complete, but hopefully good enough

  649. 	__asm__ volatile("mrs %0, faultmask\n" : "=r" (faultmask)::);

  650. 	if (faultmask) return -1;

  651. 	__asm__ volatile("mrs %0, primask\n" : "=r" (primask)::);

  652. 	if (primask) return 0;

  653. 	__asm__ volatile("mrs %0, ipsr\n" : "=r" (ipsr)::);

  654. 	if (ipsr) {

  655. 		if (ipsr < 16) priority = 0; // could be non-zero

  656. 		else priority = NVIC_GET_PRIORITY(ipsr - 16);

  657. 	}

  658. 	__asm__ volatile("mrs %0, basepri\n" : "=r" (basepri)::);

  659. 	if (basepri > 0 && basepri < priority) priority = basepri;

  660. 	return priority;

  661. }