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Teensy 4.1 core updated for C++20
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teensy-core-4.1/teensy3/SPIFIFO.h

306 line
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原始文件 Blame 歷史記錄 

  1. #ifndef _SPIFIFO_h_

  2. #define _SPIFIFO_h_

  3. 

  4. #include "avr_emulation.h"

  5. 

  6. #ifdef KINETISK

  7. 

  8. #if F_BUS == 120000000

  9. #define HAS_SPIFIFO

  10. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(3) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(120 / 5) * ((1+1)/2)

  11. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(2))                //(120 / 2) * ((1+0)/4) = 15 MHz

  12. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(3) | SPI_CTAR_BR(0))                //(120 / 5) * ((1+0)/2)

  13. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(3) | SPI_CTAR_BR(4) | SPI_CTAR_DBR) //(120 / 5) * ((1+1)/6)

  14. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(3) | SPI_CTAR_BR(2))                //(120 / 5) * ((1+0)/4)

  15. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(3) | SPI_CTAR_BR(4)) 		    //(120 / 5) * ((1+0)/6)

  16. 

  17. #elif F_BUS == 108000000

  18. #define HAS_SPIFIFO

  19. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(3) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(108 / 5) * ((1+1)/2) = 21.6 MHz

  20. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(2))                //(108 / 2) * ((1+0)/4) = 13.5 MHz

  21. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | SPI_CTAR_DBR) //(108 / 3) * ((1+1)/6)

  22. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(3) | SPI_CTAR_BR(4) | SPI_CTAR_DBR) //(108 / 5) * ((1+1)/6) = 7.2 MHz

  23. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(1) | SPI_CTAR_BR(4))                //(108 / 3) * ((1+0)/6) 

  24. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(5) | SPI_CTAR_BR(2)) 		    //(108 / 7) * ((1+0)/4) = 3.86 MHz

  25. 

  26. #elif F_BUS == 96000000

  27. #define HAS_SPIFIFO

  28. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0))                //(96 / 2) * ((1+0)/2)

  29. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(4) | SPI_CTAR_DBR) //(96 / 2) * ((1+1)/6)

  30. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | SPI_CTAR_DBR) //(96 / 2) * ((1+1)/8)

  31. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(1) | SPI_CTAR_BR(2))                //(96 / 3) * ((1+0)/4)

  32. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(6))                //(96 / 2) * ((1+0)/8)

  33. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(1) | SPI_CTAR_BR(6)) 		    //(96 / 3) * ((1+0)/8)

  34. 

  35. #elif F_BUS == 90000000

  36. #define HAS_SPIFIFO

  37. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0))                //(90 / 2) * ((1+0)/2) = 22.5 MHz

  38. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(4) | SPI_CTAR_DBR) //(90 / 2) * ((1+1)/6) = 15 MHz

  39. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | SPI_CTAR_DBR) //(90 / 2) * ((1+1)/8) = 11.25 MHz

  40. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(4))                //(90 / 2) * ((1+0)/6) = 7.5 MHz

  41. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(3) | SPI_CTAR_BR(4) | SPI_CTAR_DBR) //(90 / 5) * ((1+1)/6)

  42. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(1) | SPI_CTAR_BR(6)) 		    //(90 / 3) * ((1+0)/8) = 3.75 MHz

  43. 

  44. #elif F_BUS == 80000000

  45. #define HAS_SPIFIFO

  46. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0))                //(80 / 2) * ((1+0)/2) = 20 MHz

  47. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(3) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(80 / 5) * ((1+1)/2)

  48. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(5) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(80 / 7) * ((1+1)/2) = 11.42 MHz

  49. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(3) | SPI_CTAR_BR(0))                //(80 / 5) * ((1+0)/2)

  50. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(5) | SPI_CTAR_BR(0))                //(80 / 7) * ((1+0)/2) = 5.7 MHz

  51. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(3) | SPI_CTAR_BR(2)) 		    //(80 / 5) * ((1+0)/4)

  52. 

  53. #elif F_BUS == 72000000

  54. #define HAS_SPIFIFO

  55. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(72 / 3) * ((1+1)/2)

  56. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(4) | SPI_CTAR_DBR) //(72 / 2) * ((1+1)/6) = 12 MHz

  57. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(4) | SPI_CTAR_DBR) //(72 / 2) * ((1+1)/6)

  58. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | SPI_CTAR_DBR) //(72 / 3) * ((1+1)/6)

  59. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(4))                //(72 / 2) * ((1+0)/6)

  60. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(1) | SPI_CTAR_BR(4)) 		    //(72 / 3) * ((1+0)/6)

  61. 

  62. #elif F_BUS == 64000000

  63. #define HAS_SPIFIFO

  64. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(64 / 3) * ((1+1)/2) = 21.3 MHz

  65. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0))                //(64 / 2) * ((1+0)/2)

  66. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0)) 		    //(64 / 3) * ((1+0)/2) = 10.67 MHz

  67. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(2))                //(64 / 2) * ((1+0)/4)

  68. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(4))                //(64 / 2) * ((1+0)/6) = 5.3 MHz

  69. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(6)) 		    //(64 / 2) * ((1+0)/8)

  70. 

  71. #elif F_BUS == 60000000

  72. #define HAS_SPIFIFO

  73. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(60 / 3) * ((1+1)/2) = 20 MHz

  74. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0))                //(60 / 2) * ((1+0)/2) = 15 MHz

  75. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(60 / 5) * ((1+1)/2)

  76. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1))                //(60 / 2) * ((1+0)/4) = 7.5 MHz

  77. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(2) | SPI_CTAR_BR(0))                //(60 / 5) * ((1+0)/2)

  78. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(2) | SPI_CTAR_BR(2) | SPI_CTAR_DBR) //(60 / 5) * ((1+1)/6)

  79. 

  80. #elif F_BUS == 56000000

  81. #define HAS_SPIFIFO

  82. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(56 / 3) * ((1+1)/2) = 18.67

  83. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0))                //(56 / 2) * ((1+0)/2) = 14

  84. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(56 / 5) * ((1+1)/2) = 11.2

  85. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(3) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(56 / 7) * ((1+1)/2)

  86. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(2) | SPI_CTAR_BR(0))                //(56 / 5) * ((1+0)/2)

  87. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(3) | SPI_CTAR_BR(0))                //(56 / 7) * ((1+0)/2)

  88. 

  89. #elif F_BUS == 48000000

  90. #define HAS_SPIFIFO

  91. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(48 / 2) * ((1+1)/2)

  92. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(48 / 3) * ((1+1)/2)

  93. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0))                //(48 / 2) * ((1+0)/2)

  94. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(2) | SPI_CTAR_DBR) //(48 / 2) * ((1+1)/6)

  95. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1))                //(48 / 2) * ((1+0)/4)

  96. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(2))                //(48 / 2) * ((1+0)/6)

  97. 

  98. #elif F_BUS == 40000000

  99. #define HAS_SPIFIFO

  100. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(40 / 2) * ((1+1)/2) = 20

  101. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(40 / 3) * ((1+1)/2) = 13.33

  102. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0))                //(40 / 2) * ((1+0)/2) = 10

  103. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(40 / 5) * ((1+1)/2)

  104. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(3) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(40 / 7) * ((1+1)/2) = 5.71

  105. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(2) | SPI_CTAR_BR(1))                //(40 / 5) * ((1+0)/2)

  106. 

  107. #elif F_BUS == 36000000

  108. #define HAS_SPIFIFO

  109. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(36 / 2) * ((1+1)/2) = 18

  110. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(36 / 3) * ((1+1)/2) = 12

  111. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(36 / 3) * ((1+1)/2) = 12

  112. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(36 / 5) * ((1+1)/2) = 7.2

  113. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(2) | SPI_CTAR_DBR) //(36 / 2) * ((1+1)/6)

  114. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(1) | SPI_CTAR_BR(2) | SPI_CTAR_DBR) //(36 / 3) * ((1+1)/6)

  115. 

  116. #elif F_BUS == 24000000

  117. #define HAS_SPIFIFO

  118. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(24 / 2) * ((1+1)/2)  12 MHz

  119. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(24 / 2) * ((1+1)/2)  12 MHz

  120. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(24 / 2) * ((1+1)/2)

  121. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(24 / 3) * ((1+1)/2)

  122. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0))                //(24 / 2) * ((1+0)/2)

  123. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(2) | SPI_CTAR_DBR) //(24 / 2) * ((1+1)/6)

  124. 

  125. #elif F_BUS == 16000000

  126. #define HAS_SPIFIFO

  127. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | SPI_CTAR_DBR) //(16 / 2) * ((1+1)/8) = 2 MHz

  128. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | SPI_CTAR_DBR) //(16 / 2) * ((1+1)/8) = 2 MHz

  129. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | SPI_CTAR_DBR) //(16 / 2) * ((1+1)/8) = 2 MHz

  130. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | SPI_CTAR_DBR) //(16 / 2) * ((1+1)/8) = 2 MHz

  131. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | SPI_CTAR_DBR) //(16 / 2) * ((1+1)/8) = 2 MHz

  132. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | SPI_CTAR_DBR) //(16 / 2) * ((1+1)/8) = 2 MHz

  133. 

  134. #elif F_BUS == 8000000

  135. #define HAS_SPIFIFO

  136. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(8 / 2) * ((1+1)/4) = 2 MHz

  137. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(8 / 2) * ((1+1)/4) = 2 MHz

  138. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(8 / 2) * ((1+1)/4) = 2 MHz

  139. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(8 / 2) * ((1+1)/4) = 2 MHz

  140. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(8 / 2) * ((1+1)/4) = 2 MHz

  141. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(8 / 2) * ((1+1)/4) = 2 MHz

  142. 

  143. #elif F_BUS == 4000000

  144. #define HAS_SPIFIFO

  145. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 2 MHz

  146. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 2 MHz

  147. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 2 MHz

  148. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 2 MHz

  149. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 2 MHz

  150. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 2 MHz

  151. 

  152. #elif F_BUS == 2000000

  153. #define HAS_SPIFIFO

  154. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 1 MHz

  155. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 1 MHz

  156. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 1 MHz

  157. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 1 MHz

  158. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 1 MHz

  159. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 1 MHz

  160. 

  161. #endif // F_BUS

  162. 

  163. #endif // KINETISK

  164. 

  165. /*

  166. #! /usr/bin/perl

  167. $clock = 60;

  168. for $i (2, 3, 5, 7) {

  169.         for $j (0, 1) {

  170.                 for $k (2, 4, 6, 8, 16, 32) {

  171.                         $out = $clock / $i * (1 + $j) / $k;

  172.                         printf "%0.2f :  ", $out;

  173.                         print "$clock / $i * (1 + $j) / $k = $out\n";

  174.                 }

  175.         }

  176. }

  177. */

  178. 

  179. // sck = F_BUS / PBR * ((1+DBR)/BR)

  180. //  PBR = 2, 3, 5, 7

  181. //  DBR = 0, 1         -- zero preferred

  182. //  BR = 2, 4, 6, 8, 16, 32, 64, 128, 256, 512

  183. 

  184. 

  185. #ifdef HAS_SPIFIFO

  186. 

  187. #ifndef SPI_MODE0

  188. #define SPI_MODE0 0x00  // CPOL = 0, CPHA = 0

  189. #define SPI_MODE1 0x04  // CPOL = 0, CPHA = 1

  190. #define SPI_MODE2 0x08  // CPOL = 1, CPHA = 0

  191. #define SPI_MODE3 0x0C  // CPOL = 1, CPHA = 1

  192. #endif

  193. 

  194. #define SPI_CONTINUE 1

  195. 

  196. class SPIFIFOclass

  197. {

  198. public:

  199. 	inline void begin(uint8_t pin, uint32_t speed, uint32_t mode=SPI_MODE0) __attribute__((always_inline)) {

  200. 		uint32_t p, ctar = speed;

  201. 		SIM_SCGC6 |= SIM_SCGC6_SPI0;

  202. 

  203. 		KINETISK_SPI0.MCR = SPI_MCR_MSTR | SPI_MCR_MDIS | SPI_MCR_HALT | SPI_MCR_PCSIS(0x1F);

  204. 		if (mode & 0x08) ctar |= SPI_CTAR_CPOL;

  205. 		if (mode & 0x04) {

  206. 			ctar |= SPI_CTAR_CPHA;

  207. 			ctar |= (ctar & 0x0F) << 8;

  208. 		} else {

  209. 			ctar |= (ctar & 0x0F) << 12;

  210. 		}

  211. 		KINETISK_SPI0.CTAR0 = ctar | SPI_CTAR_FMSZ(7);

  212. 		KINETISK_SPI0.CTAR1 = ctar | SPI_CTAR_FMSZ(15);

  213. 		if (pin == 10) {         // PTC4

  214. 			CORE_PIN10_CONFIG = PORT_PCR_MUX(2);

  215. 			p = 0x01;

  216. 		} else if (pin == 2) {   // PTD0

  217. 			CORE_PIN2_CONFIG = PORT_PCR_MUX(2);

  218. 			p = 0x01;

  219. 		} else if (pin == 9) {   // PTC3

  220. 			CORE_PIN9_CONFIG = PORT_PCR_MUX(2);

  221. 			p = 0x02;

  222. 		} else if (pin == 6) {   // PTD4

  223. 			CORE_PIN6_CONFIG = PORT_PCR_MUX(2);

  224. 			p = 0x02;

  225. 		} else if (pin == 20) {  // PTD5

  226. 			CORE_PIN20_CONFIG = PORT_PCR_MUX(2);

  227. 			p = 0x04;

  228. 		} else if (pin == 23) {  // PTC2

  229. 			CORE_PIN23_CONFIG = PORT_PCR_MUX(2);

  230. 			p = 0x04;

  231. 		} else if (pin == 21) {  // PTD6

  232. 			CORE_PIN21_CONFIG = PORT_PCR_MUX(2);

  233. 			p = 0x08;

  234. 		} else if (pin == 22) {  // PTC1

  235. 			CORE_PIN22_CONFIG = PORT_PCR_MUX(2);

  236. 			p = 0x08;

  237. 		} else if (pin == 15) {  // PTC0

  238. 			CORE_PIN15_CONFIG = PORT_PCR_MUX(2);

  239. 			p = 0x10;

  240. #if defined(__MK64FX512__) || defined(__MK66FX1M0__)

  241. 		} else if (pin == 26) {  

  242. 			CORE_PIN26_CONFIG = PORT_PCR_MUX(2);

  243. 			p = 0x01;

  244. #endif

  245. 		} else {

  246. 			reg = portOutputRegister(pin);

  247. 			pinMode(pin, OUTPUT);

  248. 			*reg = 1;

  249. 			p = 0;

  250. 		}

  251. 		pcs = p;

  252. 		clear();

  253. 		SPCR.enable_pins();

  254. 	}

  255. 	inline void write(uint32_t b, uint32_t cont=0) __attribute__((always_inline)) {

  256. 		uint32_t pcsbits = pcs << 16;

  257. 		if (pcsbits) {

  258. 			KINETISK_SPI0.PUSHR = (b & 0xFF) | pcsbits | (cont ? SPI_PUSHR_CONT : 0);

  259. 			while (((KINETISK_SPI0.SR) & (15 << 12)) > (3 << 12)) ; // wait if FIFO full

  260. 		} else {

  261. 			*reg = 0;

  262. 			KINETISK_SPI0.SR = SPI_SR_EOQF;

  263. 			KINETISK_SPI0.PUSHR = (b & 0xFF) | (cont ? 0 : SPI_PUSHR_EOQ);

  264. 			if (cont) {

  265. 				while (((KINETISK_SPI0.SR) & (15 << 12)) > (3 << 12)) ;

  266. 			} else {

  267. 				while (!(KINETISK_SPI0.SR & SPI_SR_EOQF)) ;

  268. 				*reg = 1;

  269. 			}

  270. 		}

  271. 	}

  272. 	inline void write16(uint32_t b, uint32_t cont=0) __attribute__((always_inline)) {

  273. 		uint32_t pcsbits = pcs << 16;

  274. 		if (pcsbits) {

  275. 			KINETISK_SPI0.PUSHR = (b & 0xFFFF) | (pcs << 16) |

  276. 				(cont ? SPI_PUSHR_CONT : 0) | SPI_PUSHR_CTAS(1);

  277. 			while (((KINETISK_SPI0.SR) & (15 << 12)) > (3 << 12)) ;

  278. 		} else {

  279. 			*reg = 0;

  280. 			KINETISK_SPI0.SR = SPI_SR_EOQF;

  281. 			KINETISK_SPI0.PUSHR = (b & 0xFFFF) | (cont ? 0 : SPI_PUSHR_EOQ) | SPI_PUSHR_CTAS(1);

  282. 			if (cont) {

  283. 				while (((KINETISK_SPI0.SR) & (15 << 12)) > (3 << 12)) ;

  284. 			} else {

  285. 				while (!(KINETISK_SPI0.SR & SPI_SR_EOQF)) ;

  286. 				*reg = 1;

  287. 			}

  288. 		}

  289. 	}

  290. 	inline uint32_t read(void) __attribute__((always_inline)) {

  291. 		while ((KINETISK_SPI0.SR & (15 << 4)) == 0) ;  // TODO, could wait forever

  292. 		return KINETISK_SPI0.POPR;

  293. 	}

  294. 	inline void clear(void) __attribute__((always_inline)) {

  295. 		KINETISK_SPI0.MCR = SPI_MCR_MSTR | SPI_MCR_PCSIS(0x1F) | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;

  296. 	}

  297. private:

  298. 	static uint8_t pcs;

  299. 	static volatile uint8_t *reg;

  300. };

  301. extern SPIFIFOclass SPIFIFO;

  302. 

  303. #endif // HAS_SPIFIFO

  304. 

  305. #endif