Teensy 4.1 core updated for C++20
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  1. /* Teensyduino Core Library
  2. * http://www.pjrc.com/teensy/
  3. * Copyright (c) 2013 PJRC.COM, LLC.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * 1. The above copyright notice and this permission notice shall be
  14. * included in all copies or substantial portions of the Software.
  15. *
  16. * 2. If the Software is incorporated into a build system that allows
  17. * selection among a list of target devices, then similar target
  18. * devices manufactured by PJRC.COM must be included in the list of
  19. * target devices and selectable in the same manner.
  20. *
  21. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  24. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  25. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  26. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  27. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  28. * SOFTWARE.
  29. */
  30. #include "core_pins.h"
  31. //#include "HardwareSerial.h"
  32. static uint8_t calibrating;
  33. static uint8_t analog_right_shift = 0;
  34. static uint8_t analog_config_bits = 10;
  35. static uint8_t analog_num_average = 4;
  36. static uint8_t analog_reference_internal = 0;
  37. // the alternate clock is connected to OSCERCLK (16 MHz).
  38. // datasheet says ADC clock should be 2 to 12 MHz for 16 bit mode
  39. // datasheet says ADC clock should be 1 to 18 MHz for 8-12 bit mode
  40. #if F_BUS == 120000000
  41. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(3) + ADC_CFG1_ADICLK(1) // 7.5 MHz
  42. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 15 MHz
  43. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 15 MHz
  44. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 15 MHz
  45. #elif F_BUS == 108000000
  46. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(3) + ADC_CFG1_ADICLK(1) // 7 MHz
  47. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 14 MHz
  48. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 14 MHz
  49. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 14 MHz
  50. #elif F_BUS == 96000000
  51. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 12 MHz
  52. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 12 MHz
  53. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 12 MHz
  54. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 24 MHz
  55. #elif F_BUS == 90000000
  56. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 11.25 MHz
  57. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 11.25 MHz
  58. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 11.25 MHz
  59. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 22.5 MHz
  60. #elif F_BUS == 80000000
  61. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 10 MHz
  62. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 10 MHz
  63. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 10 MHz
  64. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 20 MHz
  65. #elif F_BUS == 72000000
  66. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 9 MHz
  67. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 18 MHz
  68. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 18 MHz
  69. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 18 MHz
  70. #elif F_BUS == 64000000
  71. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 8 MHz
  72. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 16 MHz
  73. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 16 MHz
  74. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 16 MHz
  75. #elif F_BUS == 60000000
  76. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 7.5 MHz
  77. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz
  78. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz
  79. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz
  80. #elif F_BUS == 56000000 || F_BUS == 54000000
  81. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 7 MHz
  82. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 14 MHz
  83. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 14 MHz
  84. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 14 MHz
  85. #elif F_BUS == 48000000
  86. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 12 MHz
  87. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 12 MHz
  88. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 12 MHz
  89. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 24 MHz
  90. #elif F_BUS == 40000000
  91. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 10 MHz
  92. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 10 MHz
  93. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 10 MHz
  94. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 20 MHz
  95. #elif F_BUS == 36000000
  96. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 9 MHz
  97. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 18 MHz
  98. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 18 MHz
  99. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 18 MHz
  100. #elif F_BUS == 24000000
  101. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(0) // 12 MHz
  102. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(0) // 12 MHz
  103. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(0) // 12 MHz
  104. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 24 MHz
  105. #elif F_BUS == 16000000
  106. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
  107. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
  108. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
  109. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 16 MHz
  110. #elif F_BUS == 8000000
  111. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
  112. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
  113. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
  114. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
  115. #elif F_BUS == 4000000
  116. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz
  117. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz
  118. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz
  119. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz
  120. #elif F_BUS == 2000000
  121. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz
  122. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz
  123. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz
  124. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz
  125. #else
  126. #error "F_BUS must be 120, 108, 96, 90, 80, 72, 64, 60, 56, 54, 48, 40, 36, 24, 4 or 2 MHz"
  127. #endif
  128. void analog_init(void)
  129. {
  130. uint32_t num;
  131. #if defined(__MK20DX128__) || defined(__MK20DX256__)
  132. VREF_TRM = 0x60;
  133. VREF_SC = 0xE1; // enable 1.2 volt ref
  134. #endif
  135. if (analog_config_bits == 8) {
  136. ADC0_CFG1 = ADC_CFG1_8BIT + ADC_CFG1_MODE(0);
  137. ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3);
  138. #ifdef HAS_KINETIS_ADC1
  139. ADC1_CFG1 = ADC_CFG1_8BIT + ADC_CFG1_MODE(0);
  140. ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3);
  141. #endif
  142. } else if (analog_config_bits == 10) {
  143. ADC0_CFG1 = ADC_CFG1_10BIT + ADC_CFG1_MODE(2) + ADC_CFG1_ADLSMP;
  144. ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3);
  145. #ifdef HAS_KINETIS_ADC1
  146. ADC1_CFG1 = ADC_CFG1_10BIT + ADC_CFG1_MODE(2) + ADC_CFG1_ADLSMP;
  147. ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3);
  148. #endif
  149. } else if (analog_config_bits == 12) {
  150. ADC0_CFG1 = ADC_CFG1_12BIT + ADC_CFG1_MODE(1) + ADC_CFG1_ADLSMP;
  151. ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2);
  152. #ifdef HAS_KINETIS_ADC1
  153. ADC1_CFG1 = ADC_CFG1_12BIT + ADC_CFG1_MODE(1) + ADC_CFG1_ADLSMP;
  154. ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2);
  155. #endif
  156. } else {
  157. ADC0_CFG1 = ADC_CFG1_16BIT + ADC_CFG1_MODE(3) + ADC_CFG1_ADLSMP;
  158. ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2);
  159. #ifdef HAS_KINETIS_ADC1
  160. ADC1_CFG1 = ADC_CFG1_16BIT + ADC_CFG1_MODE(3) + ADC_CFG1_ADLSMP;
  161. ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2);
  162. #endif
  163. }
  164. #if defined(__MK20DX128__)
  165. if (analog_reference_internal) {
  166. ADC0_SC2 = ADC_SC2_REFSEL(1); // 1.2V ref
  167. } else {
  168. ADC0_SC2 = ADC_SC2_REFSEL(0); // vcc/ext ref
  169. }
  170. #elif defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__)
  171. if (analog_reference_internal) {
  172. ADC0_SC2 = ADC_SC2_REFSEL(1); // 1.2V ref
  173. ADC1_SC2 = ADC_SC2_REFSEL(1); // 1.2V ref
  174. } else {
  175. ADC0_SC2 = ADC_SC2_REFSEL(0); // vcc/ext ref
  176. ADC1_SC2 = ADC_SC2_REFSEL(0); // vcc/ext ref
  177. }
  178. #elif defined(__MKL26Z64__)
  179. if (analog_reference_internal) {
  180. ADC0_SC2 = ADC_SC2_REFSEL(0); // external AREF
  181. } else {
  182. ADC0_SC2 = ADC_SC2_REFSEL(1); // vcc
  183. }
  184. #endif
  185. num = analog_num_average;
  186. if (num <= 1) {
  187. ADC0_SC3 = ADC_SC3_CAL; // begin cal
  188. #ifdef HAS_KINETIS_ADC1
  189. ADC1_SC3 = ADC_SC3_CAL; // begin cal
  190. #endif
  191. } else if (num <= 4) {
  192. ADC0_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(0);
  193. #ifdef HAS_KINETIS_ADC1
  194. ADC1_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(0);
  195. #endif
  196. } else if (num <= 8) {
  197. ADC0_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(1);
  198. #ifdef HAS_KINETIS_ADC1
  199. ADC1_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(1);
  200. #endif
  201. } else if (num <= 16) {
  202. ADC0_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(2);
  203. #ifdef HAS_KINETIS_ADC1
  204. ADC1_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(2);
  205. #endif
  206. } else {
  207. ADC0_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(3);
  208. #ifdef HAS_KINETIS_ADC1
  209. ADC1_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(3);
  210. #endif
  211. }
  212. calibrating = 1;
  213. }
  214. static void wait_for_cal(void)
  215. {
  216. uint16_t sum;
  217. //serial_print("wait_for_cal\n");
  218. #if defined(HAS_KINETIS_ADC0) && defined(HAS_KINETIS_ADC1)
  219. while ((ADC0_SC3 & ADC_SC3_CAL) || (ADC1_SC3 & ADC_SC3_CAL)) {
  220. // wait
  221. }
  222. #elif defined(HAS_KINETIS_ADC0)
  223. while (ADC0_SC3 & ADC_SC3_CAL) {
  224. // wait
  225. }
  226. #endif
  227. __disable_irq();
  228. if (calibrating) {
  229. //serial_print("\n");
  230. sum = ADC0_CLPS + ADC0_CLP4 + ADC0_CLP3 + ADC0_CLP2 + ADC0_CLP1 + ADC0_CLP0;
  231. sum = (sum / 2) | 0x8000;
  232. ADC0_PG = sum;
  233. //serial_print("ADC0_PG = ");
  234. //serial_phex16(sum);
  235. //serial_print("\n");
  236. sum = ADC0_CLMS + ADC0_CLM4 + ADC0_CLM3 + ADC0_CLM2 + ADC0_CLM1 + ADC0_CLM0;
  237. sum = (sum / 2) | 0x8000;
  238. ADC0_MG = sum;
  239. //serial_print("ADC0_MG = ");
  240. //serial_phex16(sum);
  241. //serial_print("\n");
  242. #ifdef HAS_KINETIS_ADC1
  243. sum = ADC1_CLPS + ADC1_CLP4 + ADC1_CLP3 + ADC1_CLP2 + ADC1_CLP1 + ADC1_CLP0;
  244. sum = (sum / 2) | 0x8000;
  245. ADC1_PG = sum;
  246. sum = ADC1_CLMS + ADC1_CLM4 + ADC1_CLM3 + ADC1_CLM2 + ADC1_CLM1 + ADC1_CLM0;
  247. sum = (sum / 2) | 0x8000;
  248. ADC1_MG = sum;
  249. #endif
  250. calibrating = 0;
  251. }
  252. __enable_irq();
  253. }
  254. // ADCx_SC2[REFSEL] bit selects the voltage reference sources for ADC.
  255. // VREFH/VREFL - connected as the primary reference option
  256. // 1.2 V VREF_OUT - connected as the VALT reference option
  257. #if defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__)
  258. #define DEFAULT 0
  259. #define INTERNAL 2
  260. #define INTERNAL1V2 2
  261. #define INTERNAL1V1 2
  262. #define EXTERNAL 0
  263. #elif defined(__MKL26Z64__)
  264. #define DEFAULT 0
  265. #define INTERNAL 0
  266. #define EXTERNAL 1
  267. #endif
  268. void analogReference(uint8_t type)
  269. {
  270. if (type) {
  271. // internal reference requested
  272. if (!analog_reference_internal) {
  273. analog_reference_internal = 1;
  274. if (calibrating) {
  275. ADC0_SC3 = 0; // cancel cal
  276. #ifdef HAS_KINETIS_ADC1
  277. ADC1_SC3 = 0; // cancel cal
  278. #endif
  279. }
  280. analog_init();
  281. }
  282. } else {
  283. // vcc or external reference requested
  284. if (analog_reference_internal) {
  285. analog_reference_internal = 0;
  286. if (calibrating) {
  287. ADC0_SC3 = 0; // cancel cal
  288. #ifdef HAS_KINETIS_ADC1
  289. ADC1_SC3 = 0; // cancel cal
  290. #endif
  291. }
  292. analog_init();
  293. }
  294. }
  295. }
  296. void analogReadRes(unsigned int bits)
  297. {
  298. unsigned int config;
  299. if (bits >= 13) {
  300. if (bits > 16) bits = 16;
  301. config = 16;
  302. } else if (bits >= 11) {
  303. config = 12;
  304. } else if (bits >= 9) {
  305. config = 10;
  306. } else {
  307. config = 8;
  308. }
  309. analog_right_shift = config - bits;
  310. if (config != analog_config_bits) {
  311. analog_config_bits = config;
  312. if (calibrating) ADC0_SC3 = 0; // cancel cal
  313. analog_init();
  314. }
  315. }
  316. void analogReadAveraging(unsigned int num)
  317. {
  318. if (calibrating) wait_for_cal();
  319. if (num <= 1) {
  320. num = 0;
  321. ADC0_SC3 = 0;
  322. } else if (num <= 4) {
  323. num = 4;
  324. ADC0_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(0);
  325. } else if (num <= 8) {
  326. num = 8;
  327. ADC0_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(1);
  328. } else if (num <= 16) {
  329. num = 16;
  330. ADC0_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(2);
  331. } else {
  332. num = 32;
  333. ADC0_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(3);
  334. }
  335. analog_num_average = num;
  336. }
  337. // The SC1A register is used for both software and hardware trigger modes of operation.
  338. #if defined(__MK20DX128__)
  339. static const uint8_t channel2sc1a[] = {
  340. 5, 14, 8, 9, 13, 12, 6, 7, 15, 4,
  341. 0, 19, 3, 21, 26, 22, 23
  342. };
  343. #elif defined(__MK20DX256__)
  344. static const uint8_t channel2sc1a[] = {
  345. 5, 14, 8, 9, 13, 12, 6, 7, 15, 4,
  346. 0, 19, 3, 19+128, 26, 18+128, 23,
  347. 5+192, 5+128, 4+128, 6+128, 7+128, 4+192
  348. // +64 -> use muxA
  349. // +128 -> use ADC1
  350. // A15 26 E1 ADC1_SE5a 5+64
  351. // A16 27 C9 ADC1_SE5b 5
  352. // A17 28 C8 ADC1_SE4b 4
  353. // A18 29 C10 ADC1_SE6b 6
  354. // A19 30 C11 ADC1_SE7b 7
  355. // A20 31 E0 ADC1_SE4a 4+64
  356. };
  357. #elif defined(__MKL26Z64__)
  358. static const uint8_t channel2sc1a[] = {
  359. 5, 14, 8, 9, 13, 12, 6, 7, 15, 11,
  360. 0, 4+64, 23, 26, 27
  361. };
  362. #elif defined(__MK64FX512__) || defined(__MK66FX1M0__)
  363. static const uint8_t channel2sc1a[] = {
  364. 5, 14, 8, 9, 13, 12, 6, 7, 15, 4, // A0-A9
  365. 3, 19+128, // A10-A11
  366. // A10 ADC1_DP0/ADC0_DP3
  367. // A11 ADC1_DM0/ADC0_DM3
  368. 14+128, 15+128, 17, 18, 4+128, 5+128, 6+128, 7+128, 17+128, // A12-A20
  369. // A12 PTB10 ADC1_SE14
  370. // A13 PTB11 ADC1_SE15
  371. // A14 PTE24 ADC0_SE17
  372. // A15 PTE25 ADC0_SE18
  373. // A16 PTC8 ADC1_SE4b
  374. // A17 PTC9 ADC1_SE5b
  375. // A18 PTC10 ADC1_SE6b
  376. // A19 PTC11 ADC1_SE7b
  377. // A20 PTA17 ADC1_SE17
  378. 23, 23+128, 26, 18+128 // A21-A22, temp sensor, vref
  379. // A21 DAC0 ADC0_SE23
  380. // A22 DAC1 ADC1_SE23
  381. };
  382. #endif
  383. // TODO: perhaps this should store the NVIC priority, so it works recursively?
  384. static volatile uint8_t analogReadBusyADC0 = 0;
  385. #ifdef HAS_KINETIS_ADC1
  386. static volatile uint8_t analogReadBusyADC1 = 0;
  387. #endif
  388. int analogRead(uint8_t pin)
  389. {
  390. int result;
  391. uint8_t index, channel;
  392. //serial_phex(pin);
  393. //serial_print(" ");
  394. #if defined(__MK20DX128__)
  395. if (pin <= 13) {
  396. index = pin; // 0-13 refer to A0-A13
  397. } else if (pin <= 23) {
  398. index = pin - 14; // 14-23 are A0-A9
  399. } else if (pin >= 34 && pin <= 40) {
  400. index = pin - 24; // 34-37 are A10-A13, 38 is temp sensor,
  401. // 39 is vref, 40 is unused analog pin
  402. } else {
  403. return 0;
  404. }
  405. #elif defined(__MK20DX256__)
  406. if (pin <= 13) {
  407. index = pin; // 0-13 refer to A0-A13
  408. } else if (pin <= 23) {
  409. index = pin - 14; // 14-23 are A0-A9
  410. } else if (pin >= 26 && pin <= 31) {
  411. index = pin - 9; // 26-31 are A15-A20
  412. } else if (pin >= 34 && pin <= 40) {
  413. index = pin - 24; // 34-37 are A10-A13, 38 is temp sensor,
  414. // 39 is vref, 40 is A14
  415. } else {
  416. return 0;
  417. }
  418. #elif defined(__MK64FX512__) || defined(__MK66FX1M0__)
  419. if (pin <= 13) {
  420. index = pin; // 0-13 refer to A0-A13
  421. } else if (pin <= 23) {
  422. index = pin - 14; // 14-23 are A0-A9
  423. } else if (pin >= 31 && pin <= 39) {
  424. index = pin - 19; // 31-39 are A12-A20
  425. } else if (pin >= 40 && pin <= 41) {
  426. index = pin - 30; // 40-41 are A10-A11
  427. } else if (pin >= 42 && pin <= 45) {
  428. index = pin - 21; // 42-43 are A21-A22, 44 is temp sensor, 45 is vref
  429. } else {
  430. return 0;
  431. }
  432. #elif defined(__MKL26Z64__)
  433. if (pin <= 12) {
  434. index = pin; // 0-12 refer to A0-A12
  435. } else if (pin >= 14 && pin <= 26) {
  436. index = pin - 14; // 14-26 are A0-A12
  437. } else if (pin >= 38 && pin <= 39) {
  438. index = pin - 25; // 38=temperature
  439. // 39=bandgap ref (PMC_REGSC |= PMC_REGSC_BGBE)
  440. } else {
  441. return 0;
  442. }
  443. #endif
  444. //serial_phex(index);
  445. //serial_print(" ");
  446. channel = channel2sc1a[index];
  447. //serial_phex(channel);
  448. //serial_print(" ");
  449. //serial_print("analogRead");
  450. //return 0;
  451. if (calibrating) wait_for_cal();
  452. //pin = 5; // PTD1/SE5b, pin 14, analog 0
  453. #ifdef HAS_KINETIS_ADC1
  454. if (channel & 0x80) goto beginADC1;
  455. #endif
  456. __disable_irq();
  457. startADC0:
  458. //serial_print("startADC0\n");
  459. #if defined(__MKL26Z64__)
  460. if (channel & 0x40) {
  461. ADC0_CFG2 &= ~ADC_CFG2_MUXSEL;
  462. channel &= 0x3F;
  463. } else {
  464. ADC0_CFG2 |= ADC_CFG2_MUXSEL;
  465. }
  466. #endif
  467. ADC0_SC1A = channel;
  468. analogReadBusyADC0 = 1;
  469. __enable_irq();
  470. while (1) {
  471. __disable_irq();
  472. if ((ADC0_SC1A & ADC_SC1_COCO)) {
  473. result = ADC0_RA;
  474. analogReadBusyADC0 = 0;
  475. __enable_irq();
  476. result >>= analog_right_shift;
  477. return result;
  478. }
  479. // detect if analogRead was used from an interrupt
  480. // if so, our analogRead got canceled, so it must
  481. // be restarted.
  482. if (!analogReadBusyADC0) goto startADC0;
  483. __enable_irq();
  484. yield();
  485. }
  486. #ifdef HAS_KINETIS_ADC1
  487. beginADC1:
  488. __disable_irq();
  489. startADC1:
  490. //serial_print("startADC1\n");
  491. // ADC1_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b.
  492. if (channel & 0x40) {
  493. ADC1_CFG2 &= ~ADC_CFG2_MUXSEL;
  494. } else {
  495. ADC1_CFG2 |= ADC_CFG2_MUXSEL;
  496. }
  497. ADC1_SC1A = channel & 0x3F;
  498. analogReadBusyADC1 = 1;
  499. __enable_irq();
  500. while (1) {
  501. __disable_irq();
  502. if ((ADC1_SC1A & ADC_SC1_COCO)) {
  503. result = ADC1_RA;
  504. analogReadBusyADC1 = 0;
  505. __enable_irq();
  506. result >>= analog_right_shift;
  507. return result;
  508. }
  509. // detect if analogRead was used from an interrupt
  510. // if so, our analogRead got canceled, so it must
  511. // be restarted.
  512. if (!analogReadBusyADC1) goto startADC1;
  513. __enable_irq();
  514. yield();
  515. }
  516. #endif
  517. }
  518. void analogWriteDAC0(int val)
  519. {
  520. #if defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__)
  521. SIM_SCGC2 |= SIM_SCGC2_DAC0;
  522. if (analog_reference_internal) {
  523. DAC0_C0 = DAC_C0_DACEN; // 1.2V ref is DACREF_1
  524. } else {
  525. DAC0_C0 = DAC_C0_DACEN | DAC_C0_DACRFS; // 3.3V VDDA is DACREF_2
  526. }
  527. if (val < 0) val = 0; // TODO: saturate instruction?
  528. else if (val > 4095) val = 4095;
  529. *(int16_t *)&(DAC0_DAT0L) = val;
  530. #elif defined(__MKL26Z64__)
  531. SIM_SCGC6 |= SIM_SCGC6_DAC0;
  532. if (analog_reference_internal == 0) {
  533. // use 3.3V VDDA power as the reference (this is the default)
  534. DAC0_C0 = DAC_C0_DACEN | DAC_C0_DACRFS | DAC_C0_DACSWTRG; // 3.3V VDDA
  535. } else {
  536. // use whatever voltage is on the AREF pin
  537. DAC0_C0 = DAC_C0_DACEN | DAC_C0_DACSWTRG; // 3.3V VDDA
  538. }
  539. if (val < 0) val = 0;
  540. else if (val > 4095) val = 4095;
  541. *(int16_t *)&(DAC0_DAT0L) = val;
  542. #endif
  543. }
  544. #if defined(__MK64FX512__) || defined(__MK66FX1M0__)
  545. void analogWriteDAC1(int val)
  546. {
  547. SIM_SCGC2 |= SIM_SCGC2_DAC1;
  548. if (analog_reference_internal) {
  549. DAC1_C0 = DAC_C0_DACEN; // 1.2V ref is DACREF_1
  550. } else {
  551. DAC1_C0 = DAC_C0_DACEN | DAC_C0_DACRFS; // 3.3V VDDA is DACREF_2
  552. }
  553. if (val < 0) val = 0; // TODO: saturate instruction?
  554. else if (val > 4095) val = 4095;
  555. *(int16_t *)&(DAC1_DAT0L) = val;
  556. }
  557. #endif